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Remove wrapper rtw_udelay_os()

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This wrapper is a simple call to udelay(). Remove it.

Link: https://lore.kernel.org/r/20210805192644.15978-4-Larry.Finger@lwfinger.net
This commit is contained in:
Larry Finger 2021-08-05 14:26:42 -05:00 committed by Carlos Garcés
parent 7f8451a86e
commit a5adfa895b
14 changed files with 37 additions and 94 deletions
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2
core/efuse/rtw_efuse.c
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@ -1985,7 +1985,7 @@ ReadEFuseByte(
/* This fix the problem that Efuse read error in high temperature condition. */ /* This fix the problem that Efuse read error in high temperature condition. */
/* Designer says that there shall be some delay after ready bit is set, or the */ /* Designer says that there shall be some delay after ready bit is set, or the */
/* result will always stay on last data we read. */ /* result will always stay on last data we read. */
rtw_udelay_os(50); udelay(50);
value32 = rtw_read32(Adapter, EFUSE_CTRL); value32 = rtw_read32(Adapter, EFUSE_CTRL);
*pbuf = (u8)(value32 & 0xff); *pbuf = (u8)(value32 & 0xff);

12
core/rtw_eeprom.c
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@ -22,7 +22,7 @@ void up_clk(_adapter *padapter, u16 *x)
{ {
*x = *x | _EESK; *x = *x | _EESK;
rtw_write8(padapter, EE_9346CR, (u8)*x); rtw_write8(padapter, EE_9346CR, (u8)*x);
rtw_udelay_os(CLOCK_RATE); udelay(CLOCK_RATE);
} }
@ -31,7 +31,7 @@ void down_clk(_adapter *padapter, u16 *x)
{ {
*x = *x & ~_EESK; *x = *x & ~_EESK;
rtw_write8(padapter, EE_9346CR, (u8)*x); rtw_write8(padapter, EE_9346CR, (u8)*x);
rtw_udelay_os(CLOCK_RATE); udelay(CLOCK_RATE);
} }
void shift_out_bits(_adapter *padapter, u16 data, u16 count) void shift_out_bits(_adapter *padapter, u16 data, u16 count)
@ -54,7 +54,7 @@ void shift_out_bits(_adapter *padapter, u16 data, u16 count)
goto out; goto out;
} }
rtw_write8(padapter, EE_9346CR, (u8)x); rtw_write8(padapter, EE_9346CR, (u8)x);
rtw_udelay_os(CLOCK_RATE); udelay(CLOCK_RATE);
up_clk(padapter, &x); up_clk(padapter, &x);
down_clk(padapter, &x); down_clk(padapter, &x);
mask = mask >> 1; mask = mask >> 1;
@ -106,10 +106,10 @@ void standby(_adapter *padapter)
x &= ~(_EECS | _EESK); x &= ~(_EECS | _EESK);
rtw_write8(padapter, EE_9346CR, x); rtw_write8(padapter, EE_9346CR, x);
rtw_udelay_os(CLOCK_RATE); udelay(CLOCK_RATE);
x |= _EECS; x |= _EECS;
rtw_write8(padapter, EE_9346CR, x); rtw_write8(padapter, EE_9346CR, x);
rtw_udelay_os(CLOCK_RATE); udelay(CLOCK_RATE);
} }
u16 wait_eeprom_cmd_done(_adapter *padapter) u16 wait_eeprom_cmd_done(_adapter *padapter)
@ -123,7 +123,7 @@ u16 wait_eeprom_cmd_done(_adapter *padapter)
res = _TRUE; res = _TRUE;
goto exit; goto exit;
} }
rtw_udelay_os(CLOCK_RATE); udelay(CLOCK_RATE);
} }
exit: exit:
return res; return res;

2
core/rtw_xmit.c
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@ -4418,7 +4418,7 @@ s32 rtw_monitor_xmit_entry(struct sk_buff *skb, struct net_device *ndev)
#endif #endif
pmgntframe = alloc_mgtxmitframe(pxmitpriv); pmgntframe = alloc_mgtxmitframe(pxmitpriv);
if (pmgntframe == NULL) { if (pmgntframe == NULL) {
rtw_udelay_os(500); udelay(500);
goto fail; goto fail;
} }

6
hal/HalPwrSeqCmd.c
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@ -132,7 +132,7 @@ u8 HalPwrSeqCmdParsing(
if (value == (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd))) if (value == (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd)))
bPollingBit = _TRUE; bPollingBit = _TRUE;
else else
rtw_udelay_os(10); udelay(10);
if (pollingCount++ > maxPollingCnt) { if (pollingCount++ > maxPollingCnt) {
RTW_ERR("HalPwrSeqCmdParsing: Fail to polling Offset[%#x]=%02x\n", offset, value); RTW_ERR("HalPwrSeqCmdParsing: Fail to polling Offset[%#x]=%02x\n", offset, value);
@ -163,9 +163,9 @@ u8 HalPwrSeqCmdParsing(
case PWR_CMD_DELAY: case PWR_CMD_DELAY:
if (GET_PWR_CFG_VALUE(PwrCfgCmd) == PWRSEQ_DELAY_US) if (GET_PWR_CFG_VALUE(PwrCfgCmd) == PWRSEQ_DELAY_US)
rtw_udelay_os(GET_PWR_CFG_OFFSET(PwrCfgCmd)); udelay(GET_PWR_CFG_OFFSET(PwrCfgCmd));
else else
rtw_udelay_os(GET_PWR_CFG_OFFSET(PwrCfgCmd) * 1000); udelay(GET_PWR_CFG_OFFSET(PwrCfgCmd) * 1000);
break; break;
case PWR_CMD_END: case PWR_CMD_END:

4
hal/hal_com.c
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@ -9016,7 +9016,7 @@ bool rtw_read_from_frame_mask(_adapter *adapter, u8 idx)
do { do {
tmp = rtw_read8(adapter, REG_RXPKTBUF_CTRL); tmp = rtw_read8(adapter, REG_RXPKTBUF_CTRL);
rtw_udelay_os(2); udelay(2);
count++; count++;
} while (!tmp && count < 100); } while (!tmp && count < 100);
@ -9127,7 +9127,7 @@ bool rtw_write_to_frame_mask(_adapter *adapter, u8 idx,
count = 0; count = 0;
do { do {
tmp = rtw_read8(adapter, REG_RXPKTBUF_CTRL); tmp = rtw_read8(adapter, REG_RXPKTBUF_CTRL);
rtw_udelay_os(2); udelay(2);
count++; count++;
} while (tmp && count < 100); } while (tmp && count < 100);

28
hal/hal_com_phycfg.c
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@ -4216,11 +4216,11 @@ phy_ConfigBBWithParaFile(
else if (u4bRegOffset == 0xfc) else if (u4bRegOffset == 0xfc)
mdelay(1); mdelay(1);
else if (u4bRegOffset == 0xfb) else if (u4bRegOffset == 0xfb)
rtw_udelay_os(50); udelay(50);
else if (u4bRegOffset == 0xfa) else if (u4bRegOffset == 0xfa)
rtw_udelay_os(5); udelay(5);
else if (u4bRegOffset == 0xf9) else if (u4bRegOffset == 0xf9)
rtw_udelay_os(1); udelay(1);
/* Get 2nd hex value as register value. */ /* Get 2nd hex value as register value. */
szLine += u4bMove; szLine += u4bMove;
@ -4232,7 +4232,7 @@ phy_ConfigBBWithParaFile(
pHalData->odmpriv.rf_calibrate_info.rega24 = u4bRegValue; pHalData->odmpriv.rf_calibrate_info.rega24 = u4bRegValue;
/* Add 1us delay between BB/RF register setting. */ /* Add 1us delay between BB/RF register setting. */
rtw_udelay_os(1); udelay(1);
} }
} }
} }
@ -4564,11 +4564,11 @@ phy_ConfigBBWithMpParaFile(
else if (u4bRegOffset == 0xfc) else if (u4bRegOffset == 0xfc)
mdelay(1); mdelay(1);
else if (u4bRegOffset == 0xfb) else if (u4bRegOffset == 0xfb)
rtw_udelay_os(50); udelay(50);
else if (u4bRegOffset == 0xfa) else if (u4bRegOffset == 0xfa)
rtw_udelay_os(5); udelay(5);
else if (u4bRegOffset == 0xf9) else if (u4bRegOffset == 0xf9)
rtw_udelay_os(1); udelay(1);
/* Get 2nd hex value as register value. */ /* Get 2nd hex value as register value. */
szLine += u4bMove; szLine += u4bMove;
@ -4577,7 +4577,7 @@ phy_ConfigBBWithMpParaFile(
phy_set_bb_reg(Adapter, u4bRegOffset, bMaskDWord, u4bRegValue); phy_set_bb_reg(Adapter, u4bRegOffset, bMaskDWord, u4bRegValue);
/* Add 1us delay between BB/RF register setting. */ /* Add 1us delay between BB/RF register setting. */
rtw_udelay_os(1); udelay(1);
} }
} }
} }
@ -4676,17 +4676,17 @@ PHY_ConfigRFWithParaFile(
} else if (u4bRegOffset == 0xfd) { } else if (u4bRegOffset == 0xfd) {
/* mdelay(5); */ /* mdelay(5); */
for (i = 0; i < 100; i++) for (i = 0; i < 100; i++)
rtw_udelay_os(MAX_STALL_TIME); udelay(MAX_STALL_TIME);
} else if (u4bRegOffset == 0xfc) { } else if (u4bRegOffset == 0xfc) {
/* mdelay(1); */ /* mdelay(1); */
for (i = 0; i < 20; i++) for (i = 0; i < 20; i++)
rtw_udelay_os(MAX_STALL_TIME); udelay(MAX_STALL_TIME);
} else if (u4bRegOffset == 0xfb) } else if (u4bRegOffset == 0xfb)
rtw_udelay_os(50); udelay(50);
else if (u4bRegOffset == 0xfa) else if (u4bRegOffset == 0xfa)
rtw_udelay_os(5); udelay(5);
else if (u4bRegOffset == 0xf9) else if (u4bRegOffset == 0xf9)
rtw_udelay_os(1); udelay(1);
else if (u4bRegOffset == 0xffff) else if (u4bRegOffset == 0xffff)
break; break;
@ -4703,7 +4703,7 @@ PHY_ConfigRFWithParaFile(
/* 0x2b 0x00808 frequency divider. */ /* 0x2b 0x00808 frequency divider. */
/* 0x2b 0x53333 */ /* 0x2b 0x53333 */
/* 0x2c 0x0000c */ /* 0x2c 0x0000c */
rtw_udelay_os(1); udelay(1);
} }
} }
} }

2
hal/hal_halmac.c
View File

@ -410,7 +410,7 @@ static void _halmac_udelay(void *p, u32 us)
{ {
/* Most hardware polling wait time < 50us) */ /* Most hardware polling wait time < 50us) */
if (us <= 50) if (us <= 50)
rtw_udelay_os(us); udelay(us);
else if (us <= 1000) else if (us <= 1000)
rtw_usleep_os(us); rtw_usleep_os(us);
else else

2
hal/hal_intf.c
View File

@ -739,7 +739,7 @@ void rtw_hal_write_rfreg(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr,
#ifdef CONFIG_PCI_HCI #ifdef CONFIG_PCI_HCI
if (!IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(padapter)) /*For N-Series IC, suggest by Jenyu*/ if (!IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(padapter)) /*For N-Series IC, suggest by Jenyu*/
rtw_udelay_os(2); udelay(2);
#endif #endif
} }
} }

4
hal/phydm/phydm_interface.c
View File

@ -615,11 +615,11 @@ void ODM_delay_us(u32 us)
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
udelay(us); udelay(us);
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
rtw_udelay_os(us); udelay(us);
#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
PlatformStallExecution(us); PlatformStallExecution(us);
#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
rtw_udelay_os(us); udelay(us);
#endif #endif
} }

4
hal/rtl8192e/rtl8192e_phycfg.c
View File

@ -140,11 +140,11 @@ phy_RFSerialRead(
phy_set_bb_reg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEdge)); phy_set_bb_reg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEdge));
phy_set_bb_reg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 | bLSSIReadEdge); phy_set_bb_reg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 | bLSSIReadEdge);
rtw_udelay_os(10);/* PlatformStallExecution(10); */ udelay(10);/* PlatformStallExecution(10); */
/* for(i=0;i<2;i++) */ /* for(i=0;i<2;i++) */
/* PlatformStallExecution(MAX_STALL_TIME); */ /* PlatformStallExecution(MAX_STALL_TIME); */
rtw_udelay_os(10);/* PlatformStallExecution(10); */ udelay(10);/* PlatformStallExecution(10); */
if (eRFPath == RF_PATH_A) if (eRFPath == RF_PATH_A)
RfPiEnable = (u1Byte)phy_query_bb_reg(Adapter, rFPGA0_XA_HSSIParameter1 | MaskforPhySet, BIT8); RfPiEnable = (u1Byte)phy_query_bb_reg(Adapter, rFPGA0_XA_HSSIParameter1 | MaskforPhySet, BIT8);

8
hal/rtl8192e/rtl8192e_rf6052.c
View File

@ -94,18 +94,18 @@ phy_RF6052_Config_ParaFile_8192E(
/*----Set RF_ENV enable----*/ /*----Set RF_ENV enable----*/
phy_set_bb_reg(Adapter, pPhyReg->rfintfe | MaskforPhySet, bRFSI_RFENV << 16, 0x1); phy_set_bb_reg(Adapter, pPhyReg->rfintfe | MaskforPhySet, bRFSI_RFENV << 16, 0x1);
rtw_udelay_os(1);/* PlatformStallExecution(1); */ udelay(1);/* PlatformStallExecution(1); */
/*----Set RF_ENV output high----*/ /*----Set RF_ENV output high----*/
phy_set_bb_reg(Adapter, pPhyReg->rfintfo | MaskforPhySet, bRFSI_RFENV, 0x1); phy_set_bb_reg(Adapter, pPhyReg->rfintfo | MaskforPhySet, bRFSI_RFENV, 0x1);
rtw_udelay_os(1);/* PlatformStallExecution(1); */ udelay(1);/* PlatformStallExecution(1); */
/* Set bit number of Address and Data for RF register */ /* Set bit number of Address and Data for RF register */
phy_set_bb_reg(Adapter, pPhyReg->rfHSSIPara2 | MaskforPhySet, b3WireAddressLength, 0x0); /* Set 1 to 4 bits for 8255 */ phy_set_bb_reg(Adapter, pPhyReg->rfHSSIPara2 | MaskforPhySet, b3WireAddressLength, 0x0); /* Set 1 to 4 bits for 8255 */
rtw_udelay_os(1);/* PlatformStallExecution(1); */ udelay(1);/* PlatformStallExecution(1); */
phy_set_bb_reg(Adapter, pPhyReg->rfHSSIPara2 | MaskforPhySet, b3WireDataLength, 0x0); /* Set 0 to 12 bits for 8255 */ phy_set_bb_reg(Adapter, pPhyReg->rfHSSIPara2 | MaskforPhySet, b3WireDataLength, 0x0); /* Set 0 to 12 bits for 8255 */
rtw_udelay_os(1);/* PlatformStallExecution(1); */ udelay(1);/* PlatformStallExecution(1); */
/*----Initialize RF fom connfiguration file----*/ /*----Initialize RF fom connfiguration file----*/
switch (eRFPath) { switch (eRFPath) {

1
include/autoconf.h
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@ -286,7 +286,6 @@
/* #define DBG_CMD_QUEUE */ /* #define DBG_CMD_QUEUE */
/* #define DBG_IO */ /* #define DBG_IO */
/* #define DBG_DELAY_OS */
/* #define DBG_MEM_ALLOC */ /* #define DBG_MEM_ALLOC */
/* #define DBG_IOCTL */ /* #define DBG_IOCTL */

7
include/osdep_service.h
View File

@ -368,13 +368,6 @@ extern void rtw_usleep_os(int us);
extern u32 rtw_atoi(u8 *s); extern u32 rtw_atoi(u8 *s);
#ifdef DBG_DELAY_OS
#define rtw_udelay_os(ms) _rtw_udelay_os((ms), __FUNCTION__, __LINE__)
extern void _rtw_udelay_os(int us, const char *func, const int line);
#else
extern void rtw_udelay_os(int us);
#endif
extern void rtw_init_timer(_timer *ptimer, void *padapter, void *pfunc, void *ctx); extern void rtw_init_timer(_timer *ptimer, void *padapter, void *pfunc, void *ctx);

49
os_dep/osdep_service.c
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@ -1606,55 +1606,6 @@ void rtw_usleep_os(int us)
} }
#ifdef DBG_DELAY_OS
void _rtw_udelay_os(int us, const char *func, const int line)
{
#if 0
if (us > 1000) {
RTW_INFO("%s:%d %s(%d)\n", func, line, __FUNCTION__, us);
rtw_usleep_os(us);
return;
}
#endif
RTW_INFO("%s:%d %s(%d)\n", func, line, __FUNCTION__, us);
#if defined(PLATFORM_LINUX)
udelay((unsigned long)us);
#elif defined(PLATFORM_WINDOWS)
NdisStallExecution(us); /* (us) */
#endif
}
void rtw_udelay_os(int us)
{
#ifdef PLATFORM_LINUX
udelay((unsigned long)us);
#endif
#ifdef PLATFORM_FREEBSD
/* Delay for delay microseconds */
DELAY(us);
return ;
#endif
#ifdef PLATFORM_WINDOWS
NdisStallExecution(us); /* (us) */
#endif
}
#endif
bool rtw_macaddr_is_larger(const u8 *a, const u8 *b) bool rtw_macaddr_is_larger(const u8 *a, const u8 *b)
{ {