From a5adfa895bd492f798eb636c7f3f2ef7fdba8a9f Mon Sep 17 00:00:00 2001 From: Larry Finger Date: Thu, 5 Aug 2021 14:26:42 -0500 Subject: [PATCH] Remove wrapper rtw_udelay_os() This wrapper is a simple call to udelay(). Remove it. Link: https://lore.kernel.org/r/20210805192644.15978-4-Larry.Finger@lwfinger.net --- core/efuse/rtw_efuse.c | 2 +- core/rtw_eeprom.c | 12 ++++----- core/rtw_xmit.c | 2 +- hal/HalPwrSeqCmd.c | 6 ++--- hal/hal_com.c | 4 +-- hal/hal_com_phycfg.c | 28 +++++++++---------- hal/hal_halmac.c | 2 +- hal/hal_intf.c | 2 +- hal/phydm/phydm_interface.c | 4 +-- hal/rtl8192e/rtl8192e_phycfg.c | 4 +-- hal/rtl8192e/rtl8192e_rf6052.c | 8 +++--- include/autoconf.h | 1 - include/osdep_service.h | 7 ----- os_dep/osdep_service.c | 49 ---------------------------------- 14 files changed, 37 insertions(+), 94 deletions(-) diff --git a/core/efuse/rtw_efuse.c b/core/efuse/rtw_efuse.c index a703589..e99dd7c 100644 --- a/core/efuse/rtw_efuse.c +++ b/core/efuse/rtw_efuse.c @@ -1985,7 +1985,7 @@ ReadEFuseByte( /* This fix the problem that Efuse read error in high temperature condition. */ /* Designer says that there shall be some delay after ready bit is set, or the */ /* result will always stay on last data we read. */ - rtw_udelay_os(50); + udelay(50); value32 = rtw_read32(Adapter, EFUSE_CTRL); *pbuf = (u8)(value32 & 0xff); diff --git a/core/rtw_eeprom.c b/core/rtw_eeprom.c index d48996e..1537755 100644 --- a/core/rtw_eeprom.c +++ b/core/rtw_eeprom.c @@ -22,7 +22,7 @@ void up_clk(_adapter *padapter, u16 *x) { *x = *x | _EESK; rtw_write8(padapter, EE_9346CR, (u8)*x); - rtw_udelay_os(CLOCK_RATE); + udelay(CLOCK_RATE); } @@ -31,7 +31,7 @@ void down_clk(_adapter *padapter, u16 *x) { *x = *x & ~_EESK; rtw_write8(padapter, EE_9346CR, (u8)*x); - rtw_udelay_os(CLOCK_RATE); + udelay(CLOCK_RATE); } void shift_out_bits(_adapter *padapter, u16 data, u16 count) @@ -54,7 +54,7 @@ void shift_out_bits(_adapter *padapter, u16 data, u16 count) goto out; } rtw_write8(padapter, EE_9346CR, (u8)x); - rtw_udelay_os(CLOCK_RATE); + udelay(CLOCK_RATE); up_clk(padapter, &x); down_clk(padapter, &x); mask = mask >> 1; @@ -106,10 +106,10 @@ void standby(_adapter *padapter) x &= ~(_EECS | _EESK); rtw_write8(padapter, EE_9346CR, x); - rtw_udelay_os(CLOCK_RATE); + udelay(CLOCK_RATE); x |= _EECS; rtw_write8(padapter, EE_9346CR, x); - rtw_udelay_os(CLOCK_RATE); + udelay(CLOCK_RATE); } u16 wait_eeprom_cmd_done(_adapter *padapter) @@ -123,7 +123,7 @@ u16 wait_eeprom_cmd_done(_adapter *padapter) res = _TRUE; goto exit; } - rtw_udelay_os(CLOCK_RATE); + udelay(CLOCK_RATE); } exit: return res; diff --git a/core/rtw_xmit.c b/core/rtw_xmit.c index fb99327..9c9f569 100644 --- a/core/rtw_xmit.c +++ b/core/rtw_xmit.c @@ -4418,7 +4418,7 @@ s32 rtw_monitor_xmit_entry(struct sk_buff *skb, struct net_device *ndev) #endif pmgntframe = alloc_mgtxmitframe(pxmitpriv); if (pmgntframe == NULL) { - rtw_udelay_os(500); + udelay(500); goto fail; } diff --git a/hal/HalPwrSeqCmd.c b/hal/HalPwrSeqCmd.c index 389785c..fbac1fe 100644 --- a/hal/HalPwrSeqCmd.c +++ b/hal/HalPwrSeqCmd.c @@ -132,7 +132,7 @@ u8 HalPwrSeqCmdParsing( if (value == (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd))) bPollingBit = _TRUE; else - rtw_udelay_os(10); + udelay(10); if (pollingCount++ > maxPollingCnt) { RTW_ERR("HalPwrSeqCmdParsing: Fail to polling Offset[%#x]=%02x\n", offset, value); @@ -163,9 +163,9 @@ u8 HalPwrSeqCmdParsing( case PWR_CMD_DELAY: if (GET_PWR_CFG_VALUE(PwrCfgCmd) == PWRSEQ_DELAY_US) - rtw_udelay_os(GET_PWR_CFG_OFFSET(PwrCfgCmd)); + udelay(GET_PWR_CFG_OFFSET(PwrCfgCmd)); else - rtw_udelay_os(GET_PWR_CFG_OFFSET(PwrCfgCmd) * 1000); + udelay(GET_PWR_CFG_OFFSET(PwrCfgCmd) * 1000); break; case PWR_CMD_END: diff --git a/hal/hal_com.c b/hal/hal_com.c index cb6ddad..d0cb0b3 100644 --- a/hal/hal_com.c +++ b/hal/hal_com.c @@ -9016,7 +9016,7 @@ bool rtw_read_from_frame_mask(_adapter *adapter, u8 idx) do { tmp = rtw_read8(adapter, REG_RXPKTBUF_CTRL); - rtw_udelay_os(2); + udelay(2); count++; } while (!tmp && count < 100); @@ -9127,7 +9127,7 @@ bool rtw_write_to_frame_mask(_adapter *adapter, u8 idx, count = 0; do { tmp = rtw_read8(adapter, REG_RXPKTBUF_CTRL); - rtw_udelay_os(2); + udelay(2); count++; } while (tmp && count < 100); diff --git a/hal/hal_com_phycfg.c b/hal/hal_com_phycfg.c index 7e89e64..6424101 100644 --- a/hal/hal_com_phycfg.c +++ b/hal/hal_com_phycfg.c @@ -4216,11 +4216,11 @@ phy_ConfigBBWithParaFile( else if (u4bRegOffset == 0xfc) mdelay(1); else if (u4bRegOffset == 0xfb) - rtw_udelay_os(50); + udelay(50); else if (u4bRegOffset == 0xfa) - rtw_udelay_os(5); + udelay(5); else if (u4bRegOffset == 0xf9) - rtw_udelay_os(1); + udelay(1); /* Get 2nd hex value as register value. */ szLine += u4bMove; @@ -4232,7 +4232,7 @@ phy_ConfigBBWithParaFile( pHalData->odmpriv.rf_calibrate_info.rega24 = u4bRegValue; /* Add 1us delay between BB/RF register setting. */ - rtw_udelay_os(1); + udelay(1); } } } @@ -4564,11 +4564,11 @@ phy_ConfigBBWithMpParaFile( else if (u4bRegOffset == 0xfc) mdelay(1); else if (u4bRegOffset == 0xfb) - rtw_udelay_os(50); + udelay(50); else if (u4bRegOffset == 0xfa) - rtw_udelay_os(5); + udelay(5); else if (u4bRegOffset == 0xf9) - rtw_udelay_os(1); + udelay(1); /* Get 2nd hex value as register value. */ szLine += u4bMove; @@ -4577,7 +4577,7 @@ phy_ConfigBBWithMpParaFile( phy_set_bb_reg(Adapter, u4bRegOffset, bMaskDWord, u4bRegValue); /* Add 1us delay between BB/RF register setting. */ - rtw_udelay_os(1); + udelay(1); } } } @@ -4676,17 +4676,17 @@ PHY_ConfigRFWithParaFile( } else if (u4bRegOffset == 0xfd) { /* mdelay(5); */ for (i = 0; i < 100; i++) - rtw_udelay_os(MAX_STALL_TIME); + udelay(MAX_STALL_TIME); } else if (u4bRegOffset == 0xfc) { /* mdelay(1); */ for (i = 0; i < 20; i++) - rtw_udelay_os(MAX_STALL_TIME); + udelay(MAX_STALL_TIME); } else if (u4bRegOffset == 0xfb) - rtw_udelay_os(50); + udelay(50); else if (u4bRegOffset == 0xfa) - rtw_udelay_os(5); + udelay(5); else if (u4bRegOffset == 0xf9) - rtw_udelay_os(1); + udelay(1); else if (u4bRegOffset == 0xffff) break; @@ -4703,7 +4703,7 @@ PHY_ConfigRFWithParaFile( /* 0x2b 0x00808 frequency divider. */ /* 0x2b 0x53333 */ /* 0x2c 0x0000c */ - rtw_udelay_os(1); + udelay(1); } } } diff --git a/hal/hal_halmac.c b/hal/hal_halmac.c index 320219b..907e487 100644 --- a/hal/hal_halmac.c +++ b/hal/hal_halmac.c @@ -410,7 +410,7 @@ static void _halmac_udelay(void *p, u32 us) { /* Most hardware polling wait time < 50us) */ if (us <= 50) - rtw_udelay_os(us); + udelay(us); else if (us <= 1000) rtw_usleep_os(us); else diff --git a/hal/hal_intf.c b/hal/hal_intf.c index c3aab45..bdfeb4e 100644 --- a/hal/hal_intf.c +++ b/hal/hal_intf.c @@ -739,7 +739,7 @@ void rtw_hal_write_rfreg(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr, #ifdef CONFIG_PCI_HCI if (!IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(padapter)) /*For N-Series IC, suggest by Jenyu*/ - rtw_udelay_os(2); + udelay(2); #endif } } diff --git a/hal/phydm/phydm_interface.c b/hal/phydm/phydm_interface.c index bf5fb55..1136fd4 100644 --- a/hal/phydm/phydm_interface.c +++ b/hal/phydm/phydm_interface.c @@ -615,11 +615,11 @@ void ODM_delay_us(u32 us) #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) udelay(us); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - rtw_udelay_os(us); + udelay(us); #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) PlatformStallExecution(us); #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) - rtw_udelay_os(us); + udelay(us); #endif } diff --git a/hal/rtl8192e/rtl8192e_phycfg.c b/hal/rtl8192e/rtl8192e_phycfg.c index 8dc9d3c..55707df 100644 --- a/hal/rtl8192e/rtl8192e_phycfg.c +++ b/hal/rtl8192e/rtl8192e_phycfg.c @@ -140,11 +140,11 @@ phy_RFSerialRead( phy_set_bb_reg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEdge)); phy_set_bb_reg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 | bLSSIReadEdge); - rtw_udelay_os(10);/* PlatformStallExecution(10); */ + udelay(10);/* PlatformStallExecution(10); */ /* for(i=0;i<2;i++) */ /* PlatformStallExecution(MAX_STALL_TIME); */ - rtw_udelay_os(10);/* PlatformStallExecution(10); */ + udelay(10);/* PlatformStallExecution(10); */ if (eRFPath == RF_PATH_A) RfPiEnable = (u1Byte)phy_query_bb_reg(Adapter, rFPGA0_XA_HSSIParameter1 | MaskforPhySet, BIT8); diff --git a/hal/rtl8192e/rtl8192e_rf6052.c b/hal/rtl8192e/rtl8192e_rf6052.c index 4bc63e2..a0d74f2 100644 --- a/hal/rtl8192e/rtl8192e_rf6052.c +++ b/hal/rtl8192e/rtl8192e_rf6052.c @@ -94,18 +94,18 @@ phy_RF6052_Config_ParaFile_8192E( /*----Set RF_ENV enable----*/ phy_set_bb_reg(Adapter, pPhyReg->rfintfe | MaskforPhySet, bRFSI_RFENV << 16, 0x1); - rtw_udelay_os(1);/* PlatformStallExecution(1); */ + udelay(1);/* PlatformStallExecution(1); */ /*----Set RF_ENV output high----*/ phy_set_bb_reg(Adapter, pPhyReg->rfintfo | MaskforPhySet, bRFSI_RFENV, 0x1); - rtw_udelay_os(1);/* PlatformStallExecution(1); */ + udelay(1);/* PlatformStallExecution(1); */ /* Set bit number of Address and Data for RF register */ phy_set_bb_reg(Adapter, pPhyReg->rfHSSIPara2 | MaskforPhySet, b3WireAddressLength, 0x0); /* Set 1 to 4 bits for 8255 */ - rtw_udelay_os(1);/* PlatformStallExecution(1); */ + udelay(1);/* PlatformStallExecution(1); */ phy_set_bb_reg(Adapter, pPhyReg->rfHSSIPara2 | MaskforPhySet, b3WireDataLength, 0x0); /* Set 0 to 12 bits for 8255 */ - rtw_udelay_os(1);/* PlatformStallExecution(1); */ + udelay(1);/* PlatformStallExecution(1); */ /*----Initialize RF fom connfiguration file----*/ switch (eRFPath) { diff --git a/include/autoconf.h b/include/autoconf.h index b96b062..bd75643 100644 --- a/include/autoconf.h +++ b/include/autoconf.h @@ -286,7 +286,6 @@ /* #define DBG_CMD_QUEUE */ /* #define DBG_IO */ -/* #define DBG_DELAY_OS */ /* #define DBG_MEM_ALLOC */ /* #define DBG_IOCTL */ diff --git a/include/osdep_service.h b/include/osdep_service.h index 1f2572a..ab24553 100644 --- a/include/osdep_service.h +++ b/include/osdep_service.h @@ -368,13 +368,6 @@ extern void rtw_usleep_os(int us); extern u32 rtw_atoi(u8 *s); -#ifdef DBG_DELAY_OS -#define rtw_udelay_os(ms) _rtw_udelay_os((ms), __FUNCTION__, __LINE__) -extern void _rtw_udelay_os(int us, const char *func, const int line); -#else -extern void rtw_udelay_os(int us); -#endif - extern void rtw_init_timer(_timer *ptimer, void *padapter, void *pfunc, void *ctx); diff --git a/os_dep/osdep_service.c b/os_dep/osdep_service.c index 1aad193..13a62c8 100644 --- a/os_dep/osdep_service.c +++ b/os_dep/osdep_service.c @@ -1606,55 +1606,6 @@ void rtw_usleep_os(int us) } -#ifdef DBG_DELAY_OS -void _rtw_udelay_os(int us, const char *func, const int line) -{ - -#if 0 - if (us > 1000) { - RTW_INFO("%s:%d %s(%d)\n", func, line, __FUNCTION__, us); - rtw_usleep_os(us); - return; - } -#endif - - - RTW_INFO("%s:%d %s(%d)\n", func, line, __FUNCTION__, us); - - -#if defined(PLATFORM_LINUX) - - udelay((unsigned long)us); - -#elif defined(PLATFORM_WINDOWS) - - NdisStallExecution(us); /* (us) */ - -#endif - -} - -void rtw_udelay_os(int us) -{ - -#ifdef PLATFORM_LINUX - - udelay((unsigned long)us); - -#endif -#ifdef PLATFORM_FREEBSD - /* Delay for delay microseconds */ - DELAY(us); - return ; -#endif -#ifdef PLATFORM_WINDOWS - - NdisStallExecution(us); /* (us) */ - -#endif - -} -#endif bool rtw_macaddr_is_larger(const u8 *a, const u8 *b) {