Github/rtl8192eu-linux-driver
1
0
Fork 0
mirror of https://github.com/Mange/rtl8192eu-linux-driver synced 2026-03-31 22:49:56 +00:00
Code Issues Packages Projects Releases Wiki Activity

Remove wrapper rtw_udelay_os()

Browse Source 
This wrapper is a simple call to udelay(). Remove it.

Link: https://lore.kernel.org/r/20210805192644.15978-4-Larry.Finger@lwfinger.net
This commit is contained in:
Larry Finger
2021-08-05 14:26:42 -05:00
committed by Carlos Garcés
parent 7f8451a86e
commit a5adfa895b
14 changed files with 37 additions and 94 deletions
Download Patch File Download Diff File Expand all files Collapse all files

28
hal/hal_com_phycfg.c
View File

@@ -4216,11 +4216,11 @@ phy_ConfigBBWithParaFile(
else if (u4bRegOffset == 0xfc)
mdelay(1);
else if (u4bRegOffset == 0xfb)
rtw_udelay_os(50);
udelay(50);
else if (u4bRegOffset == 0xfa)
rtw_udelay_os(5);
udelay(5);
else if (u4bRegOffset == 0xf9)
rtw_udelay_os(1);
udelay(1);
/* Get 2nd hex value as register value. */
szLine += u4bMove;
@@ -4232,7 +4232,7 @@ phy_ConfigBBWithParaFile(
pHalData->odmpriv.rf_calibrate_info.rega24 = u4bRegValue;
/* Add 1us delay between BB/RF register setting. */
rtw_udelay_os(1);
udelay(1);
}
}
}
@@ -4564,11 +4564,11 @@ phy_ConfigBBWithMpParaFile(
else if (u4bRegOffset == 0xfc)
mdelay(1);
else if (u4bRegOffset == 0xfb)
rtw_udelay_os(50);
udelay(50);
else if (u4bRegOffset == 0xfa)
rtw_udelay_os(5);
udelay(5);
else if (u4bRegOffset == 0xf9)
rtw_udelay_os(1);
udelay(1);
/* Get 2nd hex value as register value. */
szLine += u4bMove;
@@ -4577,7 +4577,7 @@ phy_ConfigBBWithMpParaFile(
phy_set_bb_reg(Adapter, u4bRegOffset, bMaskDWord, u4bRegValue);
/* Add 1us delay between BB/RF register setting. */
rtw_udelay_os(1);
udelay(1);
}
}
}
@@ -4676,17 +4676,17 @@ PHY_ConfigRFWithParaFile(
} else if (u4bRegOffset == 0xfd) {
/* mdelay(5); */
for (i = 0; i < 100; i++)
rtw_udelay_os(MAX_STALL_TIME);
udelay(MAX_STALL_TIME);
} else if (u4bRegOffset == 0xfc) {
/* mdelay(1); */
for (i = 0; i < 20; i++)
rtw_udelay_os(MAX_STALL_TIME);
udelay(MAX_STALL_TIME);
} else if (u4bRegOffset == 0xfb)
rtw_udelay_os(50);
udelay(50);
else if (u4bRegOffset == 0xfa)
rtw_udelay_os(5);
udelay(5);
else if (u4bRegOffset == 0xf9)
rtw_udelay_os(1);
udelay(1);
else if (u4bRegOffset == 0xffff)
break;
@@ -4703,7 +4703,7 @@ PHY_ConfigRFWithParaFile(
/* 0x2b 0x00808 frequency divider. */
/* 0x2b 0x53333 */
/* 0x2c 0x0000c */
rtw_udelay_os(1);
udelay(1);
}
}
}