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Updated to v4.3.8_12406.20140929

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This commit is contained in:
CGarces
2017-05-11 20:35:20 +02:00
parent 1387cf623d
commit 9dde4572b4
229 changed files with 35553 additions and 24316 deletions
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59
include/hal_com_reg.h
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@@ -226,13 +226,22 @@
// 0x0400h ~ 0x047Fh Protocol Configuration
//
//-----------------------------------------------------
#define REG_VOQ_INFORMATION 0x0400
#define REG_VIQ_INFORMATION 0x0404
#define REG_BEQ_INFORMATION 0x0408
#define REG_BKQ_INFORMATION 0x040C
#define REG_MGQ_INFORMATION 0x0410
#define REG_HGQ_INFORMATION 0x0414
#define REG_BCNQ_INFORMATION 0x0418
/* 92C, 92D */
#define REG_VOQ_INFO 0x0400
#define REG_VIQ_INFO 0x0404
#define REG_BEQ_INFO 0x0408
#define REG_BKQ_INFO 0x040C
/* 88E, 8723A, 8812A, 8821A, 92E, 8723B */
#define REG_Q0_INFO 0x400
#define REG_Q1_INFO 0x404
#define REG_Q2_INFO 0x408
#define REG_Q3_INFO 0x40C
#define REG_MGQ_INFO 0x0410
#define REG_HGQ_INFO 0x0414
#define REG_BCNQ_INFO 0x0418
#define REG_TXPKT_EMPTY 0x041A
#define REG_CPU_MGQ_INFORMATION 0x041C
#define REG_FWHW_TXQ_CTRL 0x0420
@@ -258,22 +267,44 @@
#define REG_FAST_EDCA_CTRL 0x0460
#define REG_RD_RESP_PKT_TH 0x0463
/* 8723A, 8812A, 8821A, 92E, 8723B */
#define REG_Q4_INFO 0x468
#define REG_Q5_INFO 0x46C
#define REG_Q6_INFO 0x470
#define REG_Q7_INFO 0x474
#define REG_INIRTS_RATE_SEL 0x0480
#define REG_INIDATA_RATE_SEL 0x0484
/* 8723B, 92E, 8812A, 8821A*/
#define REG_MACID_SLEEP_3 0x0484
#define REG_MACID_SLEEP_1 0x0488
#define REG_POWER_STAGE1 0x04B4
#define REG_POWER_STAGE2 0x04B8
#define REG_PKT_VO_VI_LIFE_TIME 0x04C0
#define REG_PKT_BE_BK_LIFE_TIME 0x04C2
#define REG_STBC_SETTING 0x04C4
#define REG_QUEUE_CTRL 0x04C6
#define REG_SINGLE_AMPDU_CTRL 0x04c7
#define REG_PROT_MODE_CTRL 0x04C8
#define REG_MAX_AGGR_NUM 0x04CA
#define REG_RTS_MAX_AGGR_NUM 0x04CB
#define REG_BAR_MODE_CTRL 0x04CC
#define REG_RA_TRY_RATE_AGG_LMT 0x04CF
#define REG_EARLY_MODE_CONTROL 0x04D0
#define REG_MACID_SLEEP 0x04D4
/* 8723A */
#define REG_MACID_DROP 0x04D0
/* 88E */
#define REG_EARLY_MODE_CONTROL 0x04D0
/* 8723B, 92E, 8812A, 8821A */
#define REG_MACID_SLEEP_2 0x04D0
/* 8723A, 8723B, 92E, 8812A, 8821A */
#define REG_MACID_SLEEP 0x04D4
#define REG_NQOS_SEQ 0x04DC
#define REG_QOS_SEQ 0x04DE
#define REG_NEED_CPU_HANDLE 0x04E0
@@ -638,6 +669,9 @@ Default: 00b.
#define RRSR_MCS6 BIT18
#define RRSR_MCS7 BIT19
#define RRSR_CCK_RATES (RRSR_11M|RRSR_5_5M|RRSR_2M|RRSR_1M)
#define RRSR_OFDM_RATES (RRSR_54M|RRSR_48M|RRSR_36M|RRSR_24M|RRSR_18M|RRSR_12M|RRSR_9M|RRSR_6M)
// WOL bit information
#define HAL92C_WOL_PTK_UPDATE_EVENT BIT0
#define HAL92C_WOL_GTK_UPDATE_EVENT BIT1
@@ -762,10 +796,6 @@ Default: 00b.
#define CAM_READ 0x00000000
#define CAM_POLLINIG BIT31
#define SCR_UseDK 0x01
#define SCR_TxSecEnable 0x02
#define SCR_RxSecEnable 0x04
//
// 10. Power Save Control Registers
//
@@ -1514,6 +1544,7 @@ Current IOREG MAP
#define SCR_NoSKMC BIT(5) //No Key Search Multicast
#define SCR_TXBCUSEDK BIT(6) // Force Tx Broadcast packets Use Default Key
#define SCR_RXBCUSEDK BIT(7) // Force Rx Broadcast packets Use Default Key
#define SCR_CHK_KEYID BIT(8)
//-----------------------------------------------------
//
@@ -1716,7 +1747,7 @@ Current IOREG MAP
// General definitions
//========================================================
#define LAST_ENTRY_OF_TX_PKT_BUFFER_8188E 176
#define LAST_ENTRY_OF_TX_PKT_BUFFER_8188E(__Adapter) ( IS_VENDOR_8188E_I_CUT_SERIES(__Adapter) ? 255 : 175 )
#define LAST_ENTRY_OF_TX_PKT_BUFFER_8812 255
#define LAST_ENTRY_OF_TX_PKT_BUFFER_8723B 255
#define LAST_ENTRY_OF_TX_PKT_BUFFER_8192C 255