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Updated to v4.3.8_12406.20140929

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This commit is contained in:
CGarces
2017-05-11 20:35:20 +02:00
parent 1387cf623d
commit 9dde4572b4
229 changed files with 35553 additions and 24316 deletions
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554
hal/rtl8192e/rtl8192e_cmd.c
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File diff suppressed because it is too large Load Diff

191
hal/rtl8192e/rtl8192e_dm.c
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@@ -234,94 +234,21 @@ dm_InitGPIOSetting(
tmp1byte = rtw_read8(Adapter, REG_GPIO_MUXCFG);
tmp1byte &= (GPIOSEL_GPIO | ~GPIOSEL_ENBT);
#ifdef CONFIG_BT_COEXIST
// UMB-B cut bug. We need to support the modification.
if (IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID) &&
pHalData->bt_coexist.BT_Coexist)
{
tmp1byte |= (BIT5);
}
#endif
rtw_write8(Adapter, REG_GPIO_MUXCFG, tmp1byte);
}
// A mapping from HalData to ODM.
ODM_BOARD_TYPE_E boardType(u8 InterfaceSel)
{
ODM_BOARD_TYPE_E board = ODM_BOARD_DEFAULT;
#ifdef CONFIG_PCI_HCI
INTERFACE_SELECT_PCIE pcie = (INTERFACE_SELECT_PCIE)InterfaceSel;
switch (pcie)
{
case INTF_SEL0_SOLO_MINICARD:
board |= ODM_BOARD_MINICARD;
break;
case INTF_SEL1_BT_COMBO_MINICARD:
board |= ODM_BOARD_BT;
board |= ODM_BOARD_MINICARD;
break;
default:
board = ODM_BOARD_DEFAULT;
break;
}
#elif defined(CONFIG_USB_HCI)
INTERFACE_SELECT_USB usb = (INTERFACE_SELECT_USB)InterfaceSel;
switch (usb)
{
case INTF_SEL1_USB_High_Power:
board |= ODM_BOARD_EXT_LNA;
board |= ODM_BOARD_EXT_PA;
break;
case INTF_SEL2_MINICARD:
board |= ODM_BOARD_MINICARD;
break;
case INTF_SEL4_USB_Combo:
board |= ODM_BOARD_BT;
break;
case INTF_SEL5_USB_Combo_MF:
board |= ODM_BOARD_BT;
break;
case INTF_SEL0_USB:
case INTF_SEL3_USB_Solo:
default:
board = ODM_BOARD_DEFAULT;
break;
}
#endif
//DBG_871X("===> boardType(): (pHalData->InterfaceSel, pDM_Odm->BoardType) = (%d, %d)\n", InterfaceSel, board);
return board;
}
//============================================================
// functions
//============================================================
static void Init_ODM_ComInfo_8192e(PADAPTER Adapter)
{
EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(Adapter);
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
PDM_ODM_T pDM_Odm = &(pHalData->odmpriv);
u8 cut_ver,fab_ver;
u8 BoardType = ODM_BOARD_DEFAULT;
//
// Init Value
//
_rtw_memset(pDM_Odm,0,sizeof(*pDM_Odm));
pDM_Odm->Adapter = Adapter;
ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_PLATFORM,ODM_CE);
if (Adapter->interface_type == RTW_GSPI)
ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_INTERFACE,ODM_ITRF_SDIO);
else
ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_INTERFACE,Adapter->interface_type);
Init_ODM_ComInfo(Adapter);
ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_IC_TYPE,ODM_RTL8192E);
@@ -341,57 +268,6 @@ static void Init_ODM_ComInfo_8192e(PADAPTER Adapter)
cut_ver = ODM_CUT_A;
ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_CUT_VER,cut_ver);
ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_MP_TEST_CHIP,IS_NORMAL_CHIP(pHalData->VersionID));
//1 ======= BoardType: ODM_CMNINFO_BOARD_TYPE =======
#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI)
if(pHalData->InterfaceSel == INTF_SEL1_USB_High_Power)
{
ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_PA, 1);
ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, 1);
}
else
{
ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_PA, pHalData->ExternalPA_2G);
ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, 0);
}
#else
// PCIE no external PA now???
ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_PA, 0);
ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, 0);
#endif
if (pHalData->ExternalLNA_2G != 0) {
BoardType |= ODM_BOARD_EXT_LNA;
ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, 1);
}
if (pHalData->ExternalPA_2G != 0) {
BoardType |= ODM_BOARD_EXT_PA;
ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_PA, 1);
}
ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, BoardType);
//1 ============== End of BoardType ==============
ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_TRSW, 0);
ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_PATCH_ID,pEEPROM->CustomerID);
// ODM_CMNINFO_BINHCT_TEST only for MP Team
ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_BWIFI_TEST,Adapter->registrypriv.wifi_spec);
if(pHalData->rf_type == RF_1T1R){
ODM_CmnInfoUpdate(pDM_Odm,ODM_CMNINFO_RF_TYPE,ODM_1T1R);
}
else if(pHalData->rf_type == RF_2T2R){
ODM_CmnInfoUpdate(pDM_Odm,ODM_CMNINFO_RF_TYPE,ODM_2T2R);
}
else if(pHalData->rf_type == RF_1T2R){
ODM_CmnInfoUpdate(pDM_Odm,ODM_CMNINFO_RF_TYPE,ODM_1T2R);
}
ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_RF_ANTENNA_TYPE, pHalData->TRxAntDivType);
#ifdef CONFIG_DISABLE_ODM
@@ -409,13 +285,9 @@ static void Init_ODM_ComInfo_8192e(PADAPTER Adapter)
}
static void Update_ODM_ComInfo_8192e(PADAPTER Adapter)
{
struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(Adapter);
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
PDM_ODM_T pDM_Odm = &(pHalData->odmpriv);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
int i;
struct dm_priv *pdmpriv = &pHalData->dmpriv;
pdmpriv->InitODMFlag = 0
| ODM_BB_DIG
@@ -425,14 +297,18 @@ static void Update_ODM_ComInfo_8192e(PADAPTER Adapter)
| ODM_BB_RSSI_MONITOR
//| ODM_BB_CCK_PD
//| ODM_BB_PWR_SAVE
| ODM_BB_CFO_TRACKING
| ODM_MAC_EDCA_TURBO
| ODM_RF_CALIBRATION
| ODM_RF_TX_PWR_TRACK
#ifdef CONFIG_ODM_ADAPTIVITY
| ODM_BB_ADAPTIVITY
#endif
| ODM_BB_PRIMARY_CCA
| ODM_BB_NHM_CNT
// | ODM_BB_PWR_TRAIN
;
if (rtw_odm_adaptivity_needed(Adapter) == _TRUE)
pdmpriv->InitODMFlag |= ODM_BB_ADAPTIVITY;
if(pHalData->AntDivCfg)
pdmpriv->InitODMFlag |= ODM_BB_ANT_DIV;
@@ -450,42 +326,8 @@ static void Update_ODM_ComInfo_8192e(PADAPTER Adapter)
#endif//CONFIG_DISABLE_ODM
ODM_CmnInfoUpdate(pDM_Odm,ODM_CMNINFO_ABILITY,pdmpriv->InitODMFlag);
ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_TX_UNI,&(Adapter->xmitpriv.tx_bytes));
ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_RX_UNI,&(Adapter->recvpriv.rx_bytes));
ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_WM_MODE,&(pmlmeext->cur_wireless_mode));
ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_BAND,&(pHalData->CurrentBandType));
ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_FORCED_RATE,&(pHalData->ForcedDataRate));
ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_SEC_CHNL_OFFSET,&(pHalData->nCur40MhzPrimeSC));
ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_SEC_MODE,&(Adapter->securitypriv.dot11PrivacyAlgrthm));
ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_BW,&(pHalData->CurrentChannelBW ));
ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_CHNL,&( pHalData->CurrentChannel));
ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_NET_CLOSED,&( Adapter->net_closed));
ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_MP_MODE,&(Adapter->registrypriv.mp_mode));
ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_FORCED_IGI_LB,&(pHalData->u1ForcedIgiLb));
//================= only for 8192D =================
/*
ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_DMSP_GET_VALUE,&(pDM_Odm->u1Byte_temp));
ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_BUDDY_ADAPTOR,&(pDM_Odm->PADAPTER_temp));
ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_DMSP_IS_MASTER,&(pDM_Odm->u1Byte_temp));
//================= only for 8192D =================
// driver havn't those variable now
ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_BT_OPERATION,&(pDM_Odm->u1Byte_temp));
ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_BT_DISABLE_EDCA,&(pDM_Odm->u1Byte_temp));
*/
ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_SCAN,&(pmlmepriv->bScanInProcess));
ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_POWER_SAVING,&(pwrctrlpriv->bpower_saving));
ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_RF_ANTENNA_TYPE, pHalData->TRxAntDivType);
for(i=0; i< NUM_STA; i++)
{
//pDM_Odm->pODM_StaInfo[i] = NULL;
ODM_CmnInfoPtrArrayHook(pDM_Odm, ODM_CMNINFO_STA_STATUS,i,NULL);
}
}
void
@@ -504,6 +346,7 @@ rtl8192e_InitHalDm(
pdmpriv->DM_Type = DM_Type_ByDriver;
pdmpriv->DMFlag = DYNAMIC_FUNC_DISABLE;
Update_ODM_ComInfo_8192e(Adapter);
ODM_DMInit(pDM_Odm);
@@ -577,6 +420,7 @@ rtl8192e_HalDmWatchDog(
{
u8 bLinked=_FALSE;
u8 bsta_state=_FALSE;
u8 bBtDisabled = _TRUE;
#ifdef CONFIG_DISABLE_ODM
pHalData->odmpriv.SupportAbility = 0;
#endif
@@ -598,6 +442,14 @@ rtl8192e_HalDmWatchDog(
ODM_CmnInfoUpdate(&pHalData->odmpriv ,ODM_CMNINFO_LINK, bLinked);
ODM_CmnInfoUpdate(&pHalData->odmpriv ,ODM_CMNINFO_STATION_STATE, bsta_state);
#ifdef CONFIG_BT_COEXIST
bBtDisabled = rtw_btcoex_IsBtDisabled(Adapter);
ODM_CmnInfoUpdate(&pHalData->odmpriv, ODM_CMNINFO_BT_ENABLED, ((bBtDisabled == _TRUE)?_FALSE:_TRUE));
#else
ODM_CmnInfoUpdate(&pHalData->odmpriv, ODM_CMNINFO_BT_ENABLED,_FALSE);
#endif // CONFIG_BT_COEXIST
ODM_DMWatchdog(&pHalData->odmpriv);
}
@@ -619,11 +471,9 @@ void rtl8192e_init_dm_priv(IN PADAPTER Adapter)
_rtw_memset(pdmpriv, 0, sizeof(struct dm_priv));
//_rtw_spinlock_init(&(pHalData->odm_stainfo_lock));
Init_ODM_ComInfo_8192e(Adapter);
//_init_timer(&(pdmpriv->SwAntennaSwitchTimer), Adapter->pnetdev , odm_SW_AntennaSwitchCallback, Adapter);
ODM_InitAllTimers(podmpriv );
ODM_InitDebugSetting(podmpriv);
pHalData->RegRFPathS1 = 0;
}
void rtl8192e_deinit_dm_priv(IN PADAPTER Adapter)
@@ -631,8 +481,7 @@ void rtl8192e_deinit_dm_priv(IN PADAPTER Adapter)
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
PDM_ODM_T podmpriv = &pHalData->odmpriv;
//_rtw_spinlock_free(&pHalData->odm_stainfo_lock);
//_cancel_timer_ex(&pdmpriv->SwAntennaSwitchTimer);
//_rtw_spinlock_free(&pHalData->odm_stainfo_lock);
ODM_CancelAllTimers(podmpriv);
}

625
hal/rtl8192e/rtl8192e_hal_init.c
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File diff suppressed because it is too large Load Diff

13
hal/rtl8192e/rtl8192e_mp.c
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@@ -392,12 +392,12 @@ void Hal_SetCCKTxPower(PADAPTER pAdapter, u8 *TxPower)
// rf-A cck tx power
write_bbreg(pAdapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, TxPower[RF_PATH_A]);
tmpval = (TxPower[RF_PATH_A]<<16) | (TxPower[RF_PATH_A]<<8) | TxPower[RF_PATH_A];
write_bbreg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval);
write_bbreg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskH3Bytes, tmpval);
// rf-B cck tx power
write_bbreg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, TxPower[RF_PATH_B]);
tmpval = (TxPower[RF_PATH_B]<<16) | (TxPower[RF_PATH_B]<<8) | TxPower[RF_PATH_B];
write_bbreg(pAdapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, tmpval);
write_bbreg(pAdapter, rTxAGC_B_CCK1_55_Mcs32, bMaskH3Bytes, tmpval);
RT_TRACE(_module_mp_, _drv_notice_,
("-SetCCKTxPower: A[0x%02x] B[0x%02x]\n",
@@ -750,7 +750,6 @@ void Hal_TriggerRFThermalMeter(PADAPTER pAdapter)
{
PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_T_METER_8192E, BIT17 | BIT16, 0x03);
// RT_TRACE(_module_mp_,_drv_alert_, ("TriggerRFThermalMeter() finished.\n" ));
}
@@ -759,10 +758,9 @@ u8 Hal_ReadRFThermalMeter(PADAPTER pAdapter)
u32 ThermalValue = 0;
//ThermalValue = _read_rfreg(pAdapter, RF_PATH_A, RF_T_METER, 0x1F); // 0x24: RF Reg[4:0]
ThermalValue = (u1Byte)PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_T_METER_8192E, 0xfc00); // 0x42: RF Reg[15:10]
DBG_871X("%s ThermalValue = 0x%x\n", __FUNCTION__,ThermalValue);
printk("%s ### REG_C80:0x%08x,REG_C88:0x%08x ####\n",__FUNCTION__,
rtw_read32(pAdapter,0xc80),rtw_read32(pAdapter,0xc88));
ThermalValue = (u1Byte)PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_T_METER_8192E, 0xfc00); // 0x42: RF Reg[15:10]
DBG_871X("%s ThermalValue = 0x%x\n", __FUNCTION__,ThermalValue);
// RT_TRACE(_module_mp_, _drv_alert_, ("ThermalValue = 0x%x\n", ThermalValue));
return (u8)ThermalValue;
}
@@ -875,6 +873,7 @@ void Hal_SetSingleToneTx(PADAPTER pAdapter, u8 bStart)
}
void Hal_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart)
{
pAdapter->mppriv.MptCtx.bCarrierSuppression = bStart;

56
hal/rtl8192e/rtl8192e_phycfg.c
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@@ -196,7 +196,8 @@ phy_RFSerialWrite(
//}
// <20121026, Kordan> If 0x818 == 1, the second value written on the previous address.
PHY_SetBBReg(Adapter, ODM_AFE_SETTING, 0x20000, 0x0);
if (IS_HARDWARE_TYPE_8192EU(Adapter))
PHY_SetBBReg(Adapter, ODM_AFE_SETTING, 0x20000, 0x0);
Offset &= 0xff;
@@ -1176,7 +1177,28 @@ phy_SpurCalibration_8192E(
PHY_SetRFReg(Adapter, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, reg0x18); //restore chnl
}
#ifdef CONFIG_SPUR_CAL_NBI
// to eliminate the 2480MHz spur for 92E suggest by James
void
phy_SpurCalibration_8192E_NBI(PADAPTER Adapter)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
//DbgPrint("===> %s CurrentChannelBW = %d, CurrentChannel = %d\n", __FUNCTION__,pHalData->CurrentChannelBW, pHalData->CurrentChannel);
if(pHalData->CurrentChannelBW == CHANNEL_WIDTH_20 &&( pHalData->CurrentChannel == 13 || pHalData->CurrentChannel == 14)){
PHY_SetBBReg(Adapter, rOFDM0_RxDSP, BIT(9), 0x1); //enable notch filter
PHY_SetBBReg(Adapter, rOFDM1_IntfDet, BIT(8)|BIT(7)|BIT(6), 0x5); //intf_TH
}
else if(pHalData->CurrentChannelBW == CHANNEL_WIDTH_40 && pHalData->CurrentChannel == 11){
PHY_SetBBReg(Adapter, rOFDM0_RxDSP, BIT(9), 0x1); //enable notch filter
PHY_SetBBReg(Adapter, rOFDM1_IntfDet, BIT(8)|BIT(7)|BIT(6), 0x5); //intf_TH
}
else{
if(Adapter->registrypriv.notch_filter == 0)
PHY_SetBBReg(Adapter, rOFDM0_RxDSP, BIT(9), 0x0); //disable notch filter
}
}
#endif
VOID
phy_SwChnl8192E(
IN PADAPTER pAdapter
@@ -1190,22 +1212,9 @@ phy_SwChnl8192E(
//RT_TRACE(COMP_MLME,DBG_LOUD,("phy_SwChnl8192E: return for PSEUDO \n"));
return;
}
pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff00) | channelToSW );
PHY_SetRFReg(pAdapter, RF_PATH_A, RF_CHNLBW, 0x3FF, pHalData->RfRegChnlVal[0] );
PHY_SetRFReg(pAdapter, RF_PATH_B, RF_CHNLBW, 0x3FF, pHalData->RfRegChnlVal[0] );
#if 0 //to do
// <20130422, VincentLan> A workaround to eliminate the 2480MHz spur for 92E
if (channelToSW == 13)
{
if (pMgntInfo->RegSpurCalMethod == 1)//if AFE == 40MHz,MAC REG_0X78
phy_SpurCalibration_8192E(pAdapter, AFE_PHASE_SEL);
else
phy_SpurCalibration_8192E(pAdapter, PLL_RESET);
}
#endif
//pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff00) | channelToSW );
PHY_SetRFReg(pAdapter, RF_PATH_A, RF_CHNLBW, 0x3FF,channelToSW );
PHY_SetRFReg(pAdapter, RF_PATH_B, RF_CHNLBW, 0x3FF, channelToSW );
}
@@ -1225,6 +1234,7 @@ phy_SwChnlAndSetBwMode8192E(
pHalData->CurrentChannel,
pHalData->bSetChnlBW,
pHalData->CurrentChannelBW);
}
if((Adapter->bDriverStopped) || (Adapter->bSurpriseRemoved))
@@ -1242,10 +1252,14 @@ phy_SwChnlAndSetBwMode8192E(
{
phy_PostSetBwMode8192E(Adapter);
pHalData->bSetChnlBW = _FALSE;
}
}
#ifdef CONFIG_SPUR_CAL_NBI
phy_SpurCalibration_8192E_NBI(Adapter);
#endif
PHY_SetTxPowerLevel8192E(Adapter, pHalData->CurrentChannel);
}
VOID
@@ -1275,7 +1289,7 @@ PHY_HandleSwChnlAndSetBW8192E(
//check is swchnl or setbw
if(!bSwitchChannel && !bSetBandWidth)
{
DBG_871X("PHY_HandleSwChnlAndSetBW8812: not switch channel and not set bandwidth \n");
DBG_871X("PHY_HandleSwChnlAndSetBW8192e: not switch channel and not set bandwidth \n");
return;
}

21
hal/rtl8192e/rtl8192e_rxdesc.c
View File

@@ -22,20 +22,6 @@
//#include <drv_types.h>
#include <rtl8192e_hal.h>
static s32 translate2dbm(u8 signal_strength_idx)
{
s32 signal_power; // in dBm.
// Translate to dBm (x=0.5y-95).
signal_power = (s32)((signal_strength_idx + 1) >> 1);
signal_power -= 95;
return signal_power;
}
static void process_rssi(_adapter *padapter,union recv_frame *prframe)
{
u32 last_rssi, tmp_val;
@@ -78,10 +64,10 @@ static void process_rssi(_adapter *padapter,union recv_frame *prframe)
if(padapter->recvpriv.is_signal_dbg) {
padapter->recvpriv.signal_strength= padapter->recvpriv.signal_strength_dbg;
padapter->recvpriv.rssi=(s8)translate2dbm((u8)padapter->recvpriv.signal_strength_dbg);
padapter->recvpriv.rssi=(s8)translate_percentage_to_dbm(padapter->recvpriv.signal_strength_dbg);
} else {
padapter->recvpriv.signal_strength= tmp_val;
padapter->recvpriv.rssi=(s8)translate2dbm((u8)tmp_val);
padapter->recvpriv.rssi=(s8)translate_percentage_to_dbm(tmp_val);
}
RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("UI RSSI = %d, ui_rssi.TotalVal = %d, ui_rssi.TotalNum = %d\n", tmp_val, padapter->recvpriv.signal_strength_data.total_val,padapter->recvpriv.signal_strength_data.total_num));
@@ -251,6 +237,8 @@ void rtl8192e_query_rx_phy_status(
!pattrib->icv_err && !pattrib->crc_err &&
_rtw_memcmp(get_hdr_bssid(wlanhdr), get_bssid(&padapter->mlmepriv), ETH_ALEN));
pkt_info.bToSelf = ((!pattrib->icv_err) && (!pattrib->crc_err)) && (_rtw_memcmp(get_ra(wlanhdr), myid(&padapter->eeprompriv), ETH_ALEN));
pkt_info.bPacketToSelf = pkt_info.bPacketMatchBSSID && (_rtw_memcmp(get_ra(wlanhdr), myid(&padapter->eeprompriv), ETH_ALEN));
pkt_info.bPacketBeacon = pkt_info.bPacketMatchBSSID && (GetFrameSubType(wlanhdr) == WIFI_BEACON);
@@ -291,6 +279,7 @@ void rtl8192e_query_rx_phy_status(
//_enter_critical_bh(&pHalData->odm_stainfo_lock, &irqL);
ODM_PhyStatusQuery(&pHalData->odmpriv,pPHYInfo,pphy_status,&(pkt_info));
if(psta) psta->rssi = pattrib->phy_info.RecvSignalPower;
//_exit_critical_bh(&pHalData->odm_stainfo_lock, &irqL);
precvframe->u.hdr.psta = NULL;

29
hal/rtl8192e/usb/rtl8192eu_recv.c
View File

@@ -77,9 +77,7 @@ int rtl8192eu_init_recv_priv(_adapter *padapter)
//init recv_buf
_rtw_init_queue(&precvpriv->free_recv_buf_queue);
#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX
_rtw_init_queue(&precvpriv->recv_buf_pending_queue);
#endif // CONFIG_USE_USB_BUFFER_ALLOC_RX
precvpriv->pallocated_recv_buf = rtw_zmalloc(NR_RECVBUFF *sizeof(struct recv_buf) + 4);
if(precvpriv->pallocated_recv_buf==NULL){
@@ -132,15 +130,23 @@ int rtl8192eu_init_recv_priv(_adapter *padapter)
for(i=0; i<NR_PREALLOC_RECV_SKB; i++)
{
#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER
pskb = rtw_alloc_skb_premem();
#else
pskb = rtw_skb_alloc(MAX_RECVBUF_SZ + RECVBUFF_ALIGN_SZ);
#endif //CONFIG_PREALLOC_RX_SKB_BUFFER
if(pskb)
{
pskb->dev = padapter->pnetdev;
#ifndef CONFIG_PREALLOC_RX_SKB_BUFFER
tmpaddr = (SIZE_PTR)pskb->data;
alignment = tmpaddr & (RECVBUFF_ALIGN_SZ-1);
skb_reserve(pskb, (RECVBUFF_ALIGN_SZ - alignment));
#endif //!
skb_queue_tail(&precvpriv->free_recv_skb_queue, pskb);
}
@@ -202,7 +208,24 @@ void rtl8192eu_free_recv_priv (_adapter *padapter)
DBG_8192C(KERN_WARNING "free_recv_skb_queue not empty, %d\n", skb_queue_len(&precvpriv->free_recv_skb_queue));
}
#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER
{
int i=0;
struct sk_buff *skb;
while ((skb = skb_dequeue(&precvpriv->free_recv_skb_queue)) != NULL)
{
if(i<NR_PREALLOC_RECV_SKB)
rtw_free_skb_premem(skb);
else
_rtw_skb_free(skb);
i++;
}
}
#else
rtw_skb_queue_purge(&precvpriv->free_recv_skb_queue);
#endif //CONFIG_PREALLOC_RX_SKB_BUFFER
#endif

5
hal/rtl8192e/usb/rtl8192eu_xmit.c
View File

@@ -279,7 +279,7 @@ static s32 update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem, s32 sz ,u8 bag
SET_TX_DESC_AGG_ENABLE_92E(ptxdesc, 1);
SET_TX_DESC_MAX_AGG_NUM_92E(ptxdesc, 0x1f);
// Set A-MPDU aggregation.
SET_TX_DESC_AMPDU_DENSITY_92E(ptxdesc, pHalData->AMPDUDensity);
SET_TX_DESC_AMPDU_DENSITY_92E(ptxdesc, pattrib->ampdu_spacing);
} else {
SET_TX_DESC_BK_92E(ptxdesc, 1);
}
@@ -745,6 +745,9 @@ s32 rtl8192eu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv
pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list);
xmitframe_plist = get_next(xmitframe_plist);
if(_FAIL == rtw_hal_busagg_qsel_check(padapter,pfirstframe->attrib.qsel,pxmitframe->attrib.qsel))
break;
pxmitframe->agg_num = 0; // not first frame of aggregation
#ifdef CONFIG_TX_EARLY_MODE
pxmitframe->pkt_offset = 1;// not first frame of aggregation,reserve offset for EM Info

201
hal/rtl8192e/usb/usb_halinit.c
View File

@@ -269,6 +269,7 @@ static u32 _InitPowerOn_8192EU(_adapter *padapter)
{
u16 value16;
u32 value32;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
// HW Power on sequence
u8 bMacPwrCtrlOn=_FALSE;
@@ -282,6 +283,10 @@ static u32 _InitPowerOn_8192EU(_adapter *padapter)
if(value32 & BIT_SPSLDO_SEL){
//LDO
rtw_write8(padapter, REG_LDO_SWR_CTRL, 0xC3);
if( IS_B_CUT(pHalData->VersionID)){
u32 voltage = (rtw_read32(padapter,0x14)& 0xFF0FFFFF )|(0x05<<20);
rtw_write32(padapter,0x14,voltage);
}
}
else {
//SPS
@@ -314,7 +319,7 @@ static u32 _InitPowerOn_8192EU(_adapter *padapter)
bMacPwrCtrlOn = _TRUE;
rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
return _SUCCESS;
}
@@ -945,6 +950,8 @@ HalDetectSelectiveSuspendMode(
}
#endif
} // HalDetectSelectiveSuspendMode
#if 0
/*-----------------------------------------------------------------------------
* Function: HwSuspendModeEnable92Cu()
*
@@ -1002,6 +1009,8 @@ HwSuspendModeEnable_8192EU(
}
} // HwSuspendModeEnable92Cu
#endif
rt_rf_power_state RfOnOffDetect(IN PADAPTER pAdapter )
{
struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(pAdapter);
@@ -1063,9 +1072,7 @@ u32 rtl8192eu_hal_init(PADAPTER Adapter)
struct registry_priv *pregistrypriv = &Adapter->registrypriv;
rt_rf_power_state eRfPowerStateToSet;
#ifdef CONFIG_BT_COEXIST
struct btcoexist_priv *pbtpriv = &(pHalData->bt_coexist);
#endif
u32 init_start_time = rtw_get_current_time();
@@ -1418,11 +1425,12 @@ HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC11);
//
rtw_write32(Adapter, REG_BAR_MODE_CTRL, 0x0201ffff);
if(pregistrypriv->wifi_spec)
if(pregistrypriv->wifi_spec){
rtw_write16(Adapter,REG_FAST_EDCA_CTRL ,0);
//Nav limit , suggest by scott
rtw_write8(Adapter, 0x652, 0x0);
//Nav limit , suggest by SD1-Pisa,disable NAV_UPPER function when wifi_spec=1 for Test item: 5.2.3
rtw_write8(Adapter, REG_NAV_UPPER, 0x0);
}
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_HAL_DM);
rtl8192e_InitHalDm(Adapter);
@@ -1447,95 +1455,6 @@ HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_HAL_DM);
// Added by tynli. 2010.03.30.
pwrctrlpriv->rf_pwrstate = rf_on;
#if 0 //to do
RT_CLEAR_PS_LEVEL(pwrctrlpriv, RT_RF_OFF_LEVL_HALT_NIC);
#if 1 //Todo
// 20100326 Joseph: Copy from GPIOChangeRFWorkItemCallBack() function to check HW radio on/off.
// 20100329 Joseph: Revise and integrate the HW/SW radio off code in initialization.
eRfPowerStateToSet = (rt_rf_power_state) RfOnOffDetect(Adapter);
pwrctrlpriv->rfoff_reason |= eRfPowerStateToSet==rf_on ? RF_CHANGE_BY_INIT : RF_CHANGE_BY_HW;
pwrctrlpriv->rfoff_reason |= (pwrctrlpriv->reg_rfoff) ? RF_CHANGE_BY_SW : 0;
if(pwrctrlpriv->rfoff_reason&RF_CHANGE_BY_HW)
pwrctrlpriv->b_hw_radio_off = _TRUE;
DBG_8192C("eRfPowerStateToSet=%d\n", eRfPowerStateToSet);
if(pwrctrlpriv->reg_rfoff == _TRUE)
{ // User disable RF via registry.
DBG_8192C("InitializeAdapter8192CU(): Turn off RF for RegRfOff.\n");
//MgntActSet_RF_State(Adapter, rf_off, RF_CHANGE_BY_SW, _TRUE);
// Those action will be discard in MgntActSet_RF_State because off the same state
//for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
//PHY_SetRFReg(Adapter, eRFPath, 0x4, 0xC00, 0x0);
}
else if(pwrctrlpriv->rfoff_reason > RF_CHANGE_BY_PS)
{ // H/W or S/W RF OFF before sleep.
DBG_8192C(" Turn off RF for RfOffReason(%x) ----------\n", pwrctrlpriv->rfoff_reason);
//pwrctrlpriv->rfoff_reason = RF_CHANGE_BY_INIT;
pwrctrlpriv->rf_pwrstate = rf_on;
//MgntActSet_RF_State(Adapter, rf_off, pwrctrlpriv->rfoff_reason, _TRUE);
}
else
{
// Perform GPIO polling to find out current RF state. added by Roger, 2010.04.09.
if(pHalData->BoardType == BOARD_MINICARD /*&& (Adapter->MgntInfo.PowerSaveControl.bGpioRfSw)*/)
{
DBG_8192C("InitializeAdapter8192CU(): RF=%d \n", eRfPowerStateToSet);
if (eRfPowerStateToSet == rf_off)
{
//MgntActSet_RF_State(Adapter, rf_off, RF_CHANGE_BY_HW, _TRUE);
pwrctrlpriv->b_hw_radio_off = _TRUE;
}
else
{
pwrctrlpriv->rf_pwrstate = rf_off;
pwrctrlpriv->rfoff_reason = RF_CHANGE_BY_INIT;
pwrctrlpriv->b_hw_radio_off = _FALSE;
//MgntActSet_RF_State(Adapter, rf_on, pwrctrlpriv->rfoff_reason, _TRUE);
}
}
else
{
pwrctrlpriv->rf_pwrstate = rf_off;
pwrctrlpriv->rfoff_reason = RF_CHANGE_BY_INIT;
//MgntActSet_RF_State(Adapter, rf_on, pwrctrlpriv->rfoff_reason, _TRUE);
}
pwrctrlpriv->rfoff_reason = 0;
pwrctrlpriv->b_hw_radio_off = _FALSE;
pwrctrlpriv->rf_pwrstate = rf_on;
rtw_led_control(Adapter, LED_CTL_POWER_ON);
}
// 2010/-8/09 MH For power down module, we need to enable register block contrl reg at 0x1c.
// Then enable power down control bit of register 0x04 BIT4 and BIT15 as 1.
if(pHalData->pwrdown && eRfPowerStateToSet == rf_off)
{
// Enable register area 0x0-0xc.
rtw_write8(Adapter, REG_RSV_CTRL, 0x0);
//
// <Roger_Notes> We should configure HW PDn source for WiFi ONLY, and then
// our HW will be set in power-down mode if PDn source from all functions are configured.
// 2010.10.06.
//
//if(IS_HARDWARE_TYPE_8723AU(Adapter))
//{
// u1bTmp = rtw_read8(Adapter, REG_MULTI_FUNC_CTRL);
// rtw_write8(Adapter, REG_MULTI_FUNC_CTRL, (u1bTmp|WL_HWPDN_EN));
//}
//else
//{
rtw_write16(Adapter, REG_APS_FSMCO, 0x8812);
//}
}
//DrvIFIndicateCurrentPhyStatus(Adapter); // 2010/08/17 MH Disable to prevent BSOD.
#endif
#endif
//0x4c6[3] 1: RTS BW = Data BW
//0: RTS BW depends on CCA / secondary CCA result.
@@ -1576,7 +1495,7 @@ HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_PW_TRACK);
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_LCK);
//PHY_LCCalibrate_8192E((GET_HAL_DATA(Adapter)->odmpriv));
}
}
#ifdef CONFIG_HIGH_CHAN_SUPER_CALIBRATION
rtw_hal_set_chnl_bw(Adapter, 13,
CHANNEL_WIDTH_20, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HAL_PRIME_CHNL_OFFSET_DONT_CARE);
@@ -1592,7 +1511,7 @@ HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_LCK);
rtw_hal_set_chnl_bw(Adapter, Adapter->registrypriv.channel,
CHANNEL_WIDTH_20, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HAL_PRIME_CHNL_OFFSET_DONT_CARE);
#endif
}
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC21);
@@ -1601,8 +1520,21 @@ HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC21);
// _InitPABias(Adapter);
#ifdef CONFIG_BT_COEXIST
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BT_COEXIST);
//_InitBTCoexist(Adapter);
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BT_COEXIST);
if ( pHalData->EEPROMBluetoothCoexist == 1)
{
// YiWei 20140624 , Fix 8192eu mailbox BT info no response issue reduce I2C clock rate to 156KHz (default 1.25Mhz)
rtw_write8(Adapter, rPMAC_TxPacketNum, rtw_read8(Adapter, rPMAC_TxPacketNum)|0x7);
// Init BT hw config.
rtw_btcoex_HAL_Initialize(Adapter, _FALSE);
}
else
{
// In combo card run wifi only , must setting some hardware reg.
rtl8192e_combo_card_WifiOnlyHwInit(Adapter);
}
#endif
// 2010/08/23 MH According to Alfred's suggestion, we need to to prevent HW enter
@@ -1733,21 +1665,9 @@ u32 rtl8192eu_hal_deinit(PADAPTER Adapter)
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
DBG_8192C("==> %s \n",__FUNCTION__);
#ifdef CONFIG_BT_COEXIST
if (BT_IsBtExist(Adapter))
{
DBG_871X("BT module enable SIC\n");
// Only under WIN7 we can support selective suspend and enter D3 state when system call halt adapter.
//rtw_write16(Adapter, REG_GPIO_MUXCFG, rtw_read16(Adapter, REG_GPIO_MUXCFG)|BIT12);
// 2010/10/13 MH If we enable SIC in the position and then call _ResetDigitalProcedure1. in XP,
// the system will hang due to 8051 reset fail.
}
else
#endif
{
rtw_write16(Adapter, REG_GPIO_MUXCFG, rtw_read16(Adapter, REG_GPIO_MUXCFG)&(~BIT12));
}
rtw_write16(Adapter, REG_GPIO_MUXCFG, rtw_read16(Adapter, REG_GPIO_MUXCFG)&(~BIT12));
if(pHalData->bSupportUSB3 == _TRUE)
{
@@ -2269,16 +2189,36 @@ _func_enter_;
case HW_VAR_RXDMA_AGG_PG_TH:
#ifdef CONFIG_USB_RX_AGGREGATION
{
//threshold == 1 , Disable Rx-agg when AP is B/G mode or wifi_spec=1 to prevent bad TP.
u8 threshold = *((u8 *)val);
if( threshold == 0)
{
if( threshold == 0){
threshold = (pHalData->RegAcUsbDmaSize & 0x0F);
}
rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH, threshold);
//threshold == 1 ,disable RX AGG
if( (pHalData->UsbRxAggMode == USB_RX_AGG_USB) && (threshold == 1))
rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH+1, 0);
#ifdef CONFIG_80211N_HT
{
// 2014-07-24 Fix WIFI Logo -5.2.4/5.2.9 - DT3 low TP issue
// Adjust RxAggrTimeout to close to zero disable RxAggr for RxAgg-USB mode, suggested by designer
// Timeout value is calculated by 34 / (2^n)
struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
struct ht_priv *phtpriv = &pmlmepriv->htpriv;
if(pHalData->UsbRxAggMode == USB_RX_AGG_USB){
#if 1
//BG mode || (wifi_spec=1 && BG mode Testbed)
if((threshold == 1) && (_FALSE == phtpriv->ht_option) )
#else
//(wifi_spec=1 && BG mode Testbed)
if((Adapter->registrypriv.wifi_spec==1) && (_FALSE == phtpriv->ht_option) )
#endif
rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH+1, 0);
}
}
#endif//#ifdef CONFIG_80211N_HT
}
#endif
break;
@@ -2358,6 +2298,7 @@ _func_enter_;
pwrctl->wowlan_wake_reason = rtw_read8(Adapter, REG_WOWLAN_WAKE_REASON);
DBG_871X_LEVEL(_drv_always_, "wowlan_wake_reason: 0x%02x\n",
pwrctl->wowlan_wake_reason);
if (Adapter->intf_stop)
Adapter->intf_stop(Adapter);
@@ -2443,8 +2384,6 @@ _func_enter_;
do {
if ((rtw_read32(Adapter, REG_RXPKT_NUM)&RXDMA_IDLE)) {
DBG_871X_LEVEL(_drv_always_, "RX_DMA_IDLE is true\n");
if (Adapter->intf_stop)
Adapter->intf_stop(Adapter);
break;
} else {
// If RX_DMA is not idle, receive one pkt from DMA
@@ -2465,6 +2404,9 @@ _func_enter_;
rtw_write8(Adapter, REG_WOWLAN_WAKE_REASON, 0);
if (Adapter->intf_stop)
Adapter->intf_stop(Adapter);
// Invoid SE0 reset signal during suspending
rtw_write8(Adapter, REG_RSV_CTRL, 0x20);
rtw_write8(Adapter, REG_RSV_CTRL, 0x60);
@@ -2643,19 +2585,6 @@ void rtl8192eu_set_hal_ops(_adapter * padapter)
_func_enter_;
#ifdef CONFIG_CONCURRENT_MODE
if(padapter->isprimary)
#endif //CONFIG_CONCURRENT_MODE
{
padapter->HalData = rtw_zvmalloc(sizeof(HAL_DATA_TYPE));
if(padapter->HalData == NULL){
DBG_8192C("cant not alloc memory for HAL DATA \n");
}
}
//_rtw_memset(padapter->HalData, 0, sizeof(HAL_DATA_TYPE));
padapter->hal_data_sz = sizeof(HAL_DATA_TYPE);
pHalFunc->hal_power_on = _InitPowerOn_8192EU;
pHalFunc->hal_power_off = hal_poweroff_8192eu;

26
hal/rtl8192e/usb/usb_ops_linux.c
View File

@@ -899,12 +899,17 @@ void rtl8192eu_recv_tasklet(void *priv)
_pkt *pskb;
_adapter *padapter = (_adapter*)priv;
struct recv_priv *precvpriv = &padapter->recvpriv;
struct recv_buf *precvbuf = NULL;
while (NULL != (pskb = skb_dequeue(&precvpriv->rx_skb_queue)))
{
if ((padapter->bDriverStopped == _TRUE)||(padapter->bSurpriseRemoved== _TRUE))
{
DBG_8192C("recv_tasklet => bDriverStopped or bSurpriseRemoved \n");
#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER
if(rtw_free_skb_premem(pskb)!=0)
#endif //CONFIG_PREALLOC_RX_SKB_BUFFER
rtw_skb_free(pskb);
break;
}
@@ -922,9 +927,12 @@ void rtl8192eu_recv_tasklet(void *priv)
#else
rtw_skb_free(pskb);
#endif
if (NULL != (precvbuf = rtw_dequeue_recvbuf(&precvpriv->recv_buf_pending_queue))) {
precvbuf->pskb = NULL;
precvbuf->reuse = _FALSE;
rtw_read_port(padapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf);
}
}
}
@@ -984,8 +992,9 @@ static void usb_read_port_complete(struct urb *purb, struct pt_regs *regs)
precvbuf->transfer_len = purb->actual_length;
skb_put(precvbuf->pskb, purb->actual_length);
skb_queue_tail(&precvpriv->rx_skb_queue, precvbuf->pskb);
#ifndef CONFIG_FIX_NR_BULKIN_BUFFER
if (skb_queue_len(&precvpriv->rx_skb_queue)<=1)
#endif
tasklet_schedule(&precvpriv->recv_tasklet);
precvbuf->pskb = NULL;
@@ -1083,14 +1092,17 @@ _func_enter_;
//re-assign for linux based on skb
if((precvbuf->reuse == _FALSE) || (precvbuf->pskb == NULL))
{
#ifndef CONFIG_FIX_NR_BULKIN_BUFFER
precvbuf->pskb = rtw_skb_alloc(MAX_RECVBUF_SZ + RECVBUFF_ALIGN_SZ);
#endif
if(precvbuf->pskb == NULL)
{
RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("init_recvbuf(): alloc_skb fail!\n"));
DBG_8192C("#### usb_read_port() alloc_skb fail!#####\n");
if (0)
DBG_8192C("usb_read_port() enqueue precvbuf=%p \n", precvbuf);
//enqueue precvbuf and wait for free skb
rtw_enqueue_recvbuf(precvbuf, &precvpriv->recv_buf_pending_queue);
return _FAIL;
}
}
tmpaddr = (SIZE_PTR)precvbuf->pskb->data;
alignment = tmpaddr & (RECVBUFF_ALIGN_SZ-1);