Github/rtl8192eu-linux-driver
1
0
Fork 0
mirror of https://github.com/Mange/rtl8192eu-linux-driver synced 2024-12-23 12:37:42 +00:00
Code Issues Packages Projects Releases Wiki Activity

Remove duplicate names for rtw_read[n] and rtw_write[n]

Browse Source 
rtw_read[n]() is redefined as _rtw_read[n]() and PlatformEFIORead[n]Byte
Same for rtw_write[n]() furntions

Link: https://lore.kernel.org/r/9880c86c2aad7d95a714d8b03b28b83634f98c1e.1621361919.git-series.hello@bryanbrattlof.com
Link: https://lore.kernel.org/r/11458342572f21d9df58b3969ad1f16fdff157f4.1621361919.git-series.hello@bryanbrattlof.com
Link: https://lore.kernel.org/r/15956707341f76de683245c392063b8121a805ea.1621361919.git-series.hello@bryanbrattlof.com
Link: https://lore.kernel.org/r/35ffc9cd5af7009b317361033a6ca5263307d61a.1621361919.git-series.hello@bryanbrattlof.com
Link: https://lore.kernel.org/r/7d53fb295f67f01c72640045afb88150391bce35.1621361919.git-series.hello@bryanbrattlof.com
Link: https://lore.kernel.org/r/43917aee34e85139e613578cf6f14938211c8835.1621361919.git-series.hello@bryanbrattlof.com

Port of
51d4aa6d6bf35d85d318831df60a34bad27cdb9e
8ff74e4307b42302c89023faf8fd37dbde4c4666
16b1b3c8221a40bf899dfeebdb3d5245ecb65515
7f06caf9a40bb3c08fe86c8355ace25b7ce69ba9
1c42d72e4747fb546eba53821ae56ecf827202a7
4d6bfc6f62705ec5baee9c572d4ca03bc9e36c00
This commit is contained in:
Carlos Garces 2021-10-23 11:09:24 +02:00
parent 99c0f78547
commit 97bac22d5b
10 changed files with 79 additions and 219 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
core/efuse/rtw_efuse.c
View File

@ -805,13 +805,13 @@ VOID efuse_PreUpdateAction(
#ifdef CONFIG_RTL8812A
BackupRegs[3] = phy_query_mac_reg(pAdapter, REG_AFE_MISC, bMaskDWord);
#endif
PlatformEFIOWrite4Byte(pAdapter, REG_RCR, 0x1);
PlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0, 0);
PlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0+1, 0);
PlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0+2, 0);
PlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0+3, 0);
PlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0+4, 0);
PlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0+5, 0);
rtw_write32(pAdapter, REG_RCR, 0x1);
rtw_write8(pAdapter, REG_RXFLTMAP0, 0);
rtw_write8(pAdapter, REG_RXFLTMAP0+1, 0);
rtw_write8(pAdapter, REG_RXFLTMAP0+2, 0);
rtw_write8(pAdapter, REG_RXFLTMAP0+3, 0);
rtw_write8(pAdapter, REG_RXFLTMAP0+4, 0);
rtw_write8(pAdapter, REG_RXFLTMAP0+5, 0);
#ifdef CONFIG_RTL8812A
/* <20140410, Kordan> 0x11 = 0x4E, lower down LX_SPS0 voltage. (Asked by Chunchu)*/
phy_set_mac_reg(pAdapter, REG_AFE_MISC, bMaskByte1, 0x4E);

98
core/rtw_io.c
View File

@ -60,7 +60,7 @@ jackson@realtek.com.tw
#endif
u8 _rtw_read8(_adapter *adapter, u32 addr)
u8 rtw_read8(_adapter *adapter, u32 addr)
{
u8 r_val;
/* struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; */
@ -73,7 +73,7 @@ u8 _rtw_read8(_adapter *adapter, u32 addr)
return r_val;
}
u16 _rtw_read16(_adapter *adapter, u32 addr)
u16 rtw_read16(_adapter *adapter, u32 addr)
{
u16 r_val;
/* struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; */
@ -86,7 +86,7 @@ u16 _rtw_read16(_adapter *adapter, u32 addr)
return rtw_le16_to_cpu(r_val);
}
u32 _rtw_read32(_adapter *adapter, u32 addr)
u32 rtw_read32(_adapter *adapter, u32 addr)
{
u32 r_val;
/* struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; */
@ -100,7 +100,7 @@ u32 _rtw_read32(_adapter *adapter, u32 addr)
}
int _rtw_write8(_adapter *adapter, u32 addr, u8 val)
int rtw_write8(_adapter *adapter, u32 addr, u8 val)
{
/* struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; */
struct io_priv *pio_priv = &adapter->iopriv;
@ -113,7 +113,7 @@ int _rtw_write8(_adapter *adapter, u32 addr, u8 val)
return RTW_STATUS_CODE(ret);
}
int _rtw_write16(_adapter *adapter, u32 addr, u16 val)
int rtw_write16(_adapter *adapter, u32 addr, u16 val)
{
/* struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; */
struct io_priv *pio_priv = &adapter->iopriv;
@ -127,7 +127,7 @@ int _rtw_write16(_adapter *adapter, u32 addr, u16 val)
return RTW_STATUS_CODE(ret);
}
int _rtw_write32(_adapter *adapter, u32 addr, u32 val)
int rtw_write32(_adapter *adapter, u32 addr, u32 val)
{
/* struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; */
struct io_priv *pio_priv = &adapter->iopriv;
@ -142,7 +142,7 @@ int _rtw_write32(_adapter *adapter, u32 addr, u32 val)
return RTW_STATUS_CODE(ret);
}
int _rtw_writeN(_adapter *adapter, u32 addr , u32 length , u8 *pdata)
int rtw_writeN(_adapter *adapter, u32 addr , u32 length , u8 *pdata)
{
/* struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; */
struct io_priv *pio_priv = &adapter->iopriv;
@ -717,90 +717,6 @@ bool match_rf_write_sniff_ranges(_adapter *adapter, u8 path, u32 addr, u32 mask)
return _FALSE;
}
u8 dbg_rtw_read8(_adapter *adapter, u32 addr, const char *caller, const int line)
{
u8 val = _rtw_read8(adapter, addr);
const struct rtw_io_sniff_ent *ent = match_read_sniff(adapter, addr, 1, val);
if (ent) {
RTW_INFO("DBG_IO %s:%d rtw_read8(0x%04x) return 0x%02x %s\n"
, caller, line, addr, val, rtw_io_sniff_ent_get_tag(ent));
}
return val;
}
u16 dbg_rtw_read16(_adapter *adapter, u32 addr, const char *caller, const int line)
{
u16 val = _rtw_read16(adapter, addr);
const struct rtw_io_sniff_ent *ent = match_read_sniff(adapter, addr, 2, val);
if (ent) {
RTW_INFO("DBG_IO %s:%d rtw_read16(0x%04x) return 0x%04x %s\n"
, caller, line, addr, val, rtw_io_sniff_ent_get_tag(ent));
}
return val;
}
u32 dbg_rtw_read32(_adapter *adapter, u32 addr, const char *caller, const int line)
{
u32 val = _rtw_read32(adapter, addr);
const struct rtw_io_sniff_ent *ent = match_read_sniff(adapter, addr, 4, val);
if (ent) {
RTW_INFO("DBG_IO %s:%d rtw_read32(0x%04x) return 0x%08x %s\n"
, caller, line, addr, val, rtw_io_sniff_ent_get_tag(ent));
}
return val;
}
int dbg_rtw_write8(_adapter *adapter, u32 addr, u8 val, const char *caller, const int line)
{
const struct rtw_io_sniff_ent *ent = match_write_sniff(adapter, addr, 1, val);
if (ent) {
RTW_INFO("DBG_IO %s:%d rtw_write8(0x%04x, 0x%02x) %s\n"
, caller, line, addr, val, rtw_io_sniff_ent_get_tag(ent));
}
return _rtw_write8(adapter, addr, val);
}
int dbg_rtw_write16(_adapter *adapter, u32 addr, u16 val, const char *caller, const int line)
{
const struct rtw_io_sniff_ent *ent = match_write_sniff(adapter, addr, 2, val);
if (ent) {
RTW_INFO("DBG_IO %s:%d rtw_write16(0x%04x, 0x%04x) %s\n"
, caller, line, addr, val, rtw_io_sniff_ent_get_tag(ent));
}
return _rtw_write16(adapter, addr, val);
}
int dbg_rtw_write32(_adapter *adapter, u32 addr, u32 val, const char *caller, const int line)
{
const struct rtw_io_sniff_ent *ent = match_write_sniff(adapter, addr, 4, val);
if (ent) {
RTW_INFO("DBG_IO %s:%d rtw_write32(0x%04x, 0x%08x) %s\n"
, caller, line, addr, val, rtw_io_sniff_ent_get_tag(ent));
}
return _rtw_write32(adapter, addr, val);
}
int dbg_rtw_writeN(_adapter *adapter, u32 addr , u32 length , u8 *data, const char *caller, const int line)
{
const struct rtw_io_sniff_ent *ent = match_write_sniff(adapter, addr, length, 0);
if (ent) {
RTW_INFO("DBG_IO %s:%d rtw_writeN(0x%04x, %u) %s\n"
, caller, line, addr, length, rtw_io_sniff_ent_get_tag(ent));
}
return _rtw_writeN(adapter, addr, length, data);
}
#ifdef CONFIG_SDIO_HCI
u8 dbg_rtw_sd_f0_read8(_adapter *adapter, u32 addr, const char *caller, const int line)
{

6
core/rtw_mp.c
View File

@ -331,7 +331,7 @@ void mpt_InitHWConfig(PADAPTER Adapter)
phy_set_mac_reg(Adapter, 0x4C , BIT23, 0); /*select DPDT_P and DPDT_N as output pin*/
#ifdef CONFIG_RTL8814A
else if (IS_HARDWARE_TYPE_8814A(Adapter))
PlatformEFIOWrite2Byte(Adapter, REG_RXFLTMAP1_8814A, 0x2000);
rtw_write16(Adapter, REG_RXFLTMAP1_8814A, 0x2000);
#endif
#ifdef CONFIG_RTL8812A
@ -346,7 +346,7 @@ void mpt_InitHWConfig(PADAPTER Adapter)
else if (IS_HARDWARE_TYPE_8822B(Adapter)) {
u32 tmp_reg = 0;
PlatformEFIOWrite2Byte(Adapter, REG_RXFLTMAP1_8822B, 0x2000);
rtw_write16(Adapter, REG_RXFLTMAP1_8822B, 0x2000);
/* fixed wifi can't 2.4g tx suggest by Szuyitasi 20160504 */
phy_set_bb_reg(Adapter, 0x70, bMaskByte3, 0x0e);
RTW_INFO(" 0x73 = 0x%x\n", phy_query_bb_reg(Adapter, 0x70, bMaskByte3));
@ -358,7 +358,7 @@ void mpt_InitHWConfig(PADAPTER Adapter)
#endif /* CONFIG_RTL8822B */
#ifdef CONFIG_RTL8821C
else if (IS_HARDWARE_TYPE_8821C(Adapter))
PlatformEFIOWrite2Byte(Adapter, REG_RXFLTMAP1_8821C, 0x2000);
rtw_write16(Adapter, REG_RXFLTMAP1_8821C, 0x2000);
#endif /* CONFIG_RTL8821C */
#if defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV)
else if (IS_HARDWARE_TYPE_8188F(Adapter) || IS_HARDWARE_TYPE_8188GTV(Adapter)) {

8
hal/HalPwrSeqCmd.c
View File

@ -142,13 +142,13 @@ u8 HalPwrSeqCmdParsing(
RTW_ERR("[WARNING] PCIE polling(0x%X) timeout(%d), Toggle 0x04[3] and try again.\n", offset, maxPollingCnt);
if (IS_HARDWARE_TYPE_8723DE(padapter))
PlatformEFIOWrite1Byte(padapter, 0x40, (PlatformEFIORead1Byte(padapter, 0x40)) & (~BIT3));
rtw_write8(padapter, 0x40, (rtw_read8(padapter, 0x40)) & (~BIT3));
PlatformEFIOWrite1Byte(padapter, 0x04, PlatformEFIORead1Byte(padapter, 0x04) | BIT3);
PlatformEFIOWrite1Byte(padapter, 0x04, PlatformEFIORead1Byte(padapter, 0x04) & ~BIT3);
rtw_write8(padapter, 0x04, rtw_read8(padapter, 0x04) | BIT3);
rtw_write8(padapter, 0x04, rtw_read8(padapter, 0x04) & ~BIT3);
if (IS_HARDWARE_TYPE_8723DE(padapter))
PlatformEFIOWrite1Byte(padapter, 0x40, PlatformEFIORead1Byte(padapter, 0x40)|BIT3);
rtw_write8(padapter, 0x40, rtw_read8(padapter, 0x40)|BIT3);
/* Retry Polling Process one more time */
pollingCount = 0;

2
hal/hal_mp.c
View File

@ -90,7 +90,7 @@ void hal_mpt_SwitchRfSetting(PADAPTER pAdapter)
pMptCtx->backup0x52_RF_A = (u1Byte)phy_query_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0);
pMptCtx->backup0x52_RF_B = (u1Byte)phy_query_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0);
if ((PlatformEFIORead4Byte(pAdapter, 0xF4) & BIT29) == BIT29) {
if ((rtw_read32(pAdapter, 0xF4) & BIT29) == BIT29) {
phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0xB);
phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0xB);
} else {

12
hal/phydm/phydm_interface.c
View File

@ -52,7 +52,7 @@ u8 odm_read_1byte(struct dm_struct *dm, u32 reg_addr)
return rtw_read8(adapter, reg_addr);
#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
void *adapter = dm->adapter;
return PlatformEFIORead1Byte(adapter, reg_addr);
return rtw_read8(adapter, reg_addr);
#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
void *adapter = dm->adapter;
@ -78,7 +78,7 @@ u16 odm_read_2byte(struct dm_struct *dm, u32 reg_addr)
return rtw_read16(adapter, reg_addr);
#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
void *adapter = dm->adapter;
return PlatformEFIORead2Byte(adapter, reg_addr);
return rtw_read16(adapter, reg_addr);
#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
void *adapter = dm->adapter;
@ -104,7 +104,7 @@ u32 odm_read_4byte(struct dm_struct *dm, u32 reg_addr)
return rtw_read32(adapter, reg_addr);
#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
void *adapter = dm->adapter;
return PlatformEFIORead4Byte(adapter, reg_addr);
return rtw_read32(adapter, reg_addr);
#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
void *adapter = dm->adapter;
@ -130,7 +130,7 @@ void odm_write_1byte(struct dm_struct *dm, u32 reg_addr, u8 data)
rtw_write8(adapter, reg_addr, data);
#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
void *adapter = dm->adapter;
PlatformEFIOWrite1Byte(adapter, reg_addr, data);
rtw_write8(adapter, reg_addr, data);
#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
void *adapter = dm->adapter;
@ -156,7 +156,7 @@ void odm_write_2byte(struct dm_struct *dm, u32 reg_addr, u16 data)
rtw_write16(adapter, reg_addr, data);
#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
void *adapter = dm->adapter;
PlatformEFIOWrite2Byte(adapter, reg_addr, data);
rtw_write16(adapter, reg_addr, data);
#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
void *adapter = dm->adapter;
@ -182,7 +182,7 @@ void odm_write_4byte(struct dm_struct *dm, u32 reg_addr, u32 data)
rtw_write32(adapter, reg_addr, data);
#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
void *adapter = dm->adapter;
PlatformEFIOWrite4Byte(adapter, reg_addr, data);
rtw_write32(adapter, reg_addr, data);
#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
void *adapter = dm->adapter;

12
hal/rtl8192e/rtl8192e_hal_init.c
View File

@ -3741,16 +3741,16 @@ u8 SetHwReg8192E(PADAPTER Adapter, u8 variable, u8 *val)
val[1] = 0x0e;
}
/* SIFS for OFDM Data ACK */
PlatformEFIOWrite1Byte(Adapter, REG_SIFS_CTX_8192E+1, val[0]);
rtw_write8(Adapter, REG_SIFS_CTX_8192E+1, val[0]);
/* SIFS for OFDM consecutive tx like CTS data! */
PlatformEFIOWrite1Byte(Adapter, REG_SIFS_TRX_8192E+1, val[1]);
rtw_write8(Adapter, REG_SIFS_TRX_8192E+1, val[1]);
PlatformEFIOWrite1Byte(Adapter, REG_SPEC_SIFS_8192E+1, val[0]);
PlatformEFIOWrite1Byte(Adapter, REG_MAC_SPEC_SIFS_8192E+1, val[0]);
rtw_write8(Adapter, REG_SPEC_SIFS_8192E+1, val[0]);
rtw_write8(Adapter, REG_MAC_SPEC_SIFS_8192E+1, val[0]);
/* Revise SIFS setting due to Hardware register definition change. */
PlatformEFIOWrite1Byte(Adapter, REG_RESP_SIFS_OFDM_8192E+1, val[0]);
PlatformEFIOWrite1Byte(Adapter, REG_RESP_SIFS_OFDM_8192E, val[0]);
rtw_write8(Adapter, REG_RESP_SIFS_OFDM_8192E+1, val[0]);
rtw_write8(Adapter, REG_RESP_SIFS_OFDM_8192E, val[0]);
}
#if 0

68
hal/rtl8192e/usb/usb_halinit.c
View File

@ -170,64 +170,64 @@ _InitBurstPktLen_8192EU(IN PADAPTER Adapter)
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
/* PlatformEFIOWrite2Byte(Adapter, REG_TRXDMA_CTRL_8195, 0xf5b0); */
/* PlatformEFIOWrite2Byte(Adapter, REG_TRXDMA_CTRL_8812, 0xf5b4); */
PlatformEFIOWrite2Byte(Adapter, REG_RXDMA_STATUS_8192E, 0x7400); /* burset lenght=4, set 0x3400 for burset length=2 */
PlatformEFIOWrite1Byte(Adapter, 0x289, 0xf5); /* for rxdma control */
/* PlatformEFIOWrite1Byte(Adapter, 0x3a, 0x46); */
/* rtw_write16(Adapter, REG_TRXDMA_CTRL_8195, 0xf5b0); */
/* rtw_write16(Adapter, REG_TRXDMA_CTRL_8812, 0xf5b4); */
rtw_write16(Adapter, REG_RXDMA_STATUS_8192E, 0x7400); /* burset lenght=4, set 0x3400 for burset length=2 */
rtw_write8(Adapter, 0x289, 0xf5); /* for rxdma control */
/* rtw_write8(Adapter, 0x3a, 0x46); */
/* 0x456 = 0x70, sugguested by Zhilin */
/* PlatformEFIOWrite1Byte(Adapter, REG_AMPDU_MAX_TIME_8192E, 0x70); */
/* rtw_write8(Adapter, REG_AMPDU_MAX_TIME_8192E, 0x70); */
/* Suggention by SD1 Jong and Pisa, by Maddest 20130107. */
PlatformEFIOWrite2Byte(Adapter, REG_MAX_AGGR_NUM_8192E, 0x0e0e);
PlatformEFIOWrite1Byte(Adapter, REG_FWHW_TXQ_CTRL_8192E, 0x80);/* EN_AMPDU_RTY_NEW */
PlatformEFIOWrite1Byte(Adapter, REG_AMPDU_MAX_TIME_8192E, 0x5e);
PlatformEFIOWrite4Byte(Adapter, REG_FAST_EDCA_CTRL_8192E, 0x03087777);
rtw_write16(Adapter, REG_MAX_AGGR_NUM_8192E, 0x0e0e);
rtw_write8(Adapter, REG_FWHW_TXQ_CTRL_8192E, 0x80);/* EN_AMPDU_RTY_NEW */
rtw_write8(Adapter, REG_AMPDU_MAX_TIME_8192E, 0x5e);
rtw_write32(Adapter, REG_FAST_EDCA_CTRL_8192E, 0x03087777);
/* PlatformEFIOWrite4Byte(Adapter, 0x458, 0xffffffff); */
PlatformEFIOWrite1Byte(Adapter, REG_USTIME_TSF_8192E, 0x50);
PlatformEFIOWrite1Byte(Adapter, REG_USTIME_EDCA_8192E, 0x50);
/* rtw_write32(Adapter, 0x458, 0xffffffff); */
rtw_write8(Adapter, REG_USTIME_TSF_8192E, 0x50);
rtw_write8(Adapter, REG_USTIME_EDCA_8192E, 0x50);
if (IS_HARDWARE_TYPE_8821U(Adapter) || IS_HARDWARE_TYPE_8192EU(Adapter))
speedvalue = BIT7;
else
speedvalue = PlatformEFIORead1Byte(Adapter, 0xff); /* check device operation speed: SS 0xff bit7 */
speedvalue = rtw_read8(Adapter, 0xff); /* check device operation speed: SS 0xff bit7 */
if (speedvalue & BIT7) { /* USB2/1.1 Mode */
temp = PlatformEFIORead1Byte(Adapter, REG_USB_INFO);
temp = rtw_read8(Adapter, REG_USB_INFO);
if (((temp >> 4) & 0x03) == 0) {
/* pHalData->UsbBulkOutSize = 512; */
provalue = PlatformEFIORead1Byte(Adapter, REG_RXDMA_PRO_8192E);
PlatformEFIOWrite1Byte(Adapter, REG_RXDMA_PRO_8192E, (provalue | BIT(4) & (~BIT(5)))); /* set burst pkt len=512B */
PlatformEFIOWrite2Byte(Adapter, REG_RXDMA_PRO_8192E, 0x1e);
provalue = rtw_read8(Adapter, REG_RXDMA_PRO_8192E);
rtw_write8(Adapter, REG_RXDMA_PRO_8192E, (provalue | BIT(4) & (~BIT(5)))); /* set burst pkt len=512B */
rtw_write16(Adapter, REG_RXDMA_PRO_8192E, 0x1e);
} else {
/* pHalData->UsbBulkOutSize = 64; */
provalue = PlatformEFIORead1Byte(Adapter, REG_RXDMA_PRO_8192E);
PlatformEFIOWrite1Byte(Adapter, REG_RXDMA_PRO_8192E, ((provalue | BIT(5)) & (~BIT(4)))); /* set burst pkt len=64B */
provalue = rtw_read8(Adapter, REG_RXDMA_PRO_8192E);
rtw_write8(Adapter, REG_RXDMA_PRO_8192E, ((provalue | BIT(5)) & (~BIT(4)))); /* set burst pkt len=64B */
}
PlatformEFIOWrite2Byte(Adapter, REG_RXDMA_AGG_PG_TH_8192E, 0x2005); /* dmc agg th 20K */
rtw_write16(Adapter, REG_RXDMA_AGG_PG_TH_8192E, 0x2005); /* dmc agg th 20K */
pHalData->bSupportUSB3 = FALSE;
}
PlatformEFIOWrite1Byte(Adapter, REG_DWBCN0_CTRL_8192E, 0x10);
rtw_write8(Adapter, REG_DWBCN0_CTRL_8192E, 0x10);
PlatformEFIOWrite1Byte(Adapter, 0x4c7, PlatformEFIORead1Byte(Adapter, 0x4c7) | BIT(7)); /* enable single pkt ampdu */
PlatformEFIOWrite1Byte(Adapter, REG_RX_PKT_LIMIT_8192E, 0x18); /* for VHT packet length 11K */
rtw_write8(Adapter, 0x4c7, rtw_read8(Adapter, 0x4c7) | BIT(7)); /* enable single pkt ampdu */
rtw_write8(Adapter, REG_RX_PKT_LIMIT_8192E, 0x18); /* for VHT packet length 11K */
/* PlatformEFIOWrite1Byte(Adapter, REG_MAX_AGGR_NUM_8192E, 0x1f); */
PlatformEFIOWrite1Byte(Adapter, REG_PIFS_8192E, 0x00);
/* PlatformEFIOWrite1Byte(Adapter, REG_FWHW_TXQ_CTRL_8192E, PlatformEFIORead1Byte(Adapter, REG_FWHW_TXQ_CTRL)&(~BIT(7))); */
/* rtw_write8(Adapter, REG_MAX_AGGR_NUM_8192E, 0x1f); */
rtw_write8(Adapter, REG_PIFS_8192E, 0x00);
/* rtw_write8(Adapter, REG_FWHW_TXQ_CTRL_8192E, rtw_read8(Adapter, REG_FWHW_TXQ_CTRL)&(~BIT(7))); */
#ifdef CONFIG_TX_EARLY_MODE
if (pHalData->AMPDUBurstMode)
PlatformEFIOWrite1Byte(Adapter, REG_SW_AMPDU_BURST_MODE_CTRL_8192E, 0x5F);
rtw_write8(Adapter, REG_SW_AMPDU_BURST_MODE_CTRL_8192E, 0x5F);
#endif
PlatformEFIOWrite1Byte(Adapter, 0x1c, PlatformEFIORead1Byte(Adapter, 0x1c) | BIT(5) | BIT(6)); /* to prevent mac is reseted by bus. 20111208, by Page */
rtw_write8(Adapter, 0x1c, rtw_read8(Adapter, 0x1c) | BIT(5) | BIT(6)); /* to prevent mac is reseted by bus. 20111208, by Page */
#endif
}
@ -255,8 +255,8 @@ static u32 _InitPowerOn_8192EU(_adapter *padapter)
/* 0x14[23:20]=b<><62>0101 (raise 1.2V voltage)
u1Byte tmp1Byte = PlatformEFIORead1Byte(Adapter,0x16);
PlatformEFIOWrite1Byte(Adapter,0x16,tmp1Byte |BIT4|BIT6); */
u1Byte tmp1Byte = rtw_read8(Adapter,0x16);
rtw_write8(Adapter,0x16,tmp1Byte |BIT4|BIT6); */
u32 voltage = rtw_read32(padapter , REG_SYS_SWR_CTRL2_8192E);
if (((voltage & 0x00F00000) >> 20) == 0x4) {
@ -1106,10 +1106,10 @@ u32 rtl8192eu_hal_init(PADAPTER Adapter)
#endif /* CONFIG_XMIT_ACK */
/* Fixed LDPC rx hang issue. */
{
u4Byte tmp4Byte = PlatformEFIORead4Byte(Adapter, REG_SYS_SWR_CTRL1_8192E);
PlatformEFIOWrite1Byte(Adapter, REG_SYS_SWR_CTRL2_8192E, 0x75);
u4Byte tmp4Byte = rtw_read32(Adapter, REG_SYS_SWR_CTRL1_8192E);
rtw_write8(Adapter, REG_SYS_SWR_CTRL2_8192E, 0x75);
tmp4Byte = (tmp4Byte & 0xfff00fff) | (0x7E << 12);
PlatformEFIOWrite4Byte(Adapter, REG_SYS_SWR_CTRL1_8192E, tmp4Byte);
rtw_write32(Adapter, REG_SYS_SWR_CTRL1_8192E, tmp4Byte);
}
exit:

70
include/rtw_io.h
View File

@ -335,18 +335,18 @@ extern void unregister_intf_hdl(struct intf_hdl *pintfhdl);
extern void _rtw_attrib_read(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
extern void _rtw_attrib_write(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
extern u8 _rtw_read8(_adapter *adapter, u32 addr);
extern u16 _rtw_read16(_adapter *adapter, u32 addr);
extern u32 _rtw_read32(_adapter *adapter, u32 addr);
extern u8 rtw_read8(_adapter *adapter, u32 addr);
extern u16 rtw_read16(_adapter *adapter, u32 addr);
extern u32 rtw_read32(_adapter *adapter, u32 addr);
extern void _rtw_read_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
extern void _rtw_read_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
extern void _rtw_read_port_cancel(_adapter *adapter);
extern int _rtw_write8(_adapter *adapter, u32 addr, u8 val);
extern int _rtw_write16(_adapter *adapter, u32 addr, u16 val);
extern int _rtw_write32(_adapter *adapter, u32 addr, u32 val);
extern int _rtw_writeN(_adapter *adapter, u32 addr, u32 length, u8 *pdata);
extern int rtw_write8(_adapter *adapter, u32 addr, u8 val);
extern int rtw_write16(_adapter *adapter, u32 addr, u16 val);
extern int rtw_write32(_adapter *adapter, u32 addr, u32 val);
extern int rtw_writeN(_adapter *adapter, u32 addr, u32 length, u8 *pdata);
#ifdef CONFIG_SDIO_HCI
u8 _rtw_sd_f0_read8(_adapter *adapter, u32 addr);
@ -377,15 +377,6 @@ const struct rtw_io_sniff_ent *match_write_sniff(_adapter *adapter, u32 addr, u1
bool match_rf_read_sniff_ranges(_adapter *adapter, u8 path, u32 addr, u32 mask);
bool match_rf_write_sniff_ranges(_adapter *adapter, u8 path, u32 addr, u32 mask);
extern u8 dbg_rtw_read8(_adapter *adapter, u32 addr, const char *caller, const int line);
extern u16 dbg_rtw_read16(_adapter *adapter, u32 addr, const char *caller, const int line);
extern u32 dbg_rtw_read32(_adapter *adapter, u32 addr, const char *caller, const int line);
extern int dbg_rtw_write8(_adapter *adapter, u32 addr, u8 val, const char *caller, const int line);
extern int dbg_rtw_write16(_adapter *adapter, u32 addr, u16 val, const char *caller, const int line);
extern int dbg_rtw_write32(_adapter *adapter, u32 addr, u32 val, const char *caller, const int line);
extern int dbg_rtw_writeN(_adapter *adapter, u32 addr , u32 length , u8 *data, const char *caller, const int line);
#ifdef CONFIG_SDIO_HCI
u8 dbg_rtw_sd_f0_read8(_adapter *adapter, u32 addr, const char *caller, const int line);
#ifdef CONFIG_SDIO_INDIRECT_ACCESS
@ -398,18 +389,10 @@ int dbg_rtw_sd_iwrite32(_adapter *adapter, u32 addr, u32 val, const char *caller
#endif /* CONFIG_SDIO_INDIRECT_ACCESS */
#endif /* CONFIG_SDIO_HCI */
#define rtw_read8(adapter, addr) dbg_rtw_read8((adapter), (addr), __FUNCTION__, __LINE__)
#define rtw_read16(adapter, addr) dbg_rtw_read16((adapter), (addr), __FUNCTION__, __LINE__)
#define rtw_read32(adapter, addr) dbg_rtw_read32((adapter), (addr), __FUNCTION__, __LINE__)
#define rtw_read_mem(adapter, addr, cnt, mem) _rtw_read_mem((adapter), (addr), (cnt), (mem))
#define rtw_read_port(adapter, addr, cnt, mem) _rtw_read_port((adapter), (addr), (cnt), (mem))
#define rtw_read_port_cancel(adapter) _rtw_read_port_cancel((adapter))
#define rtw_write8(adapter, addr, val) dbg_rtw_write8((adapter), (addr), (val), __FUNCTION__, __LINE__)
#define rtw_write16(adapter, addr, val) dbg_rtw_write16((adapter), (addr), (val), __FUNCTION__, __LINE__)
#define rtw_write32(adapter, addr, val) dbg_rtw_write32((adapter), (addr), (val), __FUNCTION__, __LINE__)
#define rtw_writeN(adapter, addr, length, data) dbg_rtw_writeN((adapter), (addr), (length), (data), __FUNCTION__, __LINE__)
#define rtw_write8_async(adapter, addr, val) _rtw_write8_async((adapter), (addr), (val))
#define rtw_write16_async(adapter, addr, val) _rtw_write16_async((adapter), (addr), (val))
#define rtw_write32_async(adapter, addr, val) _rtw_write32_async((adapter), (addr), (val))
@ -432,17 +415,10 @@ int dbg_rtw_sd_iwrite32(_adapter *adapter, u32 addr, u32 val, const char *caller
#endif /* CONFIG_SDIO_HCI */
#else /* DBG_IO */
#define rtw_read8(adapter, addr) _rtw_read8((adapter), (addr))
#define rtw_read16(adapter, addr) _rtw_read16((adapter), (addr))
#define rtw_read32(adapter, addr) _rtw_read32((adapter), (addr))
#define rtw_read_mem(adapter, addr, cnt, mem) _rtw_read_mem((adapter), (addr), (cnt), (mem))
#define rtw_read_port(adapter, addr, cnt, mem) _rtw_read_port((adapter), (addr), (cnt), (mem))
#define rtw_read_port_cancel(adapter) _rtw_read_port_cancel((adapter))
#define rtw_write8(adapter, addr, val) _rtw_write8((adapter), (addr), (val))
#define rtw_write16(adapter, addr, val) _rtw_write16((adapter), (addr), (val))
#define rtw_write32(adapter, addr, val) _rtw_write32((adapter), (addr), (val))
#define rtw_writeN(adapter, addr, length, data) _rtw_writeN((adapter), (addr), (length), (data))
#define rtw_write8_async(adapter, addr, val) _rtw_write8_async((adapter), (addr), (val))
#define rtw_write16_async(adapter, addr, val) _rtw_write16_async((adapter), (addr), (val))
@ -509,36 +485,4 @@ extern void bus_sync_io(struct io_queue *pio_q);
extern u32 _ioreq2rwmem(struct io_queue *pio_q);
extern void dev_power_down(_adapter *Adapter, u8 bpwrup);
/*
#define RTL_R8(reg) rtw_read8(padapter, reg)
#define RTL_R16(reg) rtw_read16(padapter, reg)
#define RTL_R32(reg) rtw_read32(padapter, reg)
#define RTL_W8(reg, val8) rtw_write8(padapter, reg, val8)
#define RTL_W16(reg, val16) rtw_write16(padapter, reg, val16)
#define RTL_W32(reg, val32) rtw_write32(padapter, reg, val32)
*/
/*
#define RTL_W8_ASYNC(reg, val8) rtw_write32_async(padapter, reg, val8)
#define RTL_W16_ASYNC(reg, val16) rtw_write32_async(padapter, reg, val16)
#define RTL_W32_ASYNC(reg, val32) rtw_write32_async(padapter, reg, val32)
#define RTL_WRITE_BB(reg, val32) phy_SetUsbBBReg(padapter, reg, val32)
#define RTL_READ_BB(reg) phy_QueryUsbBBReg(padapter, reg)
*/
#define PlatformEFIOWrite1Byte(_a, _b, _c) \
rtw_write8(_a, _b, _c)
#define PlatformEFIOWrite2Byte(_a, _b, _c) \
rtw_write16(_a, _b, _c)
#define PlatformEFIOWrite4Byte(_a, _b, _c) \
rtw_write32(_a, _b, _c)
#define PlatformEFIORead1Byte(_a, _b) \
rtw_read8(_a, _b)
#define PlatformEFIORead2Byte(_a, _b) \
rtw_read16(_a, _b)
#define PlatformEFIORead4Byte(_a, _b) \
rtw_read32(_a, _b)
#endif /* _RTL8711_IO_H_ */

8
os_dep/linux/ioctl_mp.c
View File

@ -1087,10 +1087,10 @@ int rtw_mp_arx(struct net_device *dev,
if (pmppriv->bloopback == _TRUE) {
sprintf(extra , "Enter MAC LoopBack mode\n");
_rtw_write32(padapter, 0x100, 0xB0106FF);
RTW_INFO("0x100 :0x%x" , _rtw_read32(padapter, 0x100));
_rtw_write16(padapter, 0x608, 0x30c);
RTW_INFO("0x100 :0x%x" , _rtw_read32(padapter, 0x608));
rtw_write32(padapter, 0x100, 0xB0106FF);
RTW_INFO("0x100 :0x%x" , rtw_read32(padapter, 0x100));
rtw_write16(padapter, 0x608, 0x30c);
RTW_INFO("0x100 :0x%x" , rtw_read32(padapter, 0x608));
}
wrqu->length = strlen(extra) + 1;