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Updated to 4.4.1

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This commit is contained in:
CGarces
2017-05-11 20:47:23 +02:00
parent 9dde4572b4
commit 3d6c7de21a
396 changed files with 174471 additions and 106990 deletions
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9
include/Hal8188EPhyCfg.h
View File

@@ -40,8 +40,6 @@
/*------------------------------Define structure----------------------------*/
#define MAX_PG_GROUP 13
#define MAX_TX_COUNT_8188E 1
/* BB/RF related */
@@ -90,9 +88,6 @@ int PHY_RFConfig8188E(IN PADAPTER Adapter );
/* RF config */
int rtl8188e_PHY_ConfigRFWithParaFile(IN PADAPTER Adapter, IN u8 * pFileName, u8 eRFPath);
/* Read initi reg value for tx power setting. */
void rtl8192c_PHY_GetHWRegOriginalValue( IN PADAPTER Adapter );
//
// RF Power setting
//
@@ -164,6 +159,10 @@ PHY_SetSwChnlBWMode8188E(
IN u8 Offset80
);
VOID
PHY_SetRFEReg_8188E(
IN PADAPTER Adapter
);
//
// BB/MAC/RF other monitor API
//

5
include/Hal8188EPhyReg.h
View File

@@ -420,14 +420,9 @@
#define RF_TX_BB1 0x23 //
//#if HARDWARE_TYPE_IS_RTL8192D == 1
#define RF_T_METER_92D 0x42 //
//#else
#define RF_T_METER_88E 0x42 //
#define RF_T_METER 0x24 //
//#endif
#define RF_SYN_G1 0x25 // RF TX Power control
#define RF_SYN_G2 0x26 // RF TX Power control
#define RF_SYN_G3 0x27 // RF TX Power control

149
include/Hal8188FPhyCfg.h Normal file
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@@ -0,0 +1,149 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __INC_HAL8188FPHYCFG_H__
#define __INC_HAL8188FPHYCFG_H__
/*--------------------------Define Parameters-------------------------------*/
#define LOOP_LIMIT 5
#define MAX_STALL_TIME 50 //us
#define AntennaDiversityValue 0x80 //(Adapter->bSoftwareAntennaDiversity ? 0x00:0x80)
#define MAX_TXPWR_IDX_NMODE_92S 63
#define Reset_Cnt_Limit 3
#ifdef CONFIG_PCI_HCI
#define MAX_AGGR_NUM 0x0B
#else
#define MAX_AGGR_NUM 0x07
#endif // CONFIG_PCI_HCI
/*--------------------------Define Parameters End-------------------------------*/
/*------------------------------Define structure----------------------------*/
/*------------------------------Define structure End----------------------------*/
/*--------------------------Exported Function prototype---------------------*/
u32
PHY_QueryBBReg_8188F(
IN PADAPTER Adapter,
IN u32 RegAddr,
IN u32 BitMask
);
VOID
PHY_SetBBReg_8188F(
IN PADAPTER Adapter,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data
);
u32
PHY_QueryRFReg_8188F(
IN PADAPTER Adapter,
IN u8 eRFPath,
IN u32 RegAddr,
IN u32 BitMask
);
VOID
PHY_SetRFReg_8188F(
IN PADAPTER Adapter,
IN u8 eRFPath,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data
);
/* MAC/BB/RF HAL config */
int PHY_BBConfig8188F(PADAPTER Adapter );
int PHY_RFConfig8188F(PADAPTER Adapter );
s32 PHY_MACConfig8188F(PADAPTER padapter);
int
PHY_ConfigRFWithParaFile_8188F(
IN PADAPTER Adapter,
IN u8* pFileName,
RF_PATH eRFPath
);
VOID
PHY_SetTxPowerIndex_8188F(
IN PADAPTER Adapter,
IN u32 PowerIndex,
IN u8 RFPath,
IN u8 Rate
);
u8
PHY_GetTxPowerIndex_8188F(
IN PADAPTER pAdapter,
IN u8 RFPath,
IN u8 Rate,
IN CHANNEL_WIDTH BandWidth,
IN u8 Channel
);
VOID
PHY_GetTxPowerLevel8188F(
IN PADAPTER Adapter,
OUT s32* powerlevel
);
VOID
PHY_SetTxPowerLevel8188F(
IN PADAPTER Adapter,
IN u8 channel
);
VOID
PHY_SetBWMode8188F(
IN PADAPTER Adapter,
IN CHANNEL_WIDTH Bandwidth, // 20M or 40M
IN unsigned char Offset // Upper, Lower, or Don't care
);
VOID
PHY_SwChnl8188F( // Call after initialization
IN PADAPTER Adapter,
IN u8 channel
);
VOID
PHY_SetSwChnlBWMode8188F(
IN PADAPTER Adapter,
IN u8 channel,
IN CHANNEL_WIDTH Bandwidth,
IN u8 Offset40,
IN u8 Offset80
);
VOID PHY_SetRFPathSwitch_8188F(
IN PADAPTER pAdapter,
IN BOOLEAN bMain
);
/*--------------------------Exported Function prototype End---------------------*/
#endif

96
include/Hal8192CPhyReg.h → include/Hal8188FPhyReg.h
View File

@@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@@ -17,37 +17,13 @@
*
*
******************************************************************************/
/*****************************************************************************
*
* Module: __INC_HAL8192CPHYREG_H
*
*
* Note: 1. Define PMAC/BB register map
* 2. Define RF register map
* 3. PMAC/BB register bit mask.
* 4. RF reg bit mask.
* 5. Other BB/RF relative definition.
*
*
* Export: Constants, macro, functions(API), global variables(None).
*
* Abbrev:
*
* History:
* Data Who Remark
* 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h.
* 2. Reorganize code architecture.
* 09/25/2008 MH 1. Add RL6052 register definition
*
*****************************************************************************/
#ifndef __INC_HAL8192CPHYREG_H
#define __INC_HAL8192CPHYREG_H
#ifndef __INC_HAL8188FPHYREG_H__
#define __INC_HAL8188FPHYREG_H__
/*--------------------------Define Parameters-------------------------------*/
//============================================================
// 8192S Regsiter offset definition
// Regsiter offset definition
//============================================================
//
@@ -474,9 +450,13 @@
#define RF_TXPA_G4 0x46
#define RF_TXPA_A4 0x4B
#define RF_0x52 0x52
#define RF_RXG_MIX_SWBW 0x87
#define RF_DBG_LP_RX2 0xDF
#define RF_WE_LUT 0xEF
#define RF_S0S1 0xB0
#define RF_TX_GAIN_OFFSET_8188F(_val) (abs((_val)) | (((_val) > 0) ? BIT5 : 0))
//
//Bit Mask
//
@@ -1129,5 +1109,63 @@
/*--------------------------Define Parameters-------------------------------*/
#endif //__INC_HAL8192SPHYREG_H
// BB Register Definition
//
// 4. Page9(0x900)
//
#define rDPDT_control 0x92c
#define rfe_ctrl_anta_src 0x930
#define rS0S1_PathSwitch 0x948
#define BBrx_DFIR 0x954
#define AGC_table_select 0xb2c
//
// PageB(0xB00)
//
#define rPdp_AntA 0xb00
#define rPdp_AntA_4 0xb04
#define rPdp_AntA_8 0xb08
#define rPdp_AntA_C 0xb0c
#define rPdp_AntA_10 0xb10
#define rPdp_AntA_14 0xb14
#define rPdp_AntA_18 0xb18
#define rPdp_AntA_1C 0xb1c
#define rPdp_AntA_20 0xb20
#define rPdp_AntA_24 0xb24
#define rConfig_Pmpd_AntA 0xb28
#define rConfig_ram64x16 0xb2c
#define rBndA 0xb30
#define rHssiPar 0xb34
#define rConfig_AntA 0xb68
#define rConfig_AntB 0xb6c
#define rPdp_AntB 0xb70
#define rPdp_AntB_4 0xb74
#define rPdp_AntB_8 0xb78
#define rPdp_AntB_C 0xb7c
#define rPdp_AntB_10 0xb80
#define rPdp_AntB_14 0xb84
#define rPdp_AntB_18 0xb88
#define rPdp_AntB_1C 0xb8c
#define rPdp_AntB_20 0xb90
#define rPdp_AntB_24 0xb94
#define rConfig_Pmpd_AntB 0xb98
#define rBndB 0xba0
#define rAPK 0xbd8
#define rPm_Rx0_AntA 0xbdc
#define rPm_Rx1_AntA 0xbe0
#define rPm_Rx2_AntA 0xbe4
#define rPm_Rx3_AntA 0xbe8
#define rPm_Rx0_AntB 0xbec
#define rPm_Rx1_AntB 0xbf0
#define rPm_Rx2_AntB 0xbf4
#define rPm_Rx3_AntB 0xbf8
#endif

199
include/Hal8188FPwrSeq.h Normal file
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@@ -0,0 +1,199 @@
#ifndef REALTEK_POWER_SEQUENCE_8188F
#define REALTEK_POWER_SEQUENCE_8188F
#include "HalPwrSeqCmd.h"
/*
Check document WM-20130815-JackieLau-RTL8188F_Power_Architecture v08.vsd
There are 6 HW Power States:
0: POFF--Power Off
1: PDN--Power Down
2: CARDEMU--Card Emulation
3: ACT--Active Mode
4: LPS--Low Power State
5: SUS--Suspend
The transision from different states are defined below
TRANS_CARDEMU_TO_ACT
TRANS_ACT_TO_CARDEMU
TRANS_CARDEMU_TO_SUS
TRANS_SUS_TO_CARDEMU
TRANS_CARDEMU_TO_PDN
TRANS_ACT_TO_LPS
TRANS_LPS_TO_ACT
TRANS_END
*/
#define RTL8188F_TRANS_CARDEMU_TO_ACT_STEPS 13
#define RTL8188F_TRANS_ACT_TO_CARDEMU_STEPS 15
#define RTL8188F_TRANS_CARDEMU_TO_SUS_STEPS 14
#define RTL8188F_TRANS_SUS_TO_CARDEMU_STEPS 15
#define RTL8188F_TRANS_CARDEMU_TO_PDN_STEPS 15
#define RTL8188F_TRANS_PDN_TO_CARDEMU_STEPS 15
#define RTL8188F_TRANS_ACT_TO_LPS_STEPS 11
#define RTL8188F_TRANS_LPS_TO_ACT_STEPS 13
#define RTL8188F_TRANS_ACT_TO_SWLPS_STEPS 21
#define RTL8188F_TRANS_SWLPS_TO_ACT_STEPS 14
#define RTL8188F_TRANS_END_STEPS 1
#define RTL8188F_TRANS_CARDEMU_TO_ACT \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, 0},/* disable SW LPS 0x04[10]=0*/ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT3), 0},/* 0x4[11]=1'b0 disable WL suspend*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* 0x4[8]=1 polling until return 0*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0, 0},/**/ \
{0x0027, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xff, 0x35}, /*0x27<=35 to reduce RF noise*/
#define RTL8188F_TRANS_ACT_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/ \
{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/*0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */\
{0x0027, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xff, 0x34}, /*0x27 <= 34, xtal_qsel=0 to xtal bring up*/\
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \
#define RTL8188F_TRANS_CARDEMU_TO_SUS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00}, /*0x07=0x00 , SOP option to disable BG/MB*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/ \
{0x00C4, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4},/* 0xC4[4] <= 1, turn off USB APHY LDO under suspend mode*/
#define RTL8188F_TRANS_SUS_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/ \
{0x00C4, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0},/* 0xC4[4] <= 1, turn off USB APHY LDO under suspend mode*/
#define RTL8188F_TRANS_CARDEMU_TO_CARDDIS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00}, /*0x07=0x00 , SOP option to disable BG/MB*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/ \
{0x00C4, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4},/* 0xC4[4] <= 1, turn off USB APHY LDO under suspend mode*/
#define RTL8188F_TRANS_CARDDIS_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/ \
{0x00C4, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0},/* 0xC4[4] <= 1, turn off USB APHY LDO under suspend mode*/
#define RTL8188F_TRANS_CARDEMU_TO_PDN \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
#define RTL8188F_TRANS_PDN_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
#define RTL8188F_TRANS_ACT_TO_LPS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0139, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/*set RPWM IMR*/ \
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/ \
{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/ \
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/ \
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \
{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/
#define RTL8188F_TRANS_LPS_TO_ACT \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
{0x0027, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xff,0x35},/*xtal_qsel=1 for low noise*/ \
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0 TSF in 40M*/\
{0x002B, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x1c, 0x1c}, /*. 0x2b[4:2] = 3b'111 to enable BB,AFE clock*/\
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/\
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
#define RTL8188F_TRANS_ACT_TO_SWLPS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0139, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*set RPWM IMR*/ \
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/ \
{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/ \
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/ \
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \
{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/ \
{0x002b, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x1C, 0x00},/*0x2b[4:2]<=0 to gated BB,AFE clock*/ \
{0x0027, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xff, 0x34},/*xtal_qsel=0 for bring up*/ \
{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xff, 0x00},/* sdio LPS option*/ \
{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xff, 0x83},/* usb LPS option, open bandgap, xtal*/ \
{0x00C4, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0}, /* 0xC4[5]<=0, digital LDO no standby mode*/ \
{0x00C4, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7}, /* 0xC4[7]<=1, on domain voltage adjust*/ \
{0x00a7, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xff, 0xe0}, /* low power LPS enable for sdio*/ \
{0x00a7, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xff, 0xe4}, /* low power LPS enable for usb*/ \
{0x0090, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /* enable WL_LPS_EN*/
#define RTL8188F_TRANS_SWLPS_TO_ACT \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/*polling TSF stable*/\
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1, enable security engine*/\
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\
{0x06B7, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x09}, /*. reset MAC rx state machine*/\
{0x06B4, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x86}, /*. reset MAC rx state machine*/\
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1},/* set CPU RAM code ready*/ \
{0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*Reset CPU IO Wrapper*/ \
{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, 0},/* Enable CPU*/ \
{0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/*enable CPU IO Wrapper*/ \
{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, BIT2},/* Enable CPU*/ \
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT7, BIT7},/*polling FW init ready */ \
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT6, BIT6},/*polling FW init ready */ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
#define RTL8188F_TRANS_END \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0,PWR_CMD_END, 0, 0}, //
extern WLAN_PWR_CFG rtl8188F_power_on_flow[RTL8188F_TRANS_CARDEMU_TO_ACT_STEPS+RTL8188F_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8188F_radio_off_flow[RTL8188F_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188F_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8188F_card_disable_flow[RTL8188F_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188F_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188F_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8188F_card_enable_flow[RTL8188F_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188F_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188F_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8188F_suspend_flow[RTL8188F_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188F_TRANS_CARDEMU_TO_SUS_STEPS+RTL8188F_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8188F_resume_flow[RTL8188F_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188F_TRANS_CARDEMU_TO_SUS_STEPS+RTL8188F_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8188F_hwpdn_flow[RTL8188F_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188F_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188F_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8188F_enter_lps_flow[RTL8188F_TRANS_ACT_TO_LPS_STEPS+RTL8188F_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8188F_leave_lps_flow[RTL8188F_TRANS_LPS_TO_ACT_STEPS+RTL8188F_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8188F_enter_swlps_flow[RTL8188F_TRANS_ACT_TO_SWLPS_STEPS+RTL8188F_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8188F_leave_swlps_flow[RTL8188F_TRANS_SWLPS_TO_ACT_STEPS+RTL8188F_TRANS_END_STEPS];
#endif

241
include/Hal8192CPhyCfg.h
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@@ -1,241 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/*****************************************************************************
* Module: __INC_HAL8192CPHYCFG_H
*
*
* Note:
*
*
* Export: Constants, macro, functions(API), global variables(None).
*
* Abbrev:
*
* History:
* Data Who Remark
* 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h.
* 2. Reorganize code architecture.
*
*****************************************************************************/
/* Check to see if the file has been included already. */
#ifndef __INC_HAL8192CPHYCFG_H
#define __INC_HAL8192CPHYCFG_H
/*--------------------------Define Parameters-------------------------------*/
#define LOOP_LIMIT 5
#define MAX_STALL_TIME 50 //us
#define AntennaDiversityValue 0x80 //(Adapter->bSoftwareAntennaDiversity ? 0x00:0x80)
#define MAX_TXPWR_IDX_NMODE_92S 63
#define Reset_Cnt_Limit 3
#ifdef CONFIG_PCI_HCI
#define MAX_AGGR_NUM 0x0A0A
#else
#define MAX_AGGR_NUM 0x0909
#endif
#ifdef CONFIG_PCI_HCI
#define SET_RTL8192SE_RF_SLEEP(_pAdapter) \
{ \
u1Byte u1bTmp; \
u1bTmp = PlatformEFIORead1Byte(_pAdapter, REG_LDOV12D_CTRL); \
u1bTmp |= BIT0; \
PlatformEFIOWrite1Byte(_pAdapter, REG_LDOV12D_CTRL, u1bTmp); \
PlatformEFIOWrite1Byte(_pAdapter, REG_SPS_OCP_CFG, 0x0); \
PlatformEFIOWrite1Byte(_pAdapter, TXPAUSE, 0xFF); \
PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x57FC); \
delay_us(100); \
PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x77FC); \
PlatformEFIOWrite1Byte(_pAdapter, PHY_CCA, 0x0); \
delay_us(10); \
PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x37FC); \
delay_us(10); \
PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x77FC); \
delay_us(10); \
PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x57FC); \
}
#endif
/*--------------------------Define Parameters-------------------------------*/
/*------------------------------Define structure----------------------------*/
/* BB/RF related */
/*------------------------------Define structure----------------------------*/
/*------------------------Export global variable----------------------------*/
/*------------------------Export global variable----------------------------*/
/*------------------------Export Marco Definition---------------------------*/
/*------------------------Export Marco Definition---------------------------*/
/*--------------------------Exported Function prototype---------------------*/
//
// BB and RF register read/write
//
u32 PHY_QueryBBReg8192C( IN PADAPTER Adapter,
IN u32 RegAddr,
IN u32 BitMask );
void PHY_SetBBReg8192C( IN PADAPTER Adapter,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data );
u32 PHY_QueryRFReg8192C( IN PADAPTER Adapter,
IN u8 eRFPath,
IN u32 RegAddr,
IN u32 BitMask );
void PHY_SetRFReg8192C( IN PADAPTER Adapter,
IN u8 eRFPath,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data );
//
// Initialization related function
//
/* MAC/BB/RF HAL config */
int PHY_MACConfig8192C( IN PADAPTER Adapter );
int PHY_BBConfig8192C( IN PADAPTER Adapter );
int PHY_RFConfig8192C( IN PADAPTER Adapter );
/* RF config */
int rtl8192c_PHY_ConfigRFWithParaFile( IN PADAPTER Adapter,
IN u8* pFileName,
IN u8 eRFPath);
int rtl8192c_PHY_ConfigRFWithHeaderFile( IN PADAPTER Adapter,
IN u8 eRFPath);
/* BB/RF readback check for making sure init OK */
int rtl8192c_PHY_CheckBBAndRFOK( IN PADAPTER Adapter,
IN HW_BLOCK_E CheckBlock,
IN u8 eRFPath );
/* Read initi reg value for tx power setting. */
void rtl8192c_PHY_GetHWRegOriginalValue( IN PADAPTER Adapter );
//
// RF Power setting
//
//extern BOOLEAN PHY_SetRFPowerState(IN PADAPTER Adapter,
// IN RT_RF_POWER_STATE eRFPowerState);
//
// BB TX Power R/W
//
void PHY_GetTxPowerLevel8192C( IN PADAPTER Adapter,
OUT s32* powerlevel );
void PHY_SetTxPowerLevel8192C( IN PADAPTER Adapter,
IN u8 channel );
BOOLEAN PHY_UpdateTxPowerDbm8192C( IN PADAPTER Adapter,
IN int powerInDbm );
//
VOID
PHY_ScanOperationBackup8192C(IN PADAPTER Adapter,
IN u8 Operation );
//
// Switch bandwidth for 8192S
//
//extern void PHY_SetBWModeCallback8192C( IN PRT_TIMER pTimer );
void PHY_SetBWMode8192C( IN PADAPTER pAdapter,
IN CHANNEL_WIDTH ChnlWidth,
IN unsigned char Offset );
//
// Set FW CMD IO for 8192S.
//
//extern BOOLEAN HalSetIO8192C( IN PADAPTER Adapter,
// IN IO_TYPE IOType);
//
// Set A2 entry to fw for 8192S
//
extern void FillA2Entry8192C( IN PADAPTER Adapter,
IN u8 index,
IN u8* val);
//
// channel switch related funciton
//
//extern void PHY_SwChnlCallback8192C( IN PRT_TIMER pTimer );
void PHY_SwChnl8192C( IN PADAPTER pAdapter,
IN u8 channel );
VOID
PHY_SetSwChnlBWMode8192C(
IN PADAPTER Adapter,
IN u8 channel,
IN CHANNEL_WIDTH Bandwidth,
IN u8 Offset40,
IN u8 Offset80
);
//
// BB/MAC/RF other monitor API
//
void PHY_SetMonitorMode8192C(IN PADAPTER pAdapter,
IN BOOLEAN bEnableMonitorMode );
BOOLEAN PHY_CheckIsLegalRfPath8192C(IN PADAPTER pAdapter,
IN u32 eRFPath );
VOID rtl8192c_PHY_SetRFPathSwitch(IN PADAPTER pAdapter, IN BOOLEAN bMain);
//
// Modify the value of the hw register when beacon interval be changed.
//
void
rtl8192c_PHY_SetBeaconHwReg( IN PADAPTER Adapter,
IN u16 BeaconInterval );
extern VOID
PHY_SwitchEphyParameter(
IN PADAPTER Adapter
);
extern VOID
PHY_EnableHostClkReq(
IN PADAPTER Adapter
);
BOOLEAN
SetAntennaConfig92C(
IN PADAPTER Adapter,
IN u8 DefaultAnt
);
#ifdef RTL8192C_RECONFIG_TO_1T1R
extern void PHY_Reconfig_To_1T1R(_adapter *padapter);
#endif
/*--------------------------Exported Function prototype---------------------*/
#endif // __INC_HAL8192CPHYCFG_H

293
include/Hal8192DPhyCfg.h
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@@ -1,293 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/*****************************************************************************
*
* Module: __INC_HAL8192DPHYCFG_H
*
*
* Note:
*
*
* Export: Constants, macro, functions(API), global variables(None).
*
* Abbrev:
*
* History:
* Data Who Remark
* 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h.
* 2. Reorganize code architecture.
*
*****************************************************************************/
/* Check to see if the file has been included already. */
#ifndef __INC_HAL8192DPHYCFG_H
#define __INC_HAL8192DPHYCFG_H
/*--------------------------Define Parameters-------------------------------*/
#define LOOP_LIMIT 5
#define MAX_STALL_TIME 50 //us
#define AntennaDiversityValue 0x80 //(Adapter->bSoftwareAntennaDiversity ? 0x00:0x80)
#define MAX_TXPWR_IDX_NMODE_92S 63
#define Reset_Cnt_Limit 3
#ifdef CONFIG_PCI_HCI
#define SET_RTL8192SE_RF_SLEEP(_pAdapter) \
{ \
u1Byte u1bTmp; \
u1bTmp = PlatformEFIORead1Byte(_pAdapter, REG_LDOV12D_CTRL); \
u1bTmp |= BIT0; \
PlatformEFIOWrite1Byte(_pAdapter, REG_LDOV12D_CTRL, u1bTmp); \
PlatformEFIOWrite1Byte(_pAdapter, REG_SPS_OCP_CFG, 0x0); \
PlatformEFIOWrite1Byte(_pAdapter, TXPAUSE, 0xFF); \
PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x57FC); \
delay_us(100); \
PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x77FC); \
PlatformEFIOWrite1Byte(_pAdapter, PHY_CCA, 0x0); \
delay_us(10); \
PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x37FC); \
delay_us(10); \
PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x77FC); \
delay_us(10); \
PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x57FC); \
}
#endif
/*--------------------------Define Parameters-------------------------------*/
/*------------------------------Define structure----------------------------*/
#define CHANNEL_GROUP_MAX_2G 3
#define CHANNEL_GROUP_IDX_5GL 3
#define CHANNEL_GROUP_IDX_5GM 6
#define CHANNEL_GROUP_IDX_5GH 9
#define CHANNEL_GROUP_MAX_5G 9
#define CHANNEL_MAX_NUMBER_2G 14
typedef enum _MACPHY_MODE_CHANGE_ACTION{
DMDP2DMSP = 0,
DMSP2DMDP = 1,
DMDP2SMSP = 2,
SMSP2DMDP = 3,
DMSP2SMSP = 4,
SMSP2DMSP = 5,
MAXACTION
}MACPHY_MODE_CHANGE_ACTION,*PMACPHY_MODE_CHANGE_ACTION;
/* BB/RF related */
/*------------------------------Define structure----------------------------*/
/*------------------------Export global variable----------------------------*/
/*------------------------Export global variable----------------------------*/
/*------------------------Export Marco Definition---------------------------*/
/*--------------------------Exported Function prototype---------------------*/
//
// BB and RF register read/write
//
void PHY_SetBBReg1Byte8192D( IN PADAPTER Adapter,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data );
u32 PHY_QueryBBReg8192D( IN PADAPTER Adapter,
IN u32 RegAddr,
IN u32 BitMask );
void PHY_SetBBReg8192D( IN PADAPTER Adapter,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data );
u32 PHY_QueryRFReg8192D( IN PADAPTER Adapter,
IN u8 eRFPath,
IN u32 RegAddr,
IN u32 BitMask );
void PHY_SetRFReg8192D( IN PADAPTER Adapter,
IN u8 eRFPath,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data );
//
// Initialization related function
//
/* MAC/BB/RF HAL config */
extern int PHY_MACConfig8192D( IN PADAPTER Adapter );
extern int PHY_BBConfig8192D( IN PADAPTER Adapter );
extern int PHY_RFConfig8192D( IN PADAPTER Adapter );
/* RF config */
int rtl8192d_PHY_ConfigRFWithParaFile( IN PADAPTER Adapter,
IN u8* pFileName,
IN u8 eRFPath);
int rtl8192d_PHY_ConfigRFWithHeaderFile( IN PADAPTER Adapter,
IN RF_CONTENT Content,
IN u8 eRFPath);
/* BB/RF readback check for making sure init OK */
int rtl8192d_PHY_CheckBBAndRFOK( IN PADAPTER Adapter,
IN HW_BLOCK_E CheckBlock,
IN u8 eRFPath );
/* Read initi reg value for tx power setting. */
void rtl8192d_PHY_GetHWRegOriginalValue( IN PADAPTER Adapter );
//
// RF Power setting
//
//extern BOOLEAN PHY_SetRFPowerState(IN PADAPTER Adapter,
// IN RT_RF_POWER_STATE eRFPowerState);
//
// BB TX Power R/W
//
void PHY_GetTxPowerLevel8192D( IN PADAPTER Adapter,
OUT s32* powerlevel );
void PHY_SetTxPowerLevel8192D( IN PADAPTER Adapter,
IN u8 channel );
BOOLEAN PHY_UpdateTxPowerDbm8192D( IN PADAPTER Adapter,
IN int powerInDbm );
//
VOID
PHY_ScanOperationBackup8192D(IN PADAPTER Adapter,
IN u8 Operation );
//
// Switch bandwidth for 8192S
//
//void PHY_SetBWModeCallback8192C( IN PRT_TIMER pTimer );
void PHY_SetBWMode8192D( IN PADAPTER pAdapter,
IN CHANNEL_WIDTH ChnlWidth,
IN unsigned char Offset );
//
// Set FW CMD IO for 8192S.
//
//extern BOOLEAN HalSetIO8192C( IN PADAPTER Adapter,
// IN IO_TYPE IOType);
//
// Set A2 entry to fw for 8192S
//
extern void FillA2Entry8192C( IN PADAPTER Adapter,
IN u8 index,
IN u8* val);
//
// channel switch related funciton
//
//extern void PHY_SwChnlCallback8192C( IN PRT_TIMER pTimer );
void PHY_SwChnl8192D( IN PADAPTER pAdapter,
IN u8 channel );
VOID
PHY_SetSwChnlBWMode8192D(
IN PADAPTER Adapter,
IN u8 channel,
IN CHANNEL_WIDTH Bandwidth,
IN u8 Offset40,
IN u8 Offset80
);
//
// BB/MAC/RF other monitor API
//
void PHY_SetMonitorMode8192D(IN PADAPTER pAdapter,
IN BOOLEAN bEnableMonitorMode );
BOOLEAN PHY_CheckIsLegalRfPath8192D(IN PADAPTER pAdapter,
IN u32 eRFPath );
//
// Modify the value of the hw register when beacon interval be changed.
//
void
rtl8192d_PHY_SetBeaconHwReg( IN PADAPTER Adapter,
IN u16 BeaconInterval );
extern VOID
PHY_SwitchEphyParameter(
IN PADAPTER Adapter
);
extern VOID
PHY_EnableHostClkReq(
IN PADAPTER Adapter
);
BOOLEAN
SetAntennaConfig92C(
IN PADAPTER Adapter,
IN u8 DefaultAnt
);
VOID
PHY_UpdateBBRFConfiguration8192D(
IN PADAPTER Adapter,
IN BOOLEAN bisBandSwitch
);
VOID PHY_ReadMacPhyMode92D(
IN PADAPTER Adapter,
IN BOOLEAN AutoloadFail
);
VOID PHY_ConfigMacPhyMode92D(
IN PADAPTER Adapter
);
VOID PHY_ConfigMacPhyModeInfo92D(
IN PADAPTER Adapter
);
VOID PHY_ConfigMacCoexist_RFPage92D(
IN PADAPTER Adapter
);
VOID
rtl8192d_PHY_InitRxSetting(
IN PADAPTER Adapter
);
VOID
rtl8192d_PHY_SetRFPathSwitch(IN PADAPTER pAdapter, IN BOOLEAN bMain);
VOID
HalChangeCCKStatus8192D(
IN PADAPTER Adapter,
IN BOOLEAN bCCKDisable
);
VOID
PHY_InitPABias92D(IN PADAPTER Adapter);
/*--------------------------Exported Function prototype---------------------*/
#define PHY_SetBBReg1Byte(Adapter, RegAddr, BitMask, Data) PHY_SetBBReg1Byte8192D((Adapter), (RegAddr), (BitMask), (Data))
#endif // __INC_HAL8192SPHYCFG_H

6
include/Hal8192EPhyCfg.h
View File

@@ -137,11 +137,17 @@ PHY_SetSwChnlBWMode8192E(
IN u8 Offset80
);
VOID
PHY_SetRFEReg_8192E(
IN PADAPTER Adapter
);
void
phy_SpurCalibration_8192E(
IN PADAPTER Adapter,
IN SPUR_CAL_METHOD Method
);
void PHY_SpurCalibration_8192E(IN PADAPTER Adapter);
#ifdef CONFIG_SPUR_CAL_NBI
void

2
include/Hal8192EPhyReg.h
View File

@@ -508,6 +508,8 @@
#define bOFDMTxStatus 0x2
#define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff))
#define RF_TX_GAIN_OFFSET_8192E(_val) ((abs((_val)) << 1) | (((_val) > 0) ? BIT0 : 0))
// 2. Page8(0x800)
#define bRFMOD 0x1 // Reg 0x800 rFPGA0_RFMOD

144
include/Hal8703BPhyCfg.h Normal file
View File

@@ -0,0 +1,144 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __INC_HAL8703BPHYCFG_H__
#define __INC_HAL8703BPHYCFG_H__
/*--------------------------Define Parameters-------------------------------*/
#define LOOP_LIMIT 5
#define MAX_STALL_TIME 50 //us
#define AntennaDiversityValue 0x80 //(Adapter->bSoftwareAntennaDiversity ? 0x00:0x80)
#define MAX_TXPWR_IDX_NMODE_92S 63
#define Reset_Cnt_Limit 3
#ifdef CONFIG_PCI_HCI
#define MAX_AGGR_NUM 0x0B
#else
#define MAX_AGGR_NUM 0x07
#endif // CONFIG_PCI_HCI
/*--------------------------Define Parameters End-------------------------------*/
/*------------------------------Define structure----------------------------*/
/*------------------------------Define structure End----------------------------*/
/*--------------------------Exported Function prototype---------------------*/
u32
PHY_QueryBBReg_8703B(
IN PADAPTER Adapter,
IN u32 RegAddr,
IN u32 BitMask
);
VOID
PHY_SetBBReg_8703B(
IN PADAPTER Adapter,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data
);
u32
PHY_QueryRFReg_8703B(
IN PADAPTER Adapter,
IN u8 eRFPath,
IN u32 RegAddr,
IN u32 BitMask
);
VOID
PHY_SetRFReg_8703B(
IN PADAPTER Adapter,
IN u8 eRFPath,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data
);
/* MAC/BB/RF HAL config */
int PHY_BBConfig8703B(PADAPTER Adapter );
int PHY_RFConfig8703B(PADAPTER Adapter );
s32 PHY_MACConfig8703B(PADAPTER padapter);
int
PHY_ConfigRFWithParaFile_8703B(
IN PADAPTER Adapter,
IN u8* pFileName,
RF_PATH eRFPath
);
VOID
PHY_SetTxPowerIndex_8703B(
IN PADAPTER Adapter,
IN u32 PowerIndex,
IN u8 RFPath,
IN u8 Rate
);
u8
PHY_GetTxPowerIndex_8703B(
IN PADAPTER pAdapter,
IN u8 RFPath,
IN u8 Rate,
IN CHANNEL_WIDTH BandWidth,
IN u8 Channel
);
VOID
PHY_GetTxPowerLevel8703B(
IN PADAPTER Adapter,
OUT s32* powerlevel
);
VOID
PHY_SetTxPowerLevel8703B(
IN PADAPTER Adapter,
IN u8 channel
);
VOID
PHY_SetBWMode8703B(
IN PADAPTER Adapter,
IN CHANNEL_WIDTH Bandwidth, // 20M or 40M
IN unsigned char Offset // Upper, Lower, or Don't care
);
VOID
PHY_SwChnl8703B( // Call after initialization
IN PADAPTER Adapter,
IN u8 channel
);
VOID
PHY_SetSwChnlBWMode8703B(
IN PADAPTER Adapter,
IN u8 channel,
IN CHANNEL_WIDTH Bandwidth,
IN u8 Offset40,
IN u8 Offset80
);
/*--------------------------Exported Function prototype End---------------------*/
#endif

2307
include/Hal8192DPhyReg.h → include/Hal8703BPhyReg.h
View File

File diff suppressed because it is too large Load Diff

184
include/Hal8703BPwrSeq.h Normal file
View File

@@ -0,0 +1,184 @@
#ifndef REALTEK_POWER_SEQUENCE_8703B
#define REALTEK_POWER_SEQUENCE_8703B
#include "HalPwrSeqCmd.h"
/*
Check document WM-20140402-JackieLau-RTL8703B_Power_Architecture v09.vsd
There are 6 HW Power States:
0: POFF--Power Off
1: PDN--Power Down
2: CARDEMU--Card Emulation
3: ACT--Active Mode
4: LPS--Low Power State
5: SUS--Suspend
The transision from different states are defined below
TRANS_CARDEMU_TO_ACT
TRANS_ACT_TO_CARDEMU
TRANS_CARDEMU_TO_SUS
TRANS_SUS_TO_CARDEMU
TRANS_CARDEMU_TO_PDN
TRANS_ACT_TO_LPS
TRANS_LPS_TO_ACT
TRANS_END
*/
#define RTL8703B_TRANS_CARDEMU_TO_ACT_STEPS 23
#define RTL8703B_TRANS_ACT_TO_CARDEMU_STEPS 15
#define RTL8703B_TRANS_CARDEMU_TO_SUS_STEPS 15
#define RTL8703B_TRANS_SUS_TO_CARDEMU_STEPS 15
#define RTL8703B_TRANS_CARDEMU_TO_PDN_STEPS 15
#define RTL8703B_TRANS_PDN_TO_CARDEMU_STEPS 15
#define RTL8703B_TRANS_ACT_TO_LPS_STEPS 15
#define RTL8703B_TRANS_LPS_TO_ACT_STEPS 15
#define RTL8703B_TRANS_END_STEPS 1
#define RTL8703B_TRANS_CARDEMU_TO_ACT \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/ \
{0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/ \
{0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/ \
{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0},/* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[11]=0*/ \
{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0 , BIT0},/* Disable USB suspend */ \
{0x0004, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 , BIT3},/* enabled usb resume */ \
{0x0004, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 , 0},/* disable usb resume */ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \
{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0 , 0},/* Enable USB suspend */ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]=1*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT4|BIT3), 0},/* disable WL suspend*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0, 0},/**/ \
{0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, BIT6},/* Enable WL control XTAL setting*/ \
{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1},/*Enable falling edge triggering interrupt*/\
{0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1},/*Enable GPIO9 interrupt mode*/\
{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Enable GPIO9 input mode*/\
{0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/*Enable HSISR GPIO[C:0] interrupt*/\
{0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1},/*Enable HSISR GPIO9 interrupt*/\
{0x0068, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, BIT3},/*For GPIO9 internal pull high setting by test chip*/\
{0x0069, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, BIT6},/*For GPIO9 internal pull high setting*/\
#define RTL8703B_TRANS_ACT_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/ \
{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Enable rising edge triggering interrupt*/ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]=1*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \
{0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, 0},/* Enable BT control XTAL setting*/\
{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/ \
{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/\
#define RTL8703B_TRANS_CARDEMU_TO_SUS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
#define RTL8703B_TRANS_SUS_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
#define RTL8703B_TRANS_CARDEMU_TO_CARDDIS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07=0x20 , SOP option to disable BG/MB*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/ \
{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/ \
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
#define RTL8703B_TRANS_CARDDIS_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/
#define RTL8703B_TRANS_CARDEMU_TO_PDN \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK|PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
#define RTL8703B_TRANS_PDN_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
#define RTL8703B_TRANS_ACT_TO_LPS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/ \
{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/ \
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \
{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/ \
{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/ \
#define RTL8703B_TRANS_LPS_TO_ACT \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0 TSF in 40M*/\
{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6|BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/\
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
#define RTL8703B_TRANS_END \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0,PWR_CMD_END, 0, 0}, //
extern WLAN_PWR_CFG rtl8703B_power_on_flow[RTL8703B_TRANS_CARDEMU_TO_ACT_STEPS+RTL8703B_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8703B_radio_off_flow[RTL8703B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8703B_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8703B_card_disable_flow[RTL8703B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8703B_TRANS_CARDEMU_TO_PDN_STEPS+RTL8703B_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8703B_card_enable_flow[RTL8703B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8703B_TRANS_CARDEMU_TO_PDN_STEPS+RTL8703B_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8703B_suspend_flow[RTL8703B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8703B_TRANS_CARDEMU_TO_SUS_STEPS+RTL8703B_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8703B_resume_flow[RTL8703B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8703B_TRANS_CARDEMU_TO_SUS_STEPS+RTL8703B_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8703B_hwpdn_flow[RTL8703B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8703B_TRANS_CARDEMU_TO_PDN_STEPS+RTL8703B_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8703B_enter_lps_flow[RTL8703B_TRANS_ACT_TO_LPS_STEPS+RTL8703B_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8703B_leave_lps_flow[RTL8703B_TRANS_LPS_TO_ACT_STEPS+RTL8703B_TRANS_END_STEPS];
#endif

39
include/Hal8723APhyCfg.h
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@@ -1,39 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __INC_HAL8723PHYCFG_H__
#define __INC_HAL8723PHYCFG_H__
#include <Hal8192CPhyCfg.h>
/* MAC/BB/RF HAL config */
int PHY_BBConfig8723A( IN PADAPTER Adapter );
int PHY_RFConfig8723A( IN PADAPTER Adapter );
s32 PHY_MACConfig8723A(PADAPTER padapter);
VOID
PHY_SetSwChnlBWMode8723A(
IN PADAPTER Adapter,
IN u8 channel,
IN CHANNEL_WIDTH Bandwidth,
IN u8 Offset40,
IN u8 Offset80
);
#endif

74
include/Hal8723APhyReg.h
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@@ -1,74 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __INC_HAL8723APHYREG_H__
#define __INC_HAL8723APHYREG_H__
#include <Hal8192CPhyReg.h>
//
// PageB(0xB00)
//
#define rPdp_AntA 0xb00
#define rPdp_AntA_4 0xb04
#define rPdp_AntA_8 0xb08
#define rPdp_AntA_C 0xb0c
#define rPdp_AntA_10 0xb10
#define rPdp_AntA_14 0xb14
#define rPdp_AntA_18 0xb18
#define rPdp_AntA_1C 0xb1c
#define rPdp_AntA_20 0xb20
#define rPdp_AntA_24 0xb24
#define rConfig_Pmpd_AntA 0xb28
#define rConfig_ram64x16 0xb2c
#define rBndA 0xb30
#define rHssiPar 0xb34
#define rConfig_AntA 0xb68
#define rConfig_AntB 0xb6c
#define rPdp_AntB 0xb70
#define rPdp_AntB_4 0xb74
#define rPdp_AntB_8 0xb78
#define rPdp_AntB_C 0xb7c
#define rPdp_AntB_10 0xb80
#define rPdp_AntB_14 0xb84
#define rPdp_AntB_18 0xb88
#define rPdp_AntB_1C 0xb8c
#define rPdp_AntB_20 0xb90
#define rPdp_AntB_24 0xb94
#define rConfig_Pmpd_AntB 0xb98
#define rBndB 0xba0
#define rAPK 0xbd8
#define rPm_Rx0_AntA 0xbdc
#define rPm_Rx1_AntA 0xbe0
#define rPm_Rx2_AntA 0xbe4
#define rPm_Rx3_AntA 0xbe8
#define rPm_Rx0_AntB 0xbec
#define rPm_Rx1_AntB 0xbf0
#define rPm_Rx2_AntB 0xbf4
#define rPm_Rx3_AntB 0xbf8
#endif

1066
include/Hal8723BPhyReg.h
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File diff suppressed because it is too large Load Diff

6
include/Hal8812PhyReg.h
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@@ -37,7 +37,8 @@
// BW and sideband setting
#define rBWIndication_Jaguar 0x834
#define rL1PeakTH_Jaguar 0x848
#define rL1PeakTH_Jaguar 0x848
#define rFPGA0_XA_LSSIReadBack 0x8a0 /*Tranceiver LSSI Readback*/
#define rRFMOD_Jaguar 0x8ac //RF mode
#define rADC_Buf_Clk_Jaguar 0x8c4
#define rRFECTRL_Jaguar 0x900
@@ -312,6 +313,9 @@
#define RF_0x52 0x52
#define RF_WE_LUT 0xEF
#define RF_TX_GAIN_OFFSET_8812A(_val) ((abs((_val)) << 1) | (((_val) > 0) ? BIT0 : 0))
#define RF_TX_GAIN_OFFSET_8821A(_val) ((abs((_val)) << 1) | (((_val) > 0) ? BIT0 : 0))
//
//Bit Mask
//

4
include/Hal8812PwrSeq.h
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@@ -61,7 +61,7 @@
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, 0},/* disable SW LPS 0x04[10]=0*/ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/ \
/*{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0}, disable HWPDN 0x04[15]=0*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, 0},/* disable WL suspend*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0, 0},/**/
@@ -76,7 +76,7 @@
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \
/*{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},//0x1F[7:0] = 0 turn off RF*/ \
/*{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},//0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x28}, /* 0x07[7:0] = 0x28 sps pwm mode */ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x2A}, /* 0x07[7:0] = 0x28 sps pwm mode 0x2a for BT coex*/ \
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x02, 0},/*0x8[1] = 0 ANA clk =500k */ \
/*{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0|BIT1, 0}, // 0x02[1:0] = 0 reset BB */ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \

282
include/Hal8814PhyCfg.h Normal file
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@@ -0,0 +1,282 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __INC_HAL8814PHYCFG_H__
#define __INC_HAL8814PHYCFG_H__
/*--------------------------Define Parameters-------------------------------*/
#define LOOP_LIMIT 5
#define MAX_STALL_TIME 50 //us
#define AntennaDiversityValue 0x80 //(Adapter->bSoftwareAntennaDiversity ? 0x00:0x80)
#define MAX_TXPWR_IDX_NMODE_92S 63
#define Reset_Cnt_Limit 3
#ifdef CONFIG_PCI_HCI
#define MAX_AGGR_NUM 0x0B
#else
#define MAX_AGGR_NUM 0x07
#endif // CONFIG_PCI_HCI
/*--------------------------Define Parameters-------------------------------*/
/*------------------------------Define structure----------------------------*/
/* BB/RF related */
#define SIC_ENABLE 0
/*------------------------------Define structure----------------------------*/
/*------------------------Export global variable----------------------------*/
/*------------------------Export global variable----------------------------*/
/*------------------------Export Marco Definition---------------------------*/
/*------------------------Export Marco Definition---------------------------*/
/*--------------------------Exported Function prototype---------------------*/
//1. BB register R/W API
extern u32
PHY_QueryBBReg8814A( IN PADAPTER Adapter,
IN u32 RegAddr,
IN u32 BitMask );
VOID
PHY_SetBBReg8814A( IN PADAPTER Adapter,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data );
extern u32
PHY_QueryRFReg8814A( IN PADAPTER Adapter,
IN u8 eRFPath,
IN u32 RegAddr,
IN u32 BitMask );
void
PHY_SetRFReg8814A( IN PADAPTER Adapter,
IN u8 eRFPath,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data );
//1 3. Initial BB/RF config by reading MAC/BB/RF txt.
s32
phy_BB8814A_Config_ParaFile(
IN PADAPTER Adapter
);
RT_STATUS
PHY_BBConfigMP_8814A(
IN PADAPTER Adapter
);
VOID
PHY_ConfigBB_8814A(
IN PADAPTER Adapter
);
VOID
phy_ADC_CLK_8814A(
IN PADAPTER Adapter
);
s32
PHY_RFConfig8814A(
IN PADAPTER Adapter
);
//
// RF Power setting
//
//BOOLEAN PHY_SetRFPowerState8814A(PADAPTER Adapter, rt_rf_power_state eRFPowerState);
//1 5. Tx Power setting API
VOID
PHY_GetTxPowerLevel8814(
IN PADAPTER Adapter,
OUT ps4Byte powerlevel
);
VOID
PHY_SetTxPowerLevel8814(
IN PADAPTER Adapter,
IN u8 Channel
);
u8
PHY_GetTxPowerIndex_8814A(
IN PADAPTER Adapter,
IN u8 RFPath,
IN u8 Rate,
IN CHANNEL_WIDTH BandWidth,
IN u8 Channel
);
VOID
PHY_SetTxPowerIndex_8814A(
IN PADAPTER Adapter,
IN u32 PowerIndex,
IN u8 RFPath,
IN u8 Rate
);
BOOLEAN
PHY_UpdateTxPowerDbm8814A(
IN PADAPTER Adapter,
IN s4Byte powerInDbm
);
u32
PHY_GetTxBBSwing_8814A(
IN PADAPTER Adapter,
IN BAND_TYPE Band,
IN u8 RFPath
);
//1 6. Channel setting API
VOID
PHY_SwChnlTimerCallback8814A(
IN PRT_TIMER pTimer
);
VOID
PHY_SwChnlWorkItemCallback8814A(
IN PVOID pContext
);
VOID
HAL_HandleSwChnl8814A(
IN PADAPTER pAdapter,
IN u8 channel
);
VOID
PHY_SwChnlSynchronously8814A( IN PADAPTER pAdapter,
IN u8 channel );
VOID
PHY_SwChnlAndSetBWModeCallback8814A(IN PVOID pContext);
VOID
PHY_HandleSwChnlAndSetBW8814A(
IN PADAPTER Adapter,
IN BOOLEAN bSwitchChannel,
IN BOOLEAN bSetBandWidth,
IN u8 ChannelNum,
IN CHANNEL_WIDTH ChnlWidth,
IN u8 ChnlOffsetOf40MHz,
IN u8 ChnlOffsetOf80MHz,
IN u8 CenterFrequencyIndex1
);
BOOLEAN
PHY_QueryRFPathSwitch_8814A( IN PADAPTER pAdapter);
//VOID PHY_SetMonitorMode8814A(PADAPTER pAdapter, BOOLEAN bEnableMonitorMode);
#if (USE_WORKITEM)
VOID
RtCheckForHangWorkItemCallback8814A(
IN PVOID pContext
);
#endif
BOOLEAN
SetAntennaConfig8814A(
IN PADAPTER Adapter,
IN u8 DefaultAnt
);
VOID
PHY_SetRFEReg8814A(
IN PADAPTER Adapter,
IN BOOLEAN bInit,
IN u8 Band
);
s32
PHY_SwitchWirelessBand8814A(
IN PADAPTER Adapter,
IN u8 Band
);
VOID
PHY_SetIO_8814A(
PADAPTER pAdapter
);
VOID
PHY_SetBWMode8814(
IN PADAPTER Adapter,
IN CHANNEL_WIDTH Bandwidth, // 20M or 40M
IN u8 Offset // Upper, Lower, or Don't care
);
VOID
PHY_SwChnl8814(
IN PADAPTER Adapter,
IN u8 channel
);
VOID
PHY_SetSwChnlBWMode8814(
IN PADAPTER Adapter,
IN u8 channel,
IN CHANNEL_WIDTH Bandwidth,
IN u8 Offset40,
IN u8 Offset80
);
s32 PHY_MACConfig8814(PADAPTER Adapter);
int PHY_BBConfig8814(PADAPTER Adapter);
VOID PHY_Set_SecCCATH_by_RXANT_8814A(PADAPTER pAdapter, u4Byte ulAntennaRx);
/*--------------------------Exported Function prototype---------------------*/
/*--------------------------Exported Function prototype---------------------*/
#endif // __INC_HAL8192CPHYCFG_H

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include/Hal8814PhyReg.h Normal file
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237
include/Hal8814PwrSeq.h Normal file
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@@ -0,0 +1,237 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __HAL8814PWRSEQ_H__
#define __HAL8814PWRSEQ_H__
#include "HalPwrSeqCmd.h"
/*
Check document WB-110628-DZ-RTL8195 (Jaguar) Power Architecture-R04.pdf
There are 6 HW Power States:
0: POFF--Power Off
1: PDN--Power Down
2: CARDEMU--Card Emulation
3: ACT--Active Mode
4: LPS--Low Power State
5: SUS--Suspend
The transision from different states are defined below
TRANS_CARDEMU_TO_ACT
TRANS_ACT_TO_CARDEMU
TRANS_CARDEMU_TO_SUS
TRANS_SUS_TO_CARDEMU
TRANS_CARDEMU_TO_PDN
TRANS_ACT_TO_LPS
TRANS_LPS_TO_ACT
TRANS_END
*/
#define RTL8814A_TRANS_CARDEMU_TO_ACT_STEPS 16
#define RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS 20
#define RTL8814A_TRANS_CARDEMU_TO_SUS_STEPS 17
#define RTL8814A_TRANS_SUS_TO_CARDEMU_STEPS 15
#define RTL8814A_TRANS_CARDEMU_TO_PDN_STEPS 17
#define RTL8814A_TRANS_PDN_TO_CARDEMU_STEPS 16
#define RTL8814A_TRANS_ACT_TO_LPS_STEPS 20
#define RTL8814A_TRANS_LPS_TO_ACT_STEPS 15
#define RTL8814A_TRANS_END_STEPS 1
#define RTL8814A_TRANS_CARDEMU_TO_ACT \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, 0},/* disable SW LPS 0x04[10]=0*/ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \
{0x002B, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0}, /* ??0x28[24]=1, enable pll phase select*/ \
{0x0015, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT3|BIT2|BIT1), (BIT3|BIT2|BIT1)},/* 0x14[11:9]=3'b111,OCP current threshold=1.5A */ \
{0x002D, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x0E, 0x08},/* 0x2C[11:9]=3'b100, select lpf R3 */ \
{0x002D, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x70, 0x50},/* 0x2C[14:12]=3'b101, select lpf Rs*/ \
{0x007B, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, BIT6},/* 0x78[30]=1'b1, SDM order select*/ \
/*{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0}, */ /* disable HWPDN 0x04[15]=0*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, 0},/* disable WL suspend*/ \
{0x00F0, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* */ \
{0x0081, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x30, 0x20},/* */ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0, 0},/**/
#define RTL8814A_TRANS_ACT_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0c00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xc00[7:0] = 4 turn off 3-wire */ \
{0x0e00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xe00[7:0] = 4 turn off 3-wire */ \
{0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /* 0x2[0] = 0 RESET BB, CLOSE RF */ \
{0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US}, /*Delay 1us*/ \
{0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \
{0x1002, ~PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /* 0x2[0] = 0 RESET BB, CLOSE RF */ \
{0x0002, ~PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US}, /*Delay 1us*/ \
{0x1002, ~PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \
{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*0x1F[7:0] = 0 turn off RF*/ \
/*{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},*/ /*0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x28}, /* 0x07[7:0] = 0x28 sps pwm mode 0x2a for BT coex*/ \
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x02, 0}, /*0x8[1] = 0 ANA clk =500k */ \
/*{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0|BIT1, 0},*/ /* 0x02[1:0] = 0 reset BB */ \
{0x0066, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0}, /*0x66[7]=0, disable ckreq for gpio7 output SUS */ \
{0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x41[4]=0, disable sic for gpio7 output SUS */ \
{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0}, /*0x42[1]=0, disable ckout for gpio7 output SUS */ \
{0x004e, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5}, /*0x4E[5]=1, disable LED2 for gpio7 output SUS */ \
{0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x41[0]=0, disable uart for gpio7 output SUS */ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/
#define RTL8814A_TRANS_CARDEMU_TO_SUS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0061, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x0F, 0x0c},\
{0x0061, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x0F, 0x0E},\
{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x0F, 0x07},/* gpio11 input mode, gpio10~8 output mode */ \
{0x0045, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/* gpio 0~7 output same value as input ?? */ \
{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xff},/* gpio0~7 output mode */ \
{0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/* 0x47[7:0] = 00 gpio mode */ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/* suspend option all off */ \
{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*0x14[13] = 1 turn on ZCD */ \
{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, BIT6},/* 0x14[14] =1 trun on ZCD */ \
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4},/*0x23[4] = 1 hpon LDO sleep mode */ \
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*0x8[1] = 0 ANA clk =500k */ \
{0x0091, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xA0, 0xA0}, /* 0x91[7]=1 0x91[5]=1 , disable sps,ldo sleep mode */ \
{0x0070, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, BIT3}, /* 0x70[3]=1 enable mainbias polling */ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, BIT3}, /*0x04[11] = 1 enable WL suspend */
#define RTL8814A_TRANS_SUS_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, 0}, /*0x04[11] = 0 enable WL suspend*/ \
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x10, 0},/*0x23[4] = 0 hpon LDO sleep mode leave */ \
{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, 0},/* 0x14[14] =0 trun off ZCD */ \
{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, 0},/*0x14[13] = 0 turn off ZCD */ \
{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/* gpio0~7 input mode */ \
{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/* gpio11 input mode, gpio10~8 input mode */
#define RTL8814A_TRANS_CARDEMU_TO_CARDDIS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
/**{0x0194, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, //0x194[0]=0 , disable 32K clock*/ \
/**{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x94}, //0x93=0x94 , 90[30] =0 enable 500k ANA clock .switch clock from 12M to 500K , 90 [26] =0 disable EEprom loader clock*/ \
{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, 0}, /*0x03[2] = 0, reset 3081*/ \
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x01}, /*0x80=05h if reload fw, fill the default value of host_CPU handshake field*/ \
{0x0081, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x30}, /*0x80=05h if reload fw, fill the default value of host_CPU handshake field*/ \
/*{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xF0, 0xcc},*/ \
/*{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xF0, 0xEC},*/ \
/*{0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x07},*/ /* gpio11 input mode, gpio10~8 output mode */ \
{0x0045, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/* gpio 0~7 output same value as input ?? */ \
{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xff},/* gpio0~7 output mode */ \
{0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/* 0x47[7:0] = 00 gpio mode */ \
{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, BIT6},/* 0x15[6] =1 trun on ZCD output */ \
{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*0x15[5] = 1 turn on ZCD */ \
{0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, 0},/*0x12[6] = 0 force PFM mode */ \
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4},/*0x23[4] = 1 hpon LDO sleep mode */ \
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*0x8[1] = 0 ANA clk =500k */ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07=0x20 , SOP option to disable BG/MB*/ \
{0x001f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0}, /* 0x01f[1]=0 , disable RFC_0 control REG_RF_CTRL_8814A */ \
{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0}, /* 0x020[1]=0 , disable RFC_1 control REG_RF_CTRL_8814A */ \
{0x0021, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0}, /* 0x021[1]=0 , disable RFC_2 control REG_RF_CTRL_8814A */ \
{0x0076, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0}, /* 0x076[1]=0 , disable RFC_3 control REG_OPT_CTRL_8814A +2 */ \
{0x0091, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xA0, 0xA0}, /* 0x91[7]=1 0x91[5]=1 , disable sps,ldo sleep mode */ \
{0x0070, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, BIT3}, /* 0x70[3]=1 enable mainbias polling */ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, BIT3}, /*0x04[11] = 1 enable WL suspend*/
#define RTL8814A_TRANS_CARDDIS_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, BIT6},/*0x12[6] = 1 force PWM mode */ \
{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, 0},/*0x15[5] = 0 turn off ZCD */ \
{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, 0},/* 0x15[6] =0 trun off ZCD output */ \
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0},/*0x23[4] = 0 hpon LDO leave sleep mode */ \
{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/* gpio0~7 input mode */ \
{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00}, /* gpio11 input mode, gpio10~8 input mode */ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, 0}, /*0x04[10] = 0, enable SW LPS PCIE only*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, 0}, /*0x04[11] = 0, enable WL suspend*/ \
/*{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, BIT2},*/ /*0x03[2] = 1, enable 3081*/ \
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/ \
{0x0071, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, 0},/*0x70[10] = 0, CPHY_MBIAS_EN disable*/
#define RTL8814A_TRANS_CARDEMU_TO_PDN \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
#define RTL8814A_TRANS_PDN_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
#define RTL8814A_TRANS_ACT_TO_LPS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/ \
{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x0c00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xc00[7:0] = 4 turn off 3-wire */ \
{0x0e00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xe00[7:0] = 4 turn off 3-wire */ \
{0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated,and RF closed*/ \
{0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
{0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \
{0x1002, ~PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated,and RF closed*/ \
{0x0002, ~PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
{0x1002, ~PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \
{0x05F1, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/*Respond TxOK to scheduler*/
#define RTL8814A_TRANS_LPS_TO_ACT \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/ \
{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/ \
{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /* Delay*/ \
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/ \
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT7, 0}, /* Polling 0x109[7]=0 TSF in 40M*/ \
/*{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6|BIT7, 0}, */ /*. ??0x29[7:6] = 2b'00 enable BB clock*/ \
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/ \
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/ \
{0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/ \
{0x1002, ~PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*. 0x1002[1:0] = 2b'11 enable BB macro*/ \
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
#define RTL8814A_TRANS_END \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0,PWR_CMD_END, 0, 0}, //
extern WLAN_PWR_CFG rtl8814A_power_on_flow[RTL8814A_TRANS_CARDEMU_TO_ACT_STEPS+RTL8814A_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8814A_radio_off_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8814A_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8814A_card_disable_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8814A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8814A_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8814A_card_enable_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8814A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8814A_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8814A_suspend_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8814A_TRANS_CARDEMU_TO_SUS_STEPS+RTL8814A_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8814A_resume_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8814A_TRANS_CARDEMU_TO_SUS_STEPS+RTL8814A_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8814A_hwpdn_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8814A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8814A_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8814A_enter_lps_flow[RTL8814A_TRANS_ACT_TO_LPS_STEPS+RTL8814A_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8814A_leave_lps_flow[RTL8814A_TRANS_LPS_TO_ACT_STEPS+RTL8814A_TRANS_END_STEPS];
#endif //__HAL8814PWRSEQ_H__

22
include/HalVerDef.h
View File

@@ -36,6 +36,9 @@ typedef enum tag_HAL_IC_Type_Definition
CHIP_8821 = 7,
CHIP_8723B = 8,
CHIP_8192E = 9,
CHIP_8814A = 10,
CHIP_8703B = 11,
CHIP_8188F = 12,
}HAL_IC_TYPE_E;
//HAL_CHIP_TYPE_E
@@ -109,15 +112,20 @@ typedef struct tag_HAL_VERSION
//HAL_VERSION VersionID
// HAL_IC_TYPE_E
#if 0
#define IS_81XXC(version) (((GET_CVID_IC_TYPE(version) == CHIP_8192C)||(GET_CVID_IC_TYPE(version) == CHIP_8188C))? TRUE : FALSE)
#define IS_8723_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8723A)? TRUE : FALSE)
#define IS_92D(version) ((GET_CVID_IC_TYPE(version) == CHIP_8192D)? TRUE : FALSE)
#endif
#define IS_8188E(version) ((GET_CVID_IC_TYPE(version) == CHIP_8188E)? TRUE : FALSE)
#define IS_8188F(version) ((GET_CVID_IC_TYPE(version) == CHIP_8188F) ? TRUE : FALSE)
#define IS_8192E(version) ((GET_CVID_IC_TYPE(version) == CHIP_8192E)? TRUE : FALSE)
#define IS_8812_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8812)? TRUE : FALSE)
#define IS_8821_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8821)? TRUE : FALSE)
#define IS_8814A_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8814A) ? TRUE : FALSE)
#define IS_8723B_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8723B)? TRUE : FALSE)
#define IS_8703B_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8703B)? TRUE : FALSE)
//HAL_CHIP_TYPE_E
#define IS_TEST_CHIP(version) ((GET_CVID_CHIP_TYPE(version)==TEST_CHIP)? TRUE: FALSE)
@@ -129,6 +137,7 @@ typedef struct tag_HAL_VERSION
#define IS_C_CUT(version) ((GET_CVID_CUT_VERSION(version) == C_CUT_VERSION) ? TRUE : FALSE)
#define IS_D_CUT(version) ((GET_CVID_CUT_VERSION(version) == D_CUT_VERSION) ? TRUE : FALSE)
#define IS_E_CUT(version) ((GET_CVID_CUT_VERSION(version) == E_CUT_VERSION) ? TRUE : FALSE)
#define IS_F_CUT(version) ((GET_CVID_CUT_VERSION(version) == F_CUT_VERSION) ? TRUE : FALSE)
#define IS_I_CUT(version) ((GET_CVID_CUT_VERSION(version) == I_CUT_VERSION) ? TRUE : FALSE)
#define IS_J_CUT(version) ((GET_CVID_CUT_VERSION(version) == J_CUT_VERSION) ? TRUE : FALSE)
#define IS_K_CUT(version) ((GET_CVID_CUT_VERSION(version) == K_CUT_VERSION) ? TRUE : FALSE)
@@ -142,11 +151,16 @@ typedef struct tag_HAL_VERSION
#define IS_1T1R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_1T1R)? TRUE : FALSE )
#define IS_1T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_1T2R)? TRUE : FALSE)
#define IS_2T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_2T2R)? TRUE : FALSE)
#define IS_3T3R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_3T3R)? TRUE : FALSE)
#define IS_3T4R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_3T4R)? TRUE : FALSE)
#define IS_4T4R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_4T4R)? TRUE : FALSE)
//----------------------------------------------------------------------------
//Chip version Macro. --
//----------------------------------------------------------------------------
#if 0
#define IS_81XXC_TEST_CHIP(version) ((IS_81XXC(version) && (!IS_NORMAL_CHIP(version)))? TRUE: FALSE)
#define IS_92C_SERIAL(version) ((IS_81XXC(version) && IS_2T2R(version)) ? TRUE : FALSE)
@@ -163,6 +177,7 @@ typedef struct tag_HAL_VERSION
#define IS_8723A_A_CUT(version) ((IS_8723_SERIES(version)) ? ( IS_A_CUT(version)?TRUE : FALSE) : FALSE)
#define IS_8723A_B_CUT(version) ((IS_8723_SERIES(version)) ? ( IS_B_CUT(version)?TRUE : FALSE) : FALSE)
#endif
#define IS_VENDOR_8188E_I_CUT_SERIES(_Adapter) ((IS_8188E(GET_HAL_DATA(_Adapter)->VersionID)) ? ((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->VersionID) >= I_CUT_VERSION) ? TRUE : FALSE) : FALSE)
@@ -178,5 +193,10 @@ typedef struct tag_HAL_VERSION
#define IS_VENDOR_8723B_TEST_CHIP(_Adapter) ((IS_8723B_SERIES(GET_HAL_DATA(_Adapter)->VersionID)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->VersionID)) ? FALSE : TRUE) : FALSE)
#define IS_VENDOR_8723B_MP_CHIP(_Adapter) ((IS_8723B_SERIES(GET_HAL_DATA(_Adapter)->VersionID)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->VersionID)) ? TRUE : FALSE) : FALSE)
#define IS_VENDOR_8703B_TEST_CHIP(_Adapter) ((IS_8703B_SERIES(GET_HAL_DATA(_Adapter)->VersionID)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->VersionID)) ? FALSE : TRUE) : FALSE)
#define IS_VENDOR_8703B_MP_CHIP(_Adapter) ((IS_8703B_SERIES(GET_HAL_DATA(_Adapter)->VersionID)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->VersionID)) ? TRUE : FALSE) : FALSE)
#define IS_VENDOR_8814A_TEST_CHIP(_Adapter) ((IS_8814A_SERIES(GET_HAL_DATA(_Adapter)->VersionID)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->VersionID)) ? FALSE : TRUE) : FALSE)
#define IS_VENDOR_8814A_MP_CHIP(_Adapter) ((IS_8814A_SERIES(GET_HAL_DATA(_Adapter)->VersionID)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->VersionID)) ? TRUE : FALSE) : FALSE)
#endif

115
include/autoconf.h
View File

@@ -41,7 +41,7 @@
//#define CONFIG_DEBUG_CFG80211
//#define CONFIG_DRV_ISSUE_PROV_REQ // IOT FOR S2
#define CONFIG_SET_SCAN_DENY_TIMER
/*#define SUPPLICANT_RTK_VERSION_LOWER_THAN_JB42*/ /* wpa_supplicant realtek version <= jb42 will be defined this */
#endif
/*
@@ -89,13 +89,8 @@
#define CONFIG_XMIT_THREAD_MODE
#endif
//befor link
//#define CONFIG_ANTENNA_DIVERSITY
/*#define CONFIG_ANTENNA_DIVERSITY*/
//after link
#ifdef CONFIG_ANTENNA_DIVERSITY
#define CONFIG_HW_ANTENNA_DIVERSITY
#endif
//#define CONFIG_CONCURRENT_MODE
@@ -103,7 +98,7 @@
//#define CONFIG_HWPORT_SWAP //Port0->Sec , Port1 -> Pri
#define CONFIG_RUNTIME_PORT_SWITCH
//#define DBG_RUNTIME_PORT_SWITCH
#define CONFIG_STA_MODE_SCAN_UNDER_AP_MODE
#define CONFIG_SCAN_BACKOP
//#define CONFIG_ATMEL_RC_PATCH
//#define CONFIG_TSF_RESET_OFFLOAD // For 2 PORT TSF SYNC.
#endif
@@ -115,8 +110,8 @@
#undef CONFIG_INTERRUPT_BASED_TXBCN
#endif
#ifdef CONFIG_INTERRUPT_BASED_TXBCN
//#define CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
#define CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
#define CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
/*#define CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR*/
#endif
#define CONFIG_NATIVEAP_MLME
@@ -124,41 +119,35 @@
#define CONFIG_HOSTAPD_MLME
#endif
#define CONFIG_FIND_BEST_CHANNEL
//#define CONFIG_NO_WIRELESS_HANDLERS
//#define CONFIG_AUTO_AP_MODE
#endif
#define CONFIG_P2P
#ifdef CONFIG_P2P
//The CONFIG_WFD is for supporting the Wi-Fi display
#define CONFIG_WFD
#ifndef CONFIG_WIFI_TEST
#define CONFIG_P2P_REMOVE_GROUP_INFO
#endif
#define CONFIG_P2P_REMOVE_GROUP_INFO
//#define CONFIG_DBG_P2P
#define CONFIG_P2P_PS
//#define CONFIG_P2P_IPS
#define CONFIG_P2P_OP_CHK_SOCIAL_CH
#define CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT //replace CONFIG_P2P_CHK_INVITE_CH_LIST flag
#define CONFIG_P2P_INVITE_IOT
#endif
// Added by Kurt 20110511
//#define CONFIG_TDLS
#ifdef CONFIG_TDLS
#define CONFIG_TDLS_DRIVER_SETUP
// #ifndef CONFIG_WFD
// #define CONFIG_WFD
// #define CONFIG_WFD
// #endif
// #define CONFIG_TDLS_AUTOSETUP
// #define CONFIG_TDLS_AUTOCHECKALIVE
// #define CONFIG_TDLS_AUTOSETUP
#define CONFIG_TDLS_AUTOCHECKALIVE
#define CONFIG_TDLS_CH_SW /* Enable this flag only when we confirm that TDLS CH SW is supported in FW */
#endif
//#define CONFIG_EFUSE_CONFIG_FILE
#define CONFIG_SKB_COPY //for amsdu
//#define CONFIG_LED
@@ -169,18 +158,6 @@
#endif
#endif // CONFIG_LED
//#define CONFIG_IOL
#ifdef CONFIG_IOL
#define CONFIG_IOL_NEW_GENERATION
#define CONFIG_IOL_READ_EFUSE_MAP
//#define DBG_IOL_READ_EFUSE_MAP
//#define CONFIG_IOL_LLT
//#define CONFIG_IOL_EFUSE_PATCH
//#define CONFIG_IOL_IOREG_CFG
//#define CONFIG_IOL_IOREG_CFG_DBG
#endif
#define USB_INTERFERENCE_ISSUE // this should be checked in all usb interface
#define CONFIG_GLOBAL_UI_PID
@@ -197,9 +174,8 @@
#endif
#define RTW_NOTCH_FILTER 0 /* 0:Disable, 1:Enable, */
#define CONFIG_DEAUTH_BEFORE_CONNECT
#define CONFIG_TX_MCAST2UNI 1 // Support IP multicast->unicast
#define CONFIG_TX_MCAST2UNI /*Support IP multicast->unicast*/
//#define CONFIG_CHECK_AC_LIFETIME 1 // Check packet lifetime of 4 ACs.
@@ -212,7 +188,6 @@
#define CONFIG_USB_RX_AGGREGATION
#endif
#define CONFIG_PREALLOC_RECV_SKB
//#define CONFIG_REDUCE_USB_TX_INT // Trade-off: Improve performance, but may cause TX URBs blocked by USB Host/Bus driver on few platforms.
//#define CONFIG_EASY_REPLACEMENT
@@ -222,10 +197,11 @@
//#define CONFIG_USE_USB_BUFFER_ALLOC_TX // Trade-off: For TX path, improve stability on some platforms, but may cause performance degrade on other platforms.
//#define CONFIG_USE_USB_BUFFER_ALLOC_RX // For RX path
#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX
#undef CONFIG_PREALLOC_RECV_SKB
#else
#define CONFIG_PREALLOC_RECV_SKB
#ifdef CONFIG_PREALLOC_RECV_SKB
// #define CONFIG_FIX_NR_BULKIN_BUFFER // only use USB prealloc_recv_buffer, no use alloc_skb()
//#define CONFIG_FIX_NR_BULKIN_BUFFER /* only use PREALLOC_RECV_SKB buffer, don't alloc skb at runtime */
#endif
#endif
@@ -264,8 +240,6 @@
#define ENABLE_USB_DROP_INCORRECT_OUT
//#define RTL8192CU_ADHOC_WORKAROUND_SETTING
#define DISABLE_BB_RF 0
//#define RTL8191C_FPGA_NETWORKTYPE_ADHOC 0
@@ -283,60 +257,11 @@
/*
* Platform Related Config
*/
#ifdef CONFIG_PLATFORM_MN10300
#define CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV
#define CONFIG_USE_USB_BUFFER_ALLOC_RX
#if defined (CONFIG_SW_ANTENNA_DIVERSITY)
#undef CONFIG_SW_ANTENNA_DIVERSITY
#define CONFIG_HW_ANTENNA_DIVERSITY
#endif
#if defined (CONFIG_POWER_SAVING)
#undef CONFIG_POWER_SAVING
#endif
#endif//CONFIG_PLATFORM_MN10300
/*
* Outsource Related Config
*/
#define TESTCHIP_SUPPORT 0
#define RTL8192CE_SUPPORT 0
#define RTL8192CU_SUPPORT 0
#define RTL8192C_SUPPORT (RTL8192CE_SUPPORT|RTL8192CU_SUPPORT)
#define RTL8192DE_SUPPORT 0
#define RTL8192DU_SUPPORT 0
#define RTL8192D_SUPPORT (RTL8192DE_SUPPORT|RTL8192DU_SUPPORT)
#define RTL8723AU_SUPPORT 0
#define RTL8723AS_SUPPORT 0
#define RTL8723AE_SUPPORT 0
#define RTL8723A_SUPPORT (RTL8723AU_SUPPORT|RTL8723AS_SUPPORT|RTL8723AE_SUPPORT)
#define RTL8723_FPGA_VERIFICATION 0
#define RTL8188E_SUPPORT 0
#define RTL8812A_SUPPORT 0
#define RTL8821A_SUPPORT 0
#define RTL8723B_SUPPORT 0
#define RTL8192E_SUPPORT 1
#define RTL8814A_SUPPORT 0
#define RATE_ADAPTIVE_SUPPORT 0
#define POWER_TRAINING_ACTIVE 0
#ifdef CONFIG_BT_COEXIST
// for ODM and outsrc BT-Coex
#define BT_30_SUPPORT 1
#ifndef CONFIG_LPS
#define CONFIG_LPS // download reserved page to FW
#endif
#else // !CONFIG_BT_COEXIST
#define BT_30_SUPPORT 0
#endif // !CONFIG_BT_COEXIST
@@ -353,12 +278,14 @@
#define CONFIG_80211D
#define CONFIG_RF_POWER_TRIM
/*
* Debug Related Config
*/
#define DBG 1
#define CONFIG_DEBUG /* DBG_871X, etc... */
//#define CONFIG_DEBUG /* DBG_871X, etc... */
//#define CONFIG_DEBUG_RTL871X /* RT_TRACE, RT_PRINT_DATA, _func_enter_, _func_exit_ */
#define CONFIG_PROC_DEBUG
@@ -384,6 +311,7 @@
//#define DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED "jeff-ap"
#define DBG_RX_SIGNAL_DISPLAY_RAW_DATA
//#define DBG_NOISE_MONITOR
//#define DBG_RX_COUNTER_DUMP
//#define DBG_TX_POWER_IDX
@@ -398,4 +326,5 @@
//#define CONFIG_SINGLE_XMIT_BUF
//RX use 1 urb
//#define CONFIG_SINGLE_RECV_BUF
#define DBG_RX_DFRAME_RAW_DATA

359
include/basic_types.h
View File

@@ -76,8 +76,12 @@
#ifdef PLATFORM_LINUX
#include <linux/version.h>
#include <linux/types.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/utsname.h>
#define IN
#define OUT
#define VOID void
@@ -96,6 +100,10 @@
#define UINT u32
#define ULONG u32
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 19))
typedef _Bool bool;
#endif
typedef void (*proc_t)(void*);
typedef __kernel_size_t SIZE_T;
@@ -155,194 +163,217 @@
#define SIZE_PTR SIZE_T
#define SSIZE_PTR SSIZE_T
//port from fw by thomas
// TODO: Belows are Sync from SD7-Driver. It is necessary to check correctness
/*
* Continuous bits starting from least significant bit
* Example:
* BIT_LEN_MASK_32(0) => 0x00000000
* BIT_LEN_MASK_32(1) => 0x00000001
* BIT_LEN_MASK_32(2) => 0x00000003
* BIT_LEN_MASK_32(32) => 0xFFFFFFFF
*/
#define BIT_LEN_MASK_32(__BitLen) ((u32)(0xFFFFFFFF >> (32 - (__BitLen))))
#define BIT_LEN_MASK_16(__BitLen) ((u16)(0xFFFF >> (16 - (__BitLen))))
#define BIT_LEN_MASK_8(__BitLen) ((u8)(0xFF >> (8 - (__BitLen))))
/*
* Call endian free function when
* 1. Read/write packet content.
* 2. Before write integer to IO.
* 3. After read integer from IO.
* Continuous bits starting from least significant bit
* Example:
* BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003
* BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000
*/
#define BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen) ((u32)(BIT_LEN_MASK_32(__BitLen) << (__BitOffset)))
#define BIT_OFFSET_LEN_MASK_16(__BitOffset, __BitLen) ((u16)(BIT_LEN_MASK_16(__BitLen) << (__BitOffset)))
#define BIT_OFFSET_LEN_MASK_8(__BitOffset, __BitLen) ((u8)(BIT_LEN_MASK_8(__BitLen) << (__BitOffset)))
//
// Byte Swapping routine.
//
#define EF1Byte (u8)
#define EF2Byte le16_to_cpu
#define EF4Byte le32_to_cpu
/*
* Convert LE data to host byte order
*/
#define EF1Byte (u8)
#define EF2Byte le16_to_cpu
#define EF4Byte le32_to_cpu
//
// Read LE format data from memory
//
#define ReadEF1Byte(_ptr) EF1Byte(*((u8 *)(_ptr)))
#define ReadEF2Byte(_ptr) EF2Byte(*((u16 *)(_ptr)))
#define ReadEF4Byte(_ptr) EF4Byte(*((u32 *)(_ptr)))
/*
* Read LE data from memory to host byte order
*/
#define ReadLE4Byte(_ptr) le32_to_cpu(*((u32 *)(_ptr)))
#define ReadLE2Byte(_ptr) le16_to_cpu(*((u16 *)(_ptr)))
#define ReadLE1Byte(_ptr) (*((u8 *)(_ptr)))
//
// Write LE data to memory
//
#define WriteEF1Byte(_ptr, _val) (*((u8 *)(_ptr)))=EF1Byte(_val)
#define WriteEF2Byte(_ptr, _val) (*((u16 *)(_ptr)))=EF2Byte(_val)
#define WriteEF4Byte(_ptr, _val) (*((u32 *)(_ptr)))=EF4Byte(_val)
/*
* Read BE data from memory to host byte order
*/
#define ReadBEE4Byte(_ptr) be32_to_cpu(*((u32 *)(_ptr)))
#define ReadBE2Byte(_ptr) be16_to_cpu(*((u16 *)(_ptr)))
#define ReadBE1Byte(_ptr) (*((u8 *)(_ptr)))
//
// Example:
// BIT_LEN_MASK_32(0) => 0x00000000
// BIT_LEN_MASK_32(1) => 0x00000001
// BIT_LEN_MASK_32(2) => 0x00000003
// BIT_LEN_MASK_32(32) => 0xFFFFFFFF
//
#define BIT_LEN_MASK_32(__BitLen) \
(0xFFFFFFFF >> (32 - (__BitLen)))
//
// Example:
// BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003
// BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000
//
#define BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen) \
(BIT_LEN_MASK_32(__BitLen) << (__BitOffset))
/*
* Write host byte order data to memory in LE order
*/
#define WriteLE4Byte(_ptr, _val) (*((u32 *)(_ptr))) = cpu_to_le32(_val)
#define WriteLE2Byte(_ptr, _val) (*((u16 *)(_ptr))) = cpu_to_le16(_val)
#define WriteLE1Byte(_ptr, _val) (*((u8 *)(_ptr))) = ((u8)(_val))
//
// Description:
// Return 4-byte value in host byte ordering from
// 4-byte pointer in litten-endian system.
//
#define LE_P4BYTE_TO_HOST_4BYTE(__pStart) \
(EF4Byte(*((u32 *)(__pStart))))
/*
* Write host byte order data to memory in BE order
*/
#define WriteBE4Byte(_ptr, _val) (*((u32 *)(_ptr))) = cpu_to_be32(_val)
#define WriteBE2Byte(_ptr, _val) (*((u16 *)(_ptr))) = cpu_to_be16(_val)
#define WriteBE1Byte(_ptr, _val) (*((u8 *)(_ptr))) = ((u8)(_val))
//
// Description:
// Translate subfield (continuous bits in little-endian) of 4-byte value in litten byte to
// 4-byte value in host byte ordering.
//
/*
* Return 4-byte value in host byte ordering from 4-byte pointer in litten-endian system.
*/
#define LE_P4BYTE_TO_HOST_4BYTE(__pStart) (le32_to_cpu(*((u32 *)(__pStart))))
#define LE_P2BYTE_TO_HOST_2BYTE(__pStart) (le16_to_cpu(*((u16 *)(__pStart))))
#define LE_P1BYTE_TO_HOST_1BYTE(__pStart) ((*((u8 *)(__pStart))))
/*
* Return 4-byte value in host byte ordering from 4-byte pointer in big-endian system.
*/
#define BE_P4BYTE_TO_HOST_4BYTE(__pStart) (be32_to_cpu(*((u32 *)(__pStart))))
#define BE_P2BYTE_TO_HOST_2BYTE(__pStart) (be16_to_cpu(*((u16 *)(__pStart))))
#define BE_P1BYTE_TO_HOST_1BYTE(__pStart) ((*((u8 *)(__pStart))))
/*
* Translate subfield (continuous bits in little-endian) of 4-byte value in LE byte to
* 4-byte value in host byte ordering.
*/
#define LE_BITS_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
( \
( LE_P4BYTE_TO_HOST_4BYTE(__pStart) >> (__BitOffset) ) \
& \
BIT_LEN_MASK_32(__BitLen) \
)
((LE_P4BYTE_TO_HOST_4BYTE(__pStart) >> (__BitOffset)) & BIT_LEN_MASK_32(__BitLen))
//
// Description:
// Mask subfield (continuous bits in little-endian) of 4-byte value in litten byte oredering
// and return the result in 4-byte value in host byte ordering.
//
#define LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
( \
LE_P4BYTE_TO_HOST_4BYTE(__pStart) \
& \
( ~BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen) ) \
)
//
// Description:
// Set subfield of little-endian 4-byte value to specified value.
//
#define SET_BITS_TO_LE_4BYTE(__pStart, __BitOffset, __BitLen, __Value) \
*((u32 *)(__pStart)) = \
EF4Byte( \
LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
| \
( (((u32)__Value) & BIT_LEN_MASK_32(__BitLen)) << (__BitOffset) ) \
);
#define BIT_LEN_MASK_16(__BitLen) \
(0xFFFF >> (16 - (__BitLen)))
#define BIT_OFFSET_LEN_MASK_16(__BitOffset, __BitLen) \
(BIT_LEN_MASK_16(__BitLen) << (__BitOffset))
#define LE_P2BYTE_TO_HOST_2BYTE(__pStart) \
(EF2Byte(*((u16 *)(__pStart))))
#define LE_BITS_TO_2BYTE(__pStart, __BitOffset, __BitLen) \
( \
( LE_P2BYTE_TO_HOST_2BYTE(__pStart) >> (__BitOffset) ) \
& \
BIT_LEN_MASK_16(__BitLen) \
)
#define LE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \
( \
LE_P2BYTE_TO_HOST_2BYTE(__pStart) \
& \
( ~BIT_OFFSET_LEN_MASK_16(__BitOffset, __BitLen) ) \
)
#define SET_BITS_TO_LE_2BYTE(__pStart, __BitOffset, __BitLen, __Value) \
*((u16 *)(__pStart)) = \
EF2Byte( \
LE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \
| \
( (((u16)__Value) & BIT_LEN_MASK_16(__BitLen)) << (__BitOffset) ) \
);
#define BIT_LEN_MASK_8(__BitLen) \
(0xFF >> (8 - (__BitLen)))
#define BIT_OFFSET_LEN_MASK_8(__BitOffset, __BitLen) \
(BIT_LEN_MASK_8(__BitLen) << (__BitOffset))
#define LE_P1BYTE_TO_HOST_1BYTE(__pStart) \
(EF1Byte(*((u8 *)(__pStart))))
((LE_P2BYTE_TO_HOST_2BYTE(__pStart) >> (__BitOffset)) & BIT_LEN_MASK_16(__BitLen))
#define LE_BITS_TO_1BYTE(__pStart, __BitOffset, __BitLen) \
( \
( LE_P1BYTE_TO_HOST_1BYTE(__pStart) >> (__BitOffset) ) \
& \
BIT_LEN_MASK_8(__BitLen) \
)
((LE_P1BYTE_TO_HOST_1BYTE(__pStart) >> (__BitOffset)) & BIT_LEN_MASK_8(__BitLen))
/*
* Translate subfield (continuous bits in big-endian) of 4-byte value in BE byte to
* 4-byte value in host byte ordering.
*/
#define BE_BITS_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
((BE_P4BYTE_TO_HOST_4BYTE(__pStart) >> (__BitOffset)) & BIT_LEN_MASK_32(__BitLen))
#define BE_BITS_TO_2BYTE(__pStart, __BitOffset, __BitLen) \
((BE_P2BYTE_TO_HOST_2BYTE(__pStart) >> (__BitOffset)) & BIT_LEN_MASK_16(__BitLen))
#define BE_BITS_TO_1BYTE(__pStart, __BitOffset, __BitLen) \
((BE_P1BYTE_TO_HOST_1BYTE(__pStart) >> (__BitOffset)) & BIT_LEN_MASK_8(__BitLen))
/*
* Mask subfield (continuous bits in little-endian) of 4-byte value in LE byte oredering
* and return the result in 4-byte value in host byte ordering.
*/
#define LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
(LE_P4BYTE_TO_HOST_4BYTE(__pStart) & (~BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen)))
#define LE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \
(LE_P2BYTE_TO_HOST_2BYTE(__pStart) & (~BIT_OFFSET_LEN_MASK_16(__BitOffset, __BitLen)))
#define LE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \
( \
LE_P1BYTE_TO_HOST_1BYTE(__pStart) \
& \
( ~BIT_OFFSET_LEN_MASK_8(__BitOffset, __BitLen) ) \
)
(LE_P1BYTE_TO_HOST_1BYTE(__pStart) & ((u8)(~BIT_OFFSET_LEN_MASK_8(__BitOffset, __BitLen))))
/*
* Mask subfield (continuous bits in big-endian) of 4-byte value in BE byte oredering
* and return the result in 4-byte value in host byte ordering.
*/
#define BE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
(BE_P4BYTE_TO_HOST_4BYTE(__pStart) & (~BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen)))
#define BE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \
(BE_P2BYTE_TO_HOST_2BYTE(__pStart) & (~BIT_OFFSET_LEN_MASK_16(__BitOffset, __BitLen)))
#define BE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \
(BE_P1BYTE_TO_HOST_1BYTE(__pStart) & (~BIT_OFFSET_LEN_MASK_8(__BitOffset, __BitLen)))
/*
* Set subfield of little-endian 4-byte value to specified value.
*/
#define SET_BITS_TO_LE_4BYTE(__pStart, __BitOffset, __BitLen, __Value) \
do { \
if (__BitOffset == 0 && __BitLen == 32) \
WriteLE4Byte(__pStart, __Value); \
else { \
WriteLE4Byte(__pStart, \
LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
| \
((((u32)__Value) & BIT_LEN_MASK_32(__BitLen)) << (__BitOffset)) \
); \
} \
} while (0)
#define SET_BITS_TO_LE_2BYTE(__pStart, __BitOffset, __BitLen, __Value) \
do { \
if (__BitOffset == 0 && __BitLen == 16) \
WriteLE2Byte(__pStart, __Value); \
else { \
WriteLE2Byte(__pStart, \
LE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \
| \
((((u16)__Value) & BIT_LEN_MASK_16(__BitLen)) << (__BitOffset)) \
); \
} \
} while (0)
#define SET_BITS_TO_LE_1BYTE(__pStart, __BitOffset, __BitLen, __Value) \
*((u8 *)(__pStart)) = \
EF1Byte( \
LE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \
| \
( (((u8)__Value) & BIT_LEN_MASK_8(__BitLen)) << (__BitOffset) ) \
);
do { \
if (__BitOffset == 0 && __BitLen == 8) \
WriteLE1Byte(__pStart, __Value); \
else { \
WriteLE1Byte(__pStart, \
LE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \
| \
((((u8)__Value) & BIT_LEN_MASK_8(__BitLen)) << (__BitOffset)) \
); \
} \
} while (0)
/*
* Set subfield of big-endian 4-byte value to specified value.
*/
#define SET_BITS_TO_BE_4BYTE(__pStart, __BitOffset, __BitLen, __Value) \
do { \
if (__BitOffset == 0 && __BitLen == 32) \
WriteBE4Byte(__pStart, __Value); \
else { \
WriteBE4Byte(__pStart, \
BE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
| \
((((u32)__Value) & BIT_LEN_MASK_32(__BitLen)) << (__BitOffset)) \
); \
} \
} while (0)
#define LE_BITS_CLEARED_TO_2BYTE_16BIT(__pStart, __BitOffset, __BitLen) \
( \
LE_P2BYTE_TO_HOST_2BYTE(__pStart) \
)
#define SET_BITS_TO_BE_2BYTE(__pStart, __BitOffset, __BitLen, __Value) \
do { \
if (__BitOffset == 0 && __BitLen == 16) \
WriteBE2Byte(__pStart, __Value); \
else { \
WriteBE2Byte(__pStart, \
BE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \
| \
((((u16)__Value) & BIT_LEN_MASK_16(__BitLen)) << (__BitOffset)) \
); \
} \
} while (0)
#define SET_BITS_TO_LE_2BYTE_16BIT(__pStart, __BitOffset, __BitLen, __Value) \
*((u16 *)(__pStart)) = \
EF2Byte( \
LE_BITS_CLEARED_TO_2BYTE_16BIT(__pStart, __BitOffset, __BitLen) \
| \
( (u16)__Value) \
);
#define LE_BITS_CLEARED_TO_1BYTE_8BIT(__pStart, __BitOffset, __BitLen) \
( \
LE_P1BYTE_TO_HOST_1BYTE(__pStart) \
)
#define SET_BITS_TO_LE_1BYTE_8BIT(__pStart, __BitOffset, __BitLen, __Value) \
{ \
*((u8 *)(__pStart)) = \
EF1Byte( \
LE_BITS_CLEARED_TO_1BYTE_8BIT(__pStart, __BitOffset, __BitLen) \
| \
((u8)__Value) \
); \
}
#define SET_BITS_TO_BE_1BYTE(__pStart, __BitOffset, __BitLen, __Value) \
do { \
if (__BitOffset == 0 && __BitLen == 8) \
WriteBE1Byte(__pStart, __Value); \
else { \
WriteBE1Byte(__pStart, \
BE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \
| \
((((u8)__Value) & BIT_LEN_MASK_8(__BitLen)) << (__BitOffset)) \
); \
} \
} while (0)
// Get the N-bytes aligment offset from the current length
#define N_BYTE_ALIGMENT(__Value, __Aligment) ((__Aligment == 1) ? (__Value) : (((__Value + __Aligment - 1) / __Aligment) * __Aligment))
typedef unsigned char BOOLEAN,*PBOOLEAN;
typedef unsigned char BOOLEAN, *PBOOLEAN, boolean;
#define TEST_FLAG(__Flag,__testFlag) (((__Flag) & (__testFlag)) != 0)
#define SET_FLAG(__Flag, __setFlag) ((__Flag) |= __setFlag)

4
include/cmd_osdep.h
View File

@@ -25,8 +25,8 @@ extern sint _rtw_init_cmd_priv (struct cmd_priv *pcmdpriv);
extern sint _rtw_init_evt_priv(struct evt_priv *pevtpriv);
extern void _rtw_free_evt_priv (struct evt_priv *pevtpriv);
extern void _rtw_free_cmd_priv (struct cmd_priv *pcmdpriv);
extern sint _rtw_enqueue_cmd(_queue *queue, struct cmd_obj *obj);
extern struct cmd_obj *_rtw_dequeue_cmd(_queue *queue);
extern sint _rtw_enqueue_cmd(_queue *queue, struct cmd_obj *obj, bool to_head);
extern struct cmd_obj *_rtw_dequeue_cmd(_queue *queue);
#endif

111
include/drv_conf.h
View File

@@ -20,6 +20,7 @@
#ifndef __DRV_CONF_H__
#define __DRV_CONF_H__
#include "autoconf.h"
#include "hal_ic_cfg.h"
#if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS)
@@ -75,12 +76,24 @@
#define CONFIG_USB_VENDOR_REQ_MUTEX
#endif
#if !defined(CONFIG_AP_MODE) && defined(CONFIG_DFS_MASTER)
#warning "undef CONFIG_DFS_MASTER because CONFIG_AP_MODE is not defined"
#undef CONFIG_DFS_MASTER
#endif
#define DYNAMIC_CAMID_ALLOC
#define RTW_SCAN_SPARSE_MIRACAST 1
#define RTW_SCAN_SPARSE_BG 0
#ifndef CONFIG_RTW_HIQ_FILTER
#define CONFIG_RTW_HIQ_FILTER 1
#endif
#ifndef CONFIG_RTW_FORCE_IGI_LB
#define CONFIG_RTW_FORCE_IGI_LB 0
#endif
#ifndef CONFIG_RTW_ADAPTIVITY_EN
#define CONFIG_RTW_ADAPTIVITY_EN 0
#endif
@@ -89,8 +102,60 @@
#define CONFIG_RTW_ADAPTIVITY_MODE 0
#endif
#ifndef CONFIG_RTW_NHM_EN
#define CONFIG_RTW_NHM_EN 0
#ifndef CONFIG_RTW_ADAPTIVITY_DML
#define CONFIG_RTW_ADAPTIVITY_DML 0
#endif
#ifndef CONFIG_RTW_ADAPTIVITY_DC_BACKOFF
#define CONFIG_RTW_ADAPTIVITY_DC_BACKOFF 2
#endif
#ifndef CONFIG_RTW_ADAPTIVITY_TH_L2H_INI
#define CONFIG_RTW_ADAPTIVITY_TH_L2H_INI 0
#endif
#ifndef CONFIG_RTW_ADAPTIVITY_TH_EDCCA_HL_DIFF
#define CONFIG_RTW_ADAPTIVITY_TH_EDCCA_HL_DIFF 0
#endif
#ifndef CONFIG_RTW_EXCL_CHS
#define CONFIG_RTW_EXCL_CHS {0}
#endif
#ifndef CONFIG_RTW_DFS_REGION_DOMAIN
#define CONFIG_RTW_DFS_REGION_DOMAIN 0
#endif
#ifndef CONFIG_RTW_TARGET_TX_PWR_2G_A
#define CONFIG_RTW_TARGET_TX_PWR_2G_A {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}
#endif
#ifndef CONFIG_RTW_TARGET_TX_PWR_2G_B
#define CONFIG_RTW_TARGET_TX_PWR_2G_B {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}
#endif
#ifndef CONFIG_RTW_TARGET_TX_PWR_2G_C
#define CONFIG_RTW_TARGET_TX_PWR_2G_C {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}
#endif
#ifndef CONFIG_RTW_TARGET_TX_PWR_2G_D
#define CONFIG_RTW_TARGET_TX_PWR_2G_D {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}
#endif
#ifndef CONFIG_RTW_TARGET_TX_PWR_5G_A
#define CONFIG_RTW_TARGET_TX_PWR_5G_A {-1, -1, -1, -1, -1, -1, -1, -1, -1}
#endif
#ifndef CONFIG_RTW_TARGET_TX_PWR_5G_B
#define CONFIG_RTW_TARGET_TX_PWR_5G_B {-1, -1, -1, -1, -1, -1, -1, -1, -1}
#endif
#ifndef CONFIG_RTW_TARGET_TX_PWR_5G_C
#define CONFIG_RTW_TARGET_TX_PWR_5G_C {-1, -1, -1, -1, -1, -1, -1, -1, -1}
#endif
#ifndef CONFIG_RTW_TARGET_TX_PWR_5G_D
#define CONFIG_RTW_TARGET_TX_PWR_5G_D {-1, -1, -1, -1, -1, -1, -1, -1, -1}
#endif
#ifndef CONFIG_RTW_AMPLIFIER_TYPE_2G
@@ -101,10 +166,48 @@
#define CONFIG_RTW_AMPLIFIER_TYPE_5G 0
#endif
#define MACID_NUM_SW_LIMIT 32
#define CAM_ENTRY_NUM_SW_LIMIT 32
#ifndef CONFIG_RTW_RFE_TYPE
#define CONFIG_RTW_RFE_TYPE 64
#endif
#ifndef CONFIG_RTW_GLNA_TYPE
#define CONFIG_RTW_GLNA_TYPE 0
#endif
#ifndef CONFIG_RTW_PLL_REF_CLK_SEL
#define CONFIG_RTW_PLL_REF_CLK_SEL 0x0F
#endif
#define MACID_NUM_SW_LIMIT 32
#define SEC_CAM_ENT_NUM_SW_LIMIT 32
#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A)
#define CONFIG_IEEE80211_BAND_5GHZ
#endif
#ifndef RTW_DEF_MODULE_REGULATORY_CERT
#define RTW_DEF_MODULE_REGULATORY_CERT 0
#endif
#if RTW_DEF_MODULE_REGULATORY_CERT
/* force enable TX power by rate and TX power limit */
#ifndef CONFIG_CALIBRATE_TX_POWER_BY_REGULATORY
#define CONFIG_CALIBRATE_TX_POWER_BY_REGULATORY
#endif
#endif
/*
Mark CONFIG_DEAUTH_BEFORE_CONNECT by Arvin 2015/07/20
If the failure of Wi-Fi connection is due to some irregular disconnection behavior (like unplug dongle,
power down etc.) in last time, we can unmark this flag to avoid some unpredictable response from AP.
*/
/*#define CONFIG_DEAUTH_BEFORE_CONNECT */
/*#define CONFIG_WEXT_DONT_JOIN_BYSSID */
//#include <rtl871x_byteorder.h>
/*#define CONFIG_DOSCAN_IN_BUSYTRAFFIC */
#endif // __DRV_CONF_H__

284
include/drv_types.h
View File

File diff suppressed because it is too large Load Diff

7
include/drv_types_pci.h
View File

@@ -69,13 +69,6 @@
#define HAL_HW_PCI_700F_DEVICE_ID 0x700F
#define HAL_HW_PCI_701F_DEVICE_ID 0x701F
#define HAL_HW_PCI_DLINK_DEVICE_ID 0x3304
#define HAL_HW_PCI_8192CET_DEVICE_ID 0x8191 //8192ce
#define HAL_HW_PCI_8192CE_DEVICE_ID 0x8178 //8192ce
#define HAL_HW_PCI_8191CE_DEVICE_ID 0x8177 //8192ce
#define HAL_HW_PCI_8188CE_DEVICE_ID 0x8176 //8192ce
#define HAL_HW_PCI_8192CU_DEVICE_ID 0x8191 //8192ce
#define HAL_HW_PCI_8192DE_DEVICE_ID 0x8193 //8192de
#define HAL_HW_PCI_002B_DEVICE_ID 0x002B //8192de, provided by HW SD
#define HAL_HW_PCI_8188EE_DEVICE_ID 0x8179
#define HAL_MEMORY_MAPPED_IO_RANGE_8190PCI 0x1000 //8190 support 16 pages of IO registers

6
include/gspi_hal.h
View File

@@ -22,11 +22,7 @@
void spi_int_dpc(PADAPTER padapter, u32 sdio_hisr);
void rtw_set_hal_ops(_adapter *padapter);
#ifdef CONFIG_RTL8723A
void rtl8723as_set_hal_ops(PADAPTER padapter);
#endif
u8 rtw_set_hal_ops(_adapter *padapter);
#ifdef CONFIG_RTL8188E
void rtl8188es_set_hal_ops(PADAPTER padapter);

5
include/gspi_ops.h
View File

@@ -146,11 +146,6 @@ struct spi_more_data {
unsigned long len;
};
#ifdef CONFIG_RTL8723A
void rtl8723as_set_hal_ops(PADAPTER padapter);
#define set_hal_ops rtl8723as_set_hal_ops
#endif
#ifdef CONFIG_RTL8188E
void rtl8188es_set_hal_ops(PADAPTER padapter);
#define set_hal_ops rtl8188es_set_hal_ops

10
include/hal_btcoex.h
View File

@@ -57,12 +57,15 @@ void hal_btcoex_MediaStatusNotify(PADAPTER padapter, u8 mediaStatus);
void hal_btcoex_SpecialPacketNotify(PADAPTER padapter, u8 pktType);
void hal_btcoex_IQKNotify(PADAPTER padapter, u8 state);
void hal_btcoex_BtInfoNotify(PADAPTER padapter, u8 length, u8 *tmpBuf);
void hal_btcoex_BtMpRptNotify(PADAPTER padapter, u8 length, u8 *tmpBuf);
void hal_btcoex_SuspendNotify(PADAPTER padapter, u8 state);
void hal_btcoex_HaltNotify(PADAPTER padapter);
void hal_btcoex_ScoreBoardStatusNotify(PADAPTER padapter, u8 length, u8 *tmpBuf);
void hal_btcoex_SwitchBtTRxMask(PADAPTER padapter);
void hal_btcoex_Hanlder(PADAPTER padapter);
s32 hal_btcoex_IsBTCoexRejectAMPDU(PADAPTER padapter);
s32 hal_btcoex_IsBTCoexCtrlAMPDUSize(PADAPTER padapter);
u32 hal_btcoex_GetAMPDUSize(PADAPTER padapter);
void hal_btcoex_SetManualControl(PADAPTER padapter, u8 bmanual);
@@ -78,10 +81,17 @@ void hal_btcoex_SetDBG(PADAPTER, u32 *pDbgModule);
u32 hal_btcoex_GetDBG(PADAPTER, u8 *pStrBuf, u32 bufSize);
u8 hal_btcoex_IncreaseScanDeviceNum(PADAPTER);
u8 hal_btcoex_IsBtLinkExist(PADAPTER);
void hal_btcoex_SetBtPatchVersion(PADAPTER,u16 btHciVer,u16 btPatchVer);
void hal_btcoex_SetHciVersion(PADAPTER, u16 hciVersion);
void hal_btcoex_SendScanNotify(PADAPTER, u8 type);
void hal_btcoex_StackUpdateProfileInfo(void);
void hal_btcoex_BTOffOnNotify(PADAPTER padapter, u8 bBTON);
void hal_btcoex_SetAntIsolationType(PADAPTER padapter, u8 anttype);
#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
int hal_btcoex_AntIsolationConfig_ParaFile(IN PADAPTER Adapter,IN char* pFileName);
int hal_btcoex_ParseAntIsolationConfigFile(PADAPTER Adapter, char* buffer);
#endif // CONFIG_LOAD_PHY_PARA_FROM_FILE
u16 hal_btcoex_btreg_read(PADAPTER padapter, u8 type, u16 addr, u32 *data);
u16 hal_btcoex_btreg_write(PADAPTER padapter, u8 type, u16 addr, u16 val);
#endif // !__HAL_BTCOEX_H__

328
include/hal_com.h
View File

@@ -26,6 +26,7 @@
#include "hal_phy_reg.h"
#include "hal_com_reg.h"
#include "hal_com_phycfg.h"
#include "../hal/hal_com_c2h.h"
/*------------------------------ Tx Desc definition Macro ------------------------*/
//#pragma mark -- Tx Desc related definition. --
@@ -124,54 +125,72 @@
#define DESC_RATEVHTSS4MCS9 0x53
#define HDATA_RATE(rate)\
(rate==DESC_RATE1M)?"CCK_1M":\
(rate==DESC_RATE2M)?"CCK_2M":\
(rate==DESC_RATE5_5M)?"CCK5_5M":\
(rate==DESC_RATE11M)?"CCK_11M":\
(rate==DESC_RATE6M)?"OFDM_6M":\
(rate==DESC_RATE9M)?"OFDM_9M":\
(rate==DESC_RATE12M)?"OFDM_12M":\
(rate==DESC_RATE18M)?"OFDM_18M":\
(rate==DESC_RATE24M)?"OFDM_24M":\
(rate==DESC_RATE36M)?"OFDM_36M":\
(rate==DESC_RATE48M)?"OFDM_48M":\
(rate==DESC_RATE54M)?"OFDM_54M":\
(rate==DESC_RATEMCS0)?"MCS0":\
(rate==DESC_RATEMCS1)?"MCS1":\
(rate==DESC_RATEMCS2)?"MCS2":\
(rate==DESC_RATEMCS3)?"MCS3":\
(rate==DESC_RATEMCS4)?"MCS4":\
(rate==DESC_RATEMCS5)?"MCS5":\
(rate==DESC_RATEMCS6)?"MCS6":\
(rate==DESC_RATEMCS7)?"MCS7":\
(rate==DESC_RATEMCS8)?"MCS8":\
(rate==DESC_RATEMCS9)?"MCS9":\
(rate==DESC_RATEMCS10)?"MCS10":\
(rate==DESC_RATEMCS11)?"MCS11":\
(rate==DESC_RATEMCS12)?"MCS12":\
(rate==DESC_RATEMCS13)?"MCS13":\
(rate==DESC_RATEMCS14)?"MCS14":\
(rate==DESC_RATEMCS15)?"MCS15":\
(rate==DESC_RATEVHTSS1MCS0)?"VHTSS1MCS0":\
(rate==DESC_RATEVHTSS1MCS1)?"VHTSS1MCS1":\
(rate==DESC_RATEVHTSS1MCS2)?"VHTSS1MCS2":\
(rate==DESC_RATEVHTSS1MCS3)?"VHTSS1MCS3":\
(rate==DESC_RATEVHTSS1MCS4)?"VHTSS1MCS4":\
(rate==DESC_RATEVHTSS1MCS5)?"VHTSS1MCS5":\
(rate==DESC_RATEVHTSS1MCS6)?"VHTSS1MCS6":\
(rate==DESC_RATEVHTSS1MCS7)?"VHTSS1MCS7":\
(rate==DESC_RATEVHTSS1MCS8)?"VHTSS1MCS8":\
(rate==DESC_RATEVHTSS1MCS9)?"VHTSS1MCS9":\
(rate==DESC_RATEVHTSS2MCS0)?"VHTSS2MCS0":\
(rate==DESC_RATEVHTSS2MCS1)?"VHTSS2MCS1":\
(rate==DESC_RATEVHTSS2MCS2)?"VHTSS2MCS2":\
(rate==DESC_RATEVHTSS2MCS3)?"VHTSS2MCS3":\
(rate==DESC_RATEVHTSS2MCS4)?"VHTSS2MCS4":\
(rate==DESC_RATEVHTSS2MCS5)?"VHTSS2MCS5":\
(rate==DESC_RATEVHTSS2MCS6)?"VHTSS2MCS6":\
(rate==DESC_RATEVHTSS2MCS7)?"VHTSS2MCS7":\
(rate==DESC_RATEVHTSS2MCS8)?"VHTSS2MCS8":\
(rate==DESC_RATEVHTSS2MCS9)?"VHTSS2MCS9":"UNKNOW"
(rate == DESC_RATE1M)?"CCK_1M" :\
(rate == DESC_RATE2M)?"CCK_2M" :\
(rate == DESC_RATE5_5M)?"CCK5_5M" :\
(rate == DESC_RATE11M)?"CCK_11M" :\
(rate == DESC_RATE6M)?"OFDM_6M" :\
(rate == DESC_RATE9M)?"OFDM_9M" :\
(rate == DESC_RATE12M)?"OFDM_12M" :\
(rate == DESC_RATE18M)?"OFDM_18M" :\
(rate == DESC_RATE24M)?"OFDM_24M" :\
(rate == DESC_RATE36M)?"OFDM_36M" :\
(rate == DESC_RATE48M)?"OFDM_48M" :\
(rate == DESC_RATE54M)?"OFDM_54M" :\
(rate == DESC_RATEMCS0)?"MCS0" :\
(rate == DESC_RATEMCS1)?"MCS1" :\
(rate == DESC_RATEMCS2)?"MCS2" :\
(rate == DESC_RATEMCS3)?"MCS3" :\
(rate == DESC_RATEMCS4)?"MCS4" :\
(rate == DESC_RATEMCS5)?"MCS5" :\
(rate == DESC_RATEMCS6)?"MCS6" :\
(rate == DESC_RATEMCS7)?"MCS7" :\
(rate == DESC_RATEMCS8)?"MCS8" :\
(rate == DESC_RATEMCS9)?"MCS9" :\
(rate == DESC_RATEMCS10)?"MCS10" :\
(rate == DESC_RATEMCS11)?"MCS11" :\
(rate == DESC_RATEMCS12)?"MCS12" :\
(rate == DESC_RATEMCS13)?"MCS13" :\
(rate == DESC_RATEMCS14)?"MCS14" :\
(rate == DESC_RATEMCS15)?"MCS15" :\
(rate == DESC_RATEMCS16)?"MCS16" :\
(rate == DESC_RATEMCS17)?"MCS17" :\
(rate == DESC_RATEMCS18)?"MCS18" :\
(rate == DESC_RATEMCS19)?"MCS19" :\
(rate == DESC_RATEMCS20)?"MCS20" :\
(rate == DESC_RATEMCS21)?"MCS21" :\
(rate == DESC_RATEMCS22)?"MCS22" :\
(rate == DESC_RATEMCS23)?"MCS23" :\
(rate == DESC_RATEVHTSS1MCS0)?"VHTSS1MCS0" :\
(rate == DESC_RATEVHTSS1MCS1)?"VHTSS1MCS1" :\
(rate == DESC_RATEVHTSS1MCS2)?"VHTSS1MCS2" :\
(rate == DESC_RATEVHTSS1MCS3)?"VHTSS1MCS3" :\
(rate == DESC_RATEVHTSS1MCS4)?"VHTSS1MCS4" :\
(rate == DESC_RATEVHTSS1MCS5)?"VHTSS1MCS5" :\
(rate == DESC_RATEVHTSS1MCS6)?"VHTSS1MCS6" :\
(rate == DESC_RATEVHTSS1MCS7)?"VHTSS1MCS7" :\
(rate == DESC_RATEVHTSS1MCS8)?"VHTSS1MCS8" :\
(rate == DESC_RATEVHTSS1MCS9)?"VHTSS1MCS9" :\
(rate == DESC_RATEVHTSS2MCS0)?"VHTSS2MCS0" :\
(rate == DESC_RATEVHTSS2MCS1)?"VHTSS2MCS1" :\
(rate == DESC_RATEVHTSS2MCS2)?"VHTSS2MCS2" :\
(rate == DESC_RATEVHTSS2MCS3)?"VHTSS2MCS3" :\
(rate == DESC_RATEVHTSS2MCS4)?"VHTSS2MCS4" :\
(rate == DESC_RATEVHTSS2MCS5)?"VHTSS2MCS5" :\
(rate == DESC_RATEVHTSS2MCS6)?"VHTSS2MCS6" :\
(rate == DESC_RATEVHTSS2MCS7)?"VHTSS2MCS7" :\
(rate == DESC_RATEVHTSS2MCS8)?"VHTSS2MCS8" :\
(rate == DESC_RATEVHTSS2MCS9)?"VHTSS2MCS9" :\
(rate == DESC_RATEVHTSS3MCS0)?"VHTSS3MCS0" :\
(rate == DESC_RATEVHTSS3MCS1)?"VHTSS3MCS1" :\
(rate == DESC_RATEVHTSS3MCS2)?"VHTSS3MCS2" :\
(rate == DESC_RATEVHTSS3MCS3)?"VHTSS3MCS3" :\
(rate == DESC_RATEVHTSS3MCS4)?"VHTSS3MCS4" :\
(rate == DESC_RATEVHTSS3MCS5)?"VHTSS3MCS5" :\
(rate == DESC_RATEVHTSS3MCS6)?"VHTSS3MCS6" :\
(rate == DESC_RATEVHTSS3MCS7)?"VHTSS3MCS7" :\
(rate == DESC_RATEVHTSS3MCS8)?"VHTSS3MCS8" :\
(rate == DESC_RATEVHTSS3MCS9)?"VHTSS3MCS9" : "UNKNOWN"
enum{
@@ -189,6 +208,11 @@ typedef enum _FIRMWARE_SOURCE {
FW_SOURCE_HEADER_FILE = 1, //from header file
} FIRMWARE_SOURCE, *PFIRMWARE_SOURCE;
typedef enum _CH_SW_USE_CASE {
CH_SW_USE_CASE_TDLS = 0,
CH_SW_USE_CASE_MCC = 1
} CH_SW_USE_CASE;
//
// Queue Select Value in TxDesc
//
@@ -214,21 +238,84 @@ typedef enum _FIRMWARE_SOURCE {
#define PageNum_512(_Len) (u32)(((_Len)>>9) + ((_Len)&0x1FF ? 1:0))
#define PageNum(_Len, _Size) (u32)(((_Len)/(_Size)) + ((_Len)&((_Size) - 1) ? 1:0))
struct dbg_rx_counter
{
u32 rx_pkt_ok;
u32 rx_pkt_crc_error;
u32 rx_pkt_drop;
u32 rx_ofdm_fa;
u32 rx_cck_fa;
u32 rx_ht_fa;
};
void rtw_dump_mac_rx_counters(_adapter* padapter,struct dbg_rx_counter *rx_counter);
void rtw_dump_phy_rx_counters(_adapter* padapter,struct dbg_rx_counter *rx_counter);
void rtw_reset_mac_rx_counters(_adapter* padapter);
void rtw_reset_phy_rx_counters(_adapter* padapter);
void rtw_reset_phy_trx_ok_counters(_adapter *padapter);
u8 rtw_hal_data_init(_adapter *padapter);
void rtw_hal_data_deinit(_adapter *padapter);
#ifdef DBG_RX_COUNTER_DUMP
#define DUMP_DRV_RX_COUNTER BIT0
#define DUMP_MAC_RX_COUNTER BIT1
#define DUMP_PHY_RX_COUNTER BIT2
#define DUMP_DRV_TRX_COUNTER_DATA BIT3
void rtw_dump_phy_rxcnts_preprocess(_adapter* padapter,u8 rx_cnt_mode);
void rtw_dump_rx_counters(_adapter* padapter);
#endif
void dump_chip_info(HAL_VERSION ChipVersion);
void rtw_hal_config_rftype(PADAPTER padapter);
u8 //return the final channel plan decision
hal_com_config_channel_plan(
IN PADAPTER padapter,
IN u8 hw_channel_plan, //channel plan from HW (efuse/eeprom)
IN u8 sw_channel_plan, //channel plan from SW (registry/module param)
IN u8 def_channel_plan, //channel plan used when the former two is invalid
IN BOOLEAN AutoLoadFail
#define BAND_CAP_2G BIT0
#define BAND_CAP_5G BIT1
#define BAND_CAP_BIT_NUM 2
#define BW_CAP_5M BIT0
#define BW_CAP_10M BIT1
#define BW_CAP_20M BIT2
#define BW_CAP_40M BIT3
#define BW_CAP_80M BIT4
#define BW_CAP_160M BIT5
#define BW_CAP_80_80M BIT6
#define BW_CAP_BIT_NUM 7
#define PROTO_CAP_11B BIT0
#define PROTO_CAP_11G BIT1
#define PROTO_CAP_11N BIT2
#define PROTO_CAP_11AC BIT3
#define PROTO_CAP_BIT_NUM 4
#define WL_FUNC_P2P BIT0
#define WL_FUNC_MIRACAST BIT1
#define WL_FUNC_TDLS BIT2
#define WL_FUNC_FTM BIT3
#define WL_FUNC_BIT_NUM 4
int hal_spec_init(_adapter *adapter);
void dump_hal_spec(void *sel, _adapter *adapter);
bool hal_chk_band_cap(_adapter *adapter, u8 cap);
bool hal_chk_bw_cap(_adapter *adapter, u8 cap);
bool hal_chk_proto_cap(_adapter *adapter, u8 cap);
bool hal_is_band_support(_adapter *adapter, u8 band);
bool hal_is_bw_support(_adapter *adapter, u8 bw);
bool hal_is_wireless_mode_support(_adapter *adapter, u8 mode);
u8 hal_largest_bw(_adapter *adapter, u8 in_bw);
bool hal_chk_wl_func(_adapter *adapter, u8 func);
u8 hal_com_config_channel_plan(
IN PADAPTER padapter,
IN char *hw_alpha2,
IN u8 hw_chplan,
IN char *sw_alpha2,
IN u8 sw_chplan,
IN u8 def_chplan,
IN BOOLEAN AutoLoadFail
);
int hal_config_macaddr(_adapter *adapter, bool autoload_fail);
BOOLEAN
HAL_IsLegalChannel(
IN PADAPTER Adapter,
@@ -262,6 +349,13 @@ u8 rtw_hal_networktype_to_raid(_adapter *adapter, struct sta_info *psta);
u8 rtw_get_mgntframe_raid(_adapter *adapter,unsigned char network_type);
void rtw_hal_update_sta_rate_mask(PADAPTER padapter, struct sta_info *psta);
/* access HW only */
u32 rtw_sec_read_cam(_adapter *adapter, u8 addr);
void rtw_sec_write_cam(_adapter *adapter, u8 addr, u32 wdata);
void rtw_sec_read_cam_ent(_adapter *adapter, u8 id, u8 *ctrl, u8 *mac, u8 *key);
void rtw_sec_write_cam_ent(_adapter *adapter, u8 id, u16 ctrl, u8 *mac, u8 *key);
bool rtw_sec_read_cam_is_gk(_adapter *adapter, u8 id);
void hw_var_port_switch(_adapter *adapter);
void SetHwReg(PADAPTER padapter, u8 variable, u8 *val);
@@ -278,11 +372,6 @@ eqNByte(
u32 num
);
BOOLEAN
IsHexDigit(
IN char chTmp
);
u32
MapCharToHexDigit(
IN char chTmp
@@ -332,23 +421,27 @@ isAllSpaceOrTab(
void linked_info_dump(_adapter *padapter,u8 benable);
#ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA
void rtw_get_raw_rssi_info(void *sel, _adapter *padapter);
void rtw_store_phy_info(_adapter *padapter, union recv_frame *prframe);
void rtw_dump_raw_rssi_info(_adapter *padapter);
void rtw_dump_raw_rssi_info(_adapter *padapter, void *sel);
#endif
#ifdef DBG_RX_DFRAME_RAW_DATA
void rtw_dump_rx_dframe_info(_adapter *padapter, void *sel);
#endif
void rtw_store_phy_info(_adapter *padapter, union recv_frame *prframe);
#define HWSET_MAX_SIZE 512
#ifdef CONFIG_EFUSE_CONFIG_FILE
#define EFUSE_FILE_COLUMN_NUM 16
u32 Hal_readPGDataFromConfigFile(PADAPTER padapter, struct file *fp);
void Hal_ReadMACAddrFromFile(PADAPTER padapter, struct file *fp);
void Hal_GetPhyEfuseMACAddr(PADAPTER padapter, u8* mac_addr);
int check_phy_efuse_tx_power_info_valid(PADAPTER padapter);
int check_phy_efuse_macaddr_info_valid(PADAPTER padapter);
#endif //CONFIG_EFUSE_CONFIG_FILE
u32 Hal_readPGDataFromConfigFile(PADAPTER padapter);
u32 Hal_ReadMACAddrFromFile(PADAPTER padapter, u8 *mac_addr);
#endif /* CONFIG_EFUSE_CONFIG_FILE */
#ifdef CONFIG_RF_GAIN_OFFSET
int check_phy_efuse_tx_power_info_valid(PADAPTER padapter);
int hal_efuse_macaddr_offset(_adapter *adapter);
int Hal_GetPhyEfuseMACAddr(PADAPTER padapter, u8 *mac_addr);
#ifdef CONFIG_RF_POWER_TRIM
void rtw_bb_rf_gain_offset(_adapter *padapter);
#endif //CONFIG_RF_GAIN_OFFSET
#endif /*CONFIG_RF_POWER_TRIM*/
void dm_DynamicUsbTxAgg(_adapter *padapter, u8 from_timer);
u8 rtw_hal_busagg_qsel_check(_adapter *padapter,u8 pre_qsel,u8 next_qsel);
@@ -372,18 +465,101 @@ struct noise_info
u8 chan;
};
#endif
void rtw_get_noise(_adapter* padapter);
u8 rtw_get_current_tx_rate(_adapter *padapter, u8 macid);
u8 rtw_get_current_tx_sgi(_adapter *padapter, u8 macid);
void rtw_hal_set_fw_rsvd_page(_adapter* adapter, bool finished);
#ifdef CONFIG_TDLS
#ifdef CONFIG_TDLS_CH_SW
s32 rtw_hal_ch_sw_oper_offload(_adapter *padapter, u8 channel, u8 channel_offset, u16 bwmode);
#endif
#endif
#ifdef CONFIG_GPIO_API
u8 rtw_hal_get_gpio(_adapter* adapter, u8 gpio_num);
int rtw_hal_set_gpio_output_value(_adapter* adapter, u8 gpio_num, BOOLEAN isHigh);
int rtw_hal_config_gpio(_adapter* adapter, u8 gpio_num, BOOLEAN isOutput);
int rtw_hal_set_gpio_output_value(_adapter* adapter, u8 gpio_num, bool isHigh);
int rtw_hal_config_gpio(_adapter* adapter, u8 gpio_num, bool isOutput);
int rtw_hal_register_gpio_interrupt(_adapter* adapter, int gpio_num, void(*callback)(u8 level));
int rtw_hal_disable_gpio_interrupt(_adapter* adapter, int gpio_num);
#endif
s8 rtw_hal_ch_sw_iqk_info_search(_adapter *padapter, u8 central_chnl, u8 bw_mode);
void rtw_hal_ch_sw_iqk_info_backup(_adapter *adapter);
void rtw_hal_ch_sw_iqk_info_restore(_adapter *padapter, u8 ch_sw_use_case);
#ifdef CONFIG_GPIO_WAKEUP
void rtw_hal_switch_gpio_wl_ctrl(_adapter *padapter, u8 index, u8 enable);
void rtw_hal_set_output_gpio(_adapter *padapter, u8 index, u8 outputval);
#endif
typedef enum _HAL_PHYDM_OPS {
HAL_PHYDM_DIS_ALL_FUNC,
HAL_PHYDM_FUNC_SET,
HAL_PHYDM_FUNC_CLR,
HAL_PHYDM_ABILITY_BK,
HAL_PHYDM_ABILITY_RESTORE,
HAL_PHYDM_ABILITY_SET,
HAL_PHYDM_ABILITY_GET,
} HAL_PHYDM_OPS;
#define DYNAMIC_FUNC_DISABLE (0x0)
u32 rtw_phydm_ability_ops(_adapter *adapter, HAL_PHYDM_OPS ops, u32 ability);
#define rtw_phydm_func_disable_all(adapter) \
rtw_phydm_ability_ops(adapter, HAL_PHYDM_DIS_ALL_FUNC, 0)
#define rtw_phydm_func_for_offchannel(adapter) \
do { \
rtw_phydm_ability_ops(adapter, HAL_PHYDM_DIS_ALL_FUNC, 0); \
if (rtw_odm_adaptivity_needed(adapter)) \
rtw_phydm_ability_ops(adapter, HAL_PHYDM_FUNC_SET, ODM_BB_ADAPTIVITY); \
} while (0)
#define rtw_phydm_func_set(adapter, ability) \
rtw_phydm_ability_ops(adapter, HAL_PHYDM_FUNC_SET, ability)
#define rtw_phydm_func_clr(adapter, ability) \
rtw_phydm_ability_ops(adapter, HAL_PHYDM_FUNC_CLR, ability)
#define rtw_phydm_ability_backup(adapter) \
rtw_phydm_ability_ops(adapter, HAL_PHYDM_ABILITY_BK, 0)
#define rtw_phydm_ability_restore(adapter) \
rtw_phydm_ability_ops(adapter, HAL_PHYDM_ABILITY_RESTORE, 0)
#define rtw_phydm_ability_set(adapter, ability) \
rtw_phydm_ability_ops(adapter, HAL_PHYDM_ABILITY_SET, ability)
static inline u32 rtw_phydm_ability_get(_adapter *adapter)
{
return rtw_phydm_ability_ops(adapter, HAL_PHYDM_ABILITY_GET, 0);
}
#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
extern char *rtw_phy_file_path;
extern char file_path[PATH_LENGTH_MAX];
#define GetLineFromBuffer(buffer) strsep(&buffer, "\n")
extern char rtw_phy_para_file_path[PATH_LENGTH_MAX];
#define GetLineFromBuffer(buffer) strsep(&buffer, "\r\n")
#endif
#ifdef CONFIG_FW_C2H_DEBUG
void Debug_FwC2H(PADAPTER padapter, u8 *pdata, u8 len);
#endif
/*CONFIG_FW_C2H_DEBUG*/
void update_IOT_info(_adapter *padapter);
#ifdef CONFIG_AUTO_CHNL_SEL_NHM
void rtw_acs_start(_adapter *padapter, bool bStart);
#endif
void hal_set_crystal_cap(_adapter *adapter, u8 crystal_cap);
#ifdef CONFIG_ANTENNA_DIVERSITY
u8 rtw_hal_antdiv_before_linked(_adapter *padapter);
void rtw_hal_antdiv_rssi_compared(_adapter *padapter, WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src);
#endif
#endif //__HAL_COMMON_H__

170
include/hal_com_h2c.h
View File

@@ -38,6 +38,7 @@ enum h2c_cmd{
H2C_FCS_RSVDPAGE = 0x10,
H2C_FCS_INFO = 0x11,
H2C_AP_WOW_GPIO_CTRL = 0x13,
H2C_CHNL_SWITCH_OPER_OFFLOAD = 0x1C,
//PoweSave Class: 001
H2C_SET_PWR_MODE = 0x20,
@@ -51,11 +52,18 @@ enum h2c_cmd{
H2C_FWLPS_IN_IPS_ = 0x28,
//Dynamic Mechanism Class: 010
H2C_MACID_CFG = 0x40,
H2C_MACID_CFG = 0x40,
H2C_TXBF = 0x41,
H2C_RSSI_SETTING = 0x42,
H2C_AP_REQ_TXRPT = 0x43,
H2C_INIT_RATE_COLLECT = 0x44,
H2C_IQ_CALIBRATION = 0x45,
H2C_RA_MASK_3SS = 0x46,/* for 8814A */
H2C_RA_PARA_ADJUST = 0x47,/* CONFIG_RA_DBG_CMD */
H2C_DYNAMIC_TX_PATH = 0x48,/* for 8814A */
H2C_FW_TRACE_EN = 0x49,
//BT Class: 011
H2C_B_TYPE_TDMA = 0x60,
@@ -80,11 +88,15 @@ enum h2c_cmd{
H2C_D0_SCAN_OFFLOAD_INFO = 0x86,
H2C_CHNL_SWITCH_OFFLOAD = 0x87,
H2C_AOAC_RSVDPAGE3 = 0x88,
H2C_P2P_OFFLOAD_RSVD_PAGE = 0x8A,
H2C_P2P_OFFLOAD = 0x8B,
H2C_RESET_TSF = 0xC0,
H2C_BCNHWSEQ = 0xC5,
H2C_MAXID,
};
#define H2C_INACTIVE_PS_LEN 3
#define H2C_RSVDPAGE_LOC_LEN 5
#define H2C_MEDIA_STATUS_RPT_LEN 3
#define H2C_KEEP_ALIVE_CTRL_LEN 2
@@ -95,7 +107,7 @@ enum h2c_cmd{
#define H2C_PWRMODE_LEN 7
#define H2C_PSTUNEPARAM_LEN 4
#define H2C_MACID_CFG_LEN 7
#define H2C_BTMP_OPER_LEN 4
#define H2C_BTMP_OPER_LEN 5
#define H2C_WOWLAN_LEN 5
#define H2C_REMOTE_WAKE_CTRL_LEN 3
#define H2C_AOAC_GLOBAL_INFO_LEN 2
@@ -107,30 +119,31 @@ enum h2c_cmd{
#define H2C_FORCE_BT_TXPWR_LEN 3
#define H2C_BCN_RSVDPAGE_LEN 5
#define H2C_PROBERSP_RSVDPAGE_LEN 5
#define H2C_P2PRSVDPAGE_LOC_LEN 5
#define H2C_P2P_OFFLOAD_LEN 3
#ifdef CONFIG_WOWLAN
#define eqMacAddr(a,b) ( ((a)[0]==(b)[0] && (a)[1]==(b)[1] && (a)[2]==(b)[2] && (a)[3]==(b)[3] && (a)[4]==(b)[4] && (a)[5]==(b)[5]) ? 1:0 )
#define cpMacAddr(des,src) ((des)[0]=(src)[0],(des)[1]=(src)[1],(des)[2]=(src)[2],(des)[3]=(src)[3],(des)[4]=(src)[4],(des)[5]=(src)[5])
#define cpIpAddr(des,src) ((des)[0]=(src)[0],(des)[1]=(src)[1],(des)[2]=(src)[2],(des)[3]=(src)[3])
#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
//
// ARP packet
//
// LLC Header
#define GET_ARP_PKT_LLC_TYPE(__pHeader) ReadEF2Byte( ((u8*)(__pHeader)) + 6)
#define GET_ARP_PKT_LLC_TYPE(__pHeader) ReadLE2Byte(((u8 *)(__pHeader)) + 6)
//ARP element
#define GET_ARP_PKT_OPERATION(__pHeader) ReadEF2Byte(((u8*)(__pHeader)) + 6)
#define GET_ARP_PKT_OPERATION(__pHeader) ReadLE2Byte(((u8 *)(__pHeader)) + 6)
#define GET_ARP_PKT_SENDER_MAC_ADDR(__pHeader, _val) cpMacAddr((u8*)(_val), ((u8*)(__pHeader))+8)
#define GET_ARP_PKT_SENDER_IP_ADDR(__pHeader, _val) cpIpAddr((u8*)(_val), ((u8*)(__pHeader))+14)
#define GET_ARP_PKT_TARGET_MAC_ADDR(__pHeader, _val) cpMacAddr((u8*)(_val), ((u8*)(__pHeader))+18)
#define GET_ARP_PKT_TARGET_IP_ADDR(__pHeader, _val) cpIpAddr((u8*)(_val), ((u8*)(__pHeader))+24)
#define SET_ARP_PKT_HW(__pHeader, __Value) WriteEF2Byte( ((u8*)(__pHeader)) + 0, __Value)
#define SET_ARP_PKT_PROTOCOL(__pHeader, __Value) WriteEF2Byte( ((u8*)(__pHeader)) + 2, __Value)
#define SET_ARP_PKT_HW_ADDR_LEN(__pHeader, __Value) WriteEF1Byte( ((u8*)(__pHeader)) + 4, __Value)
#define SET_ARP_PKT_PROTOCOL_ADDR_LEN(__pHeader, __Value) WriteEF1Byte( ((u8*)(__pHeader)) + 5, __Value)
#define SET_ARP_PKT_OPERATION(__pHeader, __Value) WriteEF2Byte( ((u8*)(__pHeader)) + 6, __Value)
#define SET_ARP_PKT_HW(__pHeader, __Value) WriteLE2Byte(((u8 *)(__pHeader)) + 0, __Value)
#define SET_ARP_PKT_PROTOCOL(__pHeader, __Value) WriteLE2Byte(((u8 *)(__pHeader)) + 2, __Value)
#define SET_ARP_PKT_HW_ADDR_LEN(__pHeader, __Value) WriteLE1Byte(((u8 *)(__pHeader)) + 4, __Value)
#define SET_ARP_PKT_PROTOCOL_ADDR_LEN(__pHeader, __Value) WriteLE1Byte(((u8 *)(__pHeader)) + 5, __Value)
#define SET_ARP_PKT_OPERATION(__pHeader, __Value) WriteLE2Byte(((u8 *)(__pHeader)) + 6, __Value)
#define SET_ARP_PKT_SENDER_MAC_ADDR(__pHeader, _val) cpMacAddr(((u8*)(__pHeader))+8, (u8*)(_val))
#define SET_ARP_PKT_SENDER_IP_ADDR(__pHeader, _val) cpIpAddr(((u8*)(__pHeader))+14, (u8*)(_val))
#define SET_ARP_PKT_TARGET_MAC_ADDR(__pHeader, _val) cpMacAddr(((u8*)(__pHeader))+18, (u8*)(_val))
@@ -163,51 +176,79 @@ enum h2c_cmd{
#endif //CONFIG_WOWLAN
//_RSVDPAGE_LOC_CMD_0x00
#define SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT(__pH2CCmd, 0, 8, __Value)
#define SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+1, 0, 8, __Value)
#define SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+2, 0, 8, __Value)
#define SET_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+3, 0, 8, __Value)
#define SET_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value)SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+4, 0, 8, __Value)
#define SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
#define SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
#define SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
#define SET_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
#define SET_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value)SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
//_MEDIA_STATUS_RPT_PARM_CMD_0x01
#define SET_H2CCMD_MSRRPT_PARM_OPMODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
#define SET_H2CCMD_MSRRPT_PARM_MACID_IND(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
#define SET_H2CCMD_MSRRPT_PARM_MACID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT(__pH2CCmd+1, 0, 8, __Value)
#define SET_H2CCMD_MSRRPT_PARM_MACID_END(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT(__pH2CCmd+2, 0, 8, __Value)
#define SET_H2CCMD_MSRRPT_PARM_OPMODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 0, 1, (__Value))
#define SET_H2CCMD_MSRRPT_PARM_MACID_IND(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 1, 1, (__Value))
#define SET_H2CCMD_MSRRPT_PARM_MIRACAST(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 2, 1, (__Value))
#define SET_H2CCMD_MSRRPT_PARM_MIRACAST_SINK(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 3, 1, (__Value))
#define SET_H2CCMD_MSRRPT_PARM_ROLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 4, 4, (__Value))
#define SET_H2CCMD_MSRRPT_PARM_MACID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)) + 1, 0, 8, (__Value))
#define SET_H2CCMD_MSRRPT_PARM_MACID_END(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)) + 2, 0, 8, (__Value))
#define GET_H2CCMD_MSRRPT_PARM_OPMODE(__pH2CCmd) LE_BITS_TO_1BYTE(((u8 *)(__pH2CCmd)), 0, 1)
#define GET_H2CCMD_MSRRPT_PARM_MIRACAST(__pH2CCmd) LE_BITS_TO_1BYTE(((u8 *)(__pH2CCmd)), 2, 1)
#define GET_H2CCMD_MSRRPT_PARM_MIRACAST_SINK(__pH2CCmd) LE_BITS_TO_1BYTE(((u8 *)(__pH2CCmd)), 3, 1)
#define GET_H2CCMD_MSRRPT_PARM_ROLE(__pH2CCmd) LE_BITS_TO_1BYTE(((u8 *)(__pH2CCmd)), 4, 4)
#define H2C_MSR_ROLE_RSVD 0
#define H2C_MSR_ROLE_STA 1
#define H2C_MSR_ROLE_AP 2
#define H2C_MSR_ROLE_GC 3
#define H2C_MSR_ROLE_GO 4
#define H2C_MSR_ROLE_TDLS 5
#define H2C_MSR_ROLE_ADHOC 6
#define H2C_MSR_ROLE_MAX 7
extern const char * const _h2c_msr_role_str[];
#define h2c_msr_role_str(role) (((role) >= H2C_MSR_ROLE_MAX) ? _h2c_msr_role_str[H2C_MSR_ROLE_MAX] : _h2c_msr_role_str[(role)])
#define H2C_MSR_FMT "%s %s%s"
#define H2C_MSR_ARG(h2c_msr) \
GET_H2CCMD_MSRRPT_PARM_OPMODE((h2c_msr)) ? " C" : "", \
h2c_msr_role_str(GET_H2CCMD_MSRRPT_PARM_ROLE((h2c_msr))), \
GET_H2CCMD_MSRRPT_PARM_MIRACAST((h2c_msr)) ? (GET_H2CCMD_MSRRPT_PARM_MIRACAST_SINK((h2c_msr)) ? " MSINK" : " MSRC") : ""
s32 rtw_hal_set_FwMediaStatusRpt_cmd(_adapter *adapter, bool opmode, bool miracast, bool miracast_sink, u8 role, u8 macid, bool macid_ind, u8 macid_end);
s32 rtw_hal_set_FwMediaStatusRpt_single_cmd(_adapter *adapter, bool opmode, bool miracast, bool miracast_sink, u8 role, u8 macid);
s32 rtw_hal_set_FwMediaStatusRpt_range_cmd(_adapter *adapter, bool opmode, bool miracast, bool miracast_sink, u8 role, u8 macid, u8 macid_end);
//_KEEP_ALIVE_CMD_0x03
#define SET_H2CCMD_KEEPALIVE_PARM_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
#define SET_H2CCMD_KEEPALIVE_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
#define SET_H2CCMD_KEEPALIVE_PARM_PKT_TYPE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
#define SET_H2CCMD_KEEPALIVE_PARM_CHECK_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT(__pH2CCmd+1, 0, 8, __Value)
#define SET_H2CCMD_KEEPALIVE_PARM_CHECK_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
//_DISCONNECT_DECISION_CMD_0x04
#define SET_H2CCMD_DISCONDECISION_PARM_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
#define SET_H2CCMD_DISCONDECISION_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
#define SET_H2CCMD_DISCONDECISION_PARM_CHECK_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT(__pH2CCmd+1, 0, 8, __Value)
#define SET_H2CCMD_DISCONDECISION_PARM_TRY_PKT_NUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT(__pH2CCmd+2, 0, 8, __Value)
#define SET_H2CCMD_DISCONDECISION_PARM_CHECK_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
#define SET_H2CCMD_DISCONDECISION_PARM_TRY_PKT_NUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
#ifdef CONFIG_AP_WOWLAN
//_AP_Offload 0x08
#define SET_H2CCMD_AP_WOWLAN_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT(__pH2CCmd, 0, 8, __Value)
#define SET_H2CCMD_AP_WOWLAN_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
//_BCN_RsvdPage 0x09
#define SET_H2CCMD_AP_WOWLAN_RSVDPAGE_LOC_BCN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT(__pH2CCmd, 0, 8, __Value)
#define SET_H2CCMD_AP_WOWLAN_RSVDPAGE_LOC_BCN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
//_Probersp_RsvdPage 0x0a
#define SET_H2CCMD_AP_WOWLAN_RSVDPAGE_LOC_ProbeRsp(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT(__pH2CCmd, 0, 8, __Value)
#define SET_H2CCMD_AP_WOWLAN_RSVDPAGE_LOC_ProbeRsp(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
//_Probersp_RsvdPage 0x13
#define SET_H2CCMD_AP_WOW_GPIO_CTRL_INDEX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)
#define SET_H2CCMD_AP_WOW_GPIO_CTRL_C2H_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value)
#define SET_H2CCMD_AP_WOW_GPIO_CTRL_PLUS(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value)
#define SET_H2CCMD_AP_WOW_GPIO_CTRL_HIGH_ACTIVE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 6, 1, __Value)
#define SET_H2CCMD_AP_WOW_GPIO_CTRL_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 7, 1, __Value)
#define SET_H2CCMD_AP_WOW_GPIO_CTRL_DURATION(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+1, 0, 8, __Value)
#define SET_H2CCMD_AP_WOW_GPIO_CTRL_C2H_DURATION(__pH2CCmd, __Value)SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+2, 0, 8, __Value)
#define SET_H2CCMD_AP_WOW_GPIO_CTRL_DURATION(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
#define SET_H2CCMD_AP_WOW_GPIO_CTRL_C2H_DURATION(__pH2CCmd, __Value)SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
//_AP_PS 0x26
#define SET_H2CCMD_AP_WOW_PS_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
#define SET_H2CCMD_AP_WOW_PS_32K_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
#define SET_H2CCMD_AP_WOW_PS_RF(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
#define SET_H2CCMD_AP_WOW_PS_DURATION(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+1, 0, 8, __Value)
#endif
#define SET_H2CCMD_AP_WOW_PS_DURATION(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
// _WoWLAN PARAM_CMD_0x80
#define SET_H2CCMD_WOWLAN_FUNC_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
@@ -220,11 +261,11 @@ enum h2c_cmd{
#define SET_H2CCMD_WOWLAN_DISCONNECT_WAKE_UP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 7, 1, __Value)
#define SET_H2CCMD_WOWLAN_GPIONUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 7, __Value)
#define SET_H2CCMD_WOWLAN_DATAPIN_WAKE_UP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 7, 1, __Value)
#define SET_H2CCMD_WOWLAN_GPIO_DURATION(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+2, 0, 8, __Value)
#define SET_H2CCMD_WOWLAN_GPIO_DURATION(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
#define SET_H2CCMD_WOWLAN_GPIO_PULSE_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 1, __Value)
#define SET_H2CCMD_WOWLAN_GPIO_PULSE_COUNT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+3, 1, 7, __Value)
#define SET_H2CCMD_WOWLAN_LOWPR_RX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+4, 0, 1, __Value)
#define SET_H2CCMD_WOWLAN_GPIO_PULSE_COUNT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 1, 7, __Value)
#define SET_H2CCMD_WOWLAN_LOWPR_RX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 1, __Value)
#define SET_H2CCMD_WOWLAN_CHANGE_UNIT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 2, 1, __Value)
// _REMOTE_WAKEUP_CMD_0x81
#define SET_H2CCMD_REMOTE_WAKECTRL_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
#define SET_H2CCMD_REMOTE_WAKE_CTRL_ARP_OFFLOAD_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
@@ -232,33 +273,46 @@ enum h2c_cmd{
#define SET_H2CCMD_REMOTE_WAKE_CTRL_GTK_OFFLOAD_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)
#define SET_H2CCMD_REMOTE_WAKE_CTRL_NLO_OFFLOAD_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value)
#define SET_H2CCMD_REMOTE_WAKE_CTRL_FW_UNICAST_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 7, 1, __Value)
#define SET_H2CCMD_REMOTE_WAKE_CTRL_P2P_OFFLAD_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 1, __Value)
#define SET_H2CCMD_REMOTE_WAKE_CTRL_NBNS_FILTER_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 2, 1, __Value)
#define SET_H2CCMD_REMOTE_WAKE_CTRL_ARP_ACTION(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 1, __Value)
#define SET_H2CCMD_REMOTE_WAKE_CTRL_FW_PARSING_UNTIL_WAKEUP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 4, 1, __Value)
// AOAC_GLOBAL_INFO_0x82
#define SET_H2CCMD_AOAC_GLOBAL_INFO_PAIRWISE_ENC_ALG(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT(__pH2CCmd, 0, 8, __Value)
#define SET_H2CCMD_AOAC_GLOBAL_INFO_GROUP_ENC_ALG(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+1, 0, 8, __Value)
#define SET_H2CCMD_AOAC_GLOBAL_INFO_PAIRWISE_ENC_ALG(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
#define SET_H2CCMD_AOAC_GLOBAL_INFO_GROUP_ENC_ALG(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
// AOAC_RSVDPAGE_LOC_0x83
#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_REMOTE_WAKE_CTRL_INFO(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd), 0, 8, __Value)
#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_ARP_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+1, 0, 8, __Value)
#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_NEIGHBOR_ADV(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+2, 0, 8, __Value)
#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+3, 0, 8, __Value)
#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_INFO(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+4, 0, 8, __Value)
#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_REMOTE_WAKE_CTRL_INFO(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 0, 8, __Value)
#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_ARP_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_NEIGHBOR_ADV(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_INFO(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
#ifdef CONFIG_GTK_OL
#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_EXT_MEM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+5, 0, 8, __Value)
#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_EXT_MEM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)
#endif //CONFIG_GTK_OL
#ifdef CONFIG_PNO_SUPPORT
#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_NLO_INFO(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd), 0, 8, __Value)
#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_NLO_INFO(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 0, 8, __Value)
#endif
#ifdef CONFIG_PNO_SUPPORT
// D0_Scan_Offload_Info_0x86
#define SET_H2CCMD_AOAC_NLO_FUN_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 3, 1, __Value)
#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_PROBE_PACKET(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+1, 0, 8, __Value)
#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_SCAN_INFO(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+2, 0, 8, __Value)
#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_SSID_INFO(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+3, 0, 8, __Value)
#define SET_H2CCMD_AOAC_NLO_IPS_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 4, 1, __Value)
#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_PROBE_PACKET(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_SCAN_INFO(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_SSID_INFO(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
#endif //CONFIG_PNO_SUPPORT
#ifdef CONFIG_P2P_WOWLAN
//P2P_RsvdPage_0x8a
#define SET_H2CCMD_RSVDPAGE_LOC_P2P_BCN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
#define SET_H2CCMD_RSVDPAGE_LOC_P2P_PROBE_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
#define SET_H2CCMD_RSVDPAGE_LOC_P2P_NEGO_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
#define SET_H2CCMD_RSVDPAGE_LOC_P2P_INVITE_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
#define SET_H2CCMD_RSVDPAGE_LOC_P2P_PD_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
#endif //CONFIG_P2P_WOWLAN
//---------------------------------------------------------------------------------------------------------//
//------------------------------------------- Structure --------------------------------------------------//
//---------------------------------------------------------------------------------------------------------//
@@ -286,16 +340,26 @@ typedef struct _RSVDPAGE_LOC {
u8 LocProbePacket;
#endif //CONFIG_PNO_SUPPORT
#endif //CONFIG_WOWLAN
#ifdef CONFIG_AP_WOWLAN
u8 LocApOffloadBCN;
#endif //CONFIG_AP_WOWLAN
#ifdef CONFIG_P2P_WOWLAN
u8 LocP2PBeacon;
u8 LocP2PProbeRsp;
u8 LocNegoRsp;
u8 LocInviteRsp;
u8 LocPDRsp;
#endif //CONFIG_P2P_WOWLAN
} RSVDPAGE_LOC, *PRSVDPAGE_LOC;
#endif
void dump_TX_FIFO(PADAPTER padapter, u8 page_num, u16 page_size);
u8 rtw_check_invalid_mac_address (u8 *mac_addr);
u8 rtw_hal_set_fw_media_status_cmd(_adapter* adapter, u8 mstatus, u8 macid);
#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
void rtw_get_current_ip_address(PADAPTER padapter, u8 *pcurrentip);
void rtw_get_sec_iv(PADAPTER padapter, u8*pcur_dot11txpn, u8 *StaAddr);
void rtw_set_sec_pn(_adapter *padapter);
//WOW command function
void rtw_hal_set_fw_wow_related_cmd(_adapter* padapter, u8 enable);
#ifdef CONFIG_P2P_WOWLAN
//H2C 0x8A
u8 rtw_hal_set_FwP2PRsvdPage_cmd(_adapter* adapter, PRSVDPAGE_LOC rsvdpageloc);
//H2C 0x8B
u8 rtw_hal_set_p2p_wowlan_offload_cmd(_adapter* adapter);
#endif //CONFIG_P2P_WOWLAN
#endif

3
include/hal_com_led.h
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@@ -264,7 +264,8 @@ typedef struct _LED_USB{
_timer BlinkTimer; // Timer object for led blinking.
_workitem BlinkWorkItem; // Workitem used by BlinkTimer to manipulate H/W to blink LED.
_workitem BlinkWorkItem; // Workitem used by BlinkTimer to manipulate H/W to blink LED.'
ATOMIC_T bCancelWorkItem; //check if WorkItem is cancelled
} LED_USB, *PLED_USB;
typedef struct _LED_USB LED_DATA, *PLED_DATA;

89
include/hal_com_phycfg.h
View File

@@ -25,19 +25,6 @@
#define PathC 0x2
#define PathD 0x3
typedef enum _RATE_SECTION {
CCK = 0,
OFDM,
HT_MCS0_MCS7,
HT_MCS8_MCS15,
HT_MCS16_MCS23,
HT_MCS24_MCS31,
VHT_1SSMCS0_1SSMCS9,
VHT_2SSMCS0_2SSMCS9,
VHT_3SSMCS0_3SSMCS9,
VHT_4SSMCS0_4SSMCS9,
} RATE_SECTION;
typedef enum _RF_TX_NUM {
RF_1TX = 0,
RF_2TX,
@@ -58,6 +45,9 @@ typedef enum _REGULATION_TXPWR_LMT {
TXPWR_LMT_MAX_REGULATION_NUM = 4
} REGULATION_TXPWR_LMT;
#define TX_PWR_LMT_REF_VHT_FROM_HT BIT0
#define TX_PWR_LMT_REF_HT_FROM_VHT BIT1
/*------------------------------Define structure----------------------------*/
typedef struct _BB_REGISTER_DEFINITION{
u32 rfintfs; // set software control:
@@ -84,13 +74,6 @@ typedef struct _BB_REGISTER_DEFINITION{
//----------------------------------------------------------------------
s32
phy_TxPwrIdxToDbm(
IN PADAPTER Adapter,
IN WIRELESS_MODE WirelessMode,
IN u8 TxPwrIdx
);
u8
PHY_GetTxPowerByRateBase(
IN PADAPTER Adapter,
@@ -100,22 +83,24 @@ PHY_GetTxPowerByRateBase(
IN RATE_SECTION RateSection
);
#ifdef TX_POWER_BY_RATE_OLD
u8
PHY_GetRateSectionIndexOfTxPowerByRate(
IN PADAPTER pAdapter,
IN u32 RegAddr,
IN u32 BitMask
);
#endif /* TX_POWER_BY_RATE_OLD */
VOID
PHY_GetRateValuesOfTxPowerByRate(
IN PADAPTER pAdapter,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Value,
OUT u8* RateIndex,
OUT s8* PwrByRateVal,
OUT u8* RateNum
IN PADAPTER pAdapter,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Value,
OUT u8 *Rate,
OUT s8 *PwrByRateVal,
OUT u8 *RateNum
);
u8
@@ -131,6 +116,15 @@ PHY_SetTxPowerIndexByRateSection(
IN u8 RateSection
);
s8
_PHY_GetTxPowerByRate(
IN PADAPTER pAdapter,
IN u8 Band,
IN u8 RFPath,
IN u8 TxNum,
IN u8 RateIndex
);
s8
PHY_GetTxPowerByRate(
IN PADAPTER pAdapter,
@@ -209,18 +203,6 @@ PHY_GetTxPowerLimit(
IN u8 Channel
);
VOID
PHY_SetTxPowerLimit(
IN PADAPTER Adapter,
IN u8 *Regulation,
IN u8 *Band,
IN u8 *Bandwidth,
IN u8 *RateSection,
IN u8 *RfPath,
IN u8 *Channel,
IN u8 *PowerLimit
);
VOID
PHY_ConvertTxPowerLimitToPowerIndex(
IN PADAPTER Adapter
@@ -255,11 +237,20 @@ PHY_SetTxPowerIndex(
IN u8 Rate
);
VOID
Hal_ChannelPlanToRegulation(
IN PADAPTER Adapter,
IN u16 ChannelPlan
);
bool phy_is_tx_power_limit_needed(_adapter *adapter);
bool phy_is_tx_power_by_rate_needed(_adapter *adapter);
int phy_load_tx_power_by_rate(_adapter *adapter, const char *hal_file_name, u8 force);
int phy_load_tx_power_limit(_adapter *adapter, const char *hal_file_name, u8 force);
void phy_load_tx_power_ext_info(_adapter *adapter, u8 chk_file, u8 force);
void phy_reload_tx_power_ext_info(_adapter *adapter);
void phy_reload_default_tx_power_ext_info(_adapter *adapter);
void dump_tx_power_ext_info(void *sel, _adapter *adapter);
void dump_target_tx_power(void *sel, _adapter *adapter);
void dump_tx_power_by_rate(void *sel, _adapter *adapter);
void dump_tx_power_limit(void *sel, _adapter *adapter);
int rtw_is_phy_file_readable(const char *hal_file_name);
#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
#define MAX_PARA_FILE_BUF_LEN 25600
@@ -276,7 +267,7 @@ int phy_ConfigMACWithParaFile(IN PADAPTER Adapter, IN char* pFileName);
int phy_ConfigBBWithParaFile(IN PADAPTER Adapter, IN char* pFileName, IN u32 ConfigType);
int phy_ConfigBBWithPgParaFile(IN PADAPTER Adapter, IN char* pFileName);
int phy_ConfigBBWithPgParaFile(IN PADAPTER Adapter, IN const char *pFileName);
int phy_ConfigBBWithMpParaFile(IN PADAPTER Adapter, IN char* pFileName);
@@ -284,11 +275,11 @@ int PHY_ConfigRFWithParaFile(IN PADAPTER Adapter, IN char* pFileName, IN u8 eRFP
int PHY_ConfigRFWithTxPwrTrackParaFile(IN PADAPTER Adapter, IN char* pFileName);
int PHY_ConfigRFWithPowerLimitTableParaFile(IN PADAPTER Adapter, IN char* pFileName);
int PHY_ConfigRFWithPowerLimitTableParaFile(IN PADAPTER Adapter, IN const char *pFileName);
void phy_free_filebuf_mask(_adapter *padapter, u8 mask);
void phy_free_filebuf(_adapter *padapter);
#endif //CONFIG_LOAD_PHY_PARA_FROM_FILE
#endif /* CONFIG_LOAD_PHY_PARA_FROM_FILE */
#endif //__HAL_COMMON_H__
#endif /* __HAL_COMMON_H__ */

66
include/hal_com_reg.h
View File

@@ -43,6 +43,7 @@
#define REG_SYS_FUNC_EN 0x0002
#define REG_APS_FSMCO 0x0004
#define REG_SYS_CLKR 0x0008
#define REG_SYS_CLK_CTRL REG_SYS_CLKR
#define REG_9346CR 0x000A
#define REG_SYS_EEPROM_CTRL 0x000A
#define REG_EE_VPD 0x000C
@@ -157,6 +158,10 @@
#define REG_HMEBOX_2 0x01D8
#define REG_HMEBOX_3 0x01DC
#define REG_LLT_INIT 0x01E0
#define REG_HMEBOX_EXT_0 0x01F0
#define REG_HMEBOX_EXT_1 0x01F4
#define REG_HMEBOX_EXT_2 0x01F8
#define REG_HMEBOX_EXT_3 0x01FC
//-----------------------------------------------------
@@ -188,28 +193,29 @@
//
//-----------------------------------------------------
#define REG_PCIE_CTRL_REG 0x0300
#define REG_INT_MIG 0x0304 // Interrupt Migration
#define REG_BCNQ_DESA 0x0308 // TX Beacon Descriptor Address
#define REG_HQ_DESA 0x0310 // TX High Queue Descriptor Address
#define REG_MGQ_DESA 0x0318 // TX Manage Queue Descriptor Address
#define REG_VOQ_DESA 0x0320 // TX VO Queue Descriptor Address
#define REG_VIQ_DESA 0x0328 // TX VI Queue Descriptor Address
#define REG_BEQ_DESA 0x0330 // TX BE Queue Descriptor Address
#define REG_BKQ_DESA 0x0338 // TX BK Queue Descriptor Address
#define REG_RX_DESA 0x0340 // RX Queue Descriptor Address
#define REG_INT_MIG 0x0304 /* Interrupt Migration */
#define REG_BCNQ_DESA 0x0308 /* TX Beacon Descriptor Address */
#define REG_HQ_DESA 0x0310 /* TX High Queue Descriptor Address */
#define REG_MGQ_DESA 0x0318 /* TX Manage Queue Descriptor Address */
#define REG_VOQ_DESA 0x0320 /* TX VO Queue Descriptor Address */
#define REG_VIQ_DESA 0x0328 /* TX VI Queue Descriptor Address */
#define REG_BEQ_DESA 0x0330 /* TX BE Queue Descriptor Address */
#define REG_BKQ_DESA 0x0338 /* TX BK Queue Descriptor Address */
#define REG_RX_DESA 0x0340 /* RX Queue Descriptor Address */
//sherry added for DBI Read/Write 20091126
#define REG_DBI_WDATA 0x0348 // Backdoor REG for Access Configuration
#define REG_DBI_RDATA 0x034C //Backdoor REG for Access Configuration
#define REG_DBI_CTRL 0x0350 //Backdoor REG for Access Configuration
#define REG_DBI_FLAG 0x0352 //Backdoor REG for Access Configuration
#define REG_MDIO 0x0354 // MDIO for Access PCIE PHY
#define REG_DBG_SEL 0x0360 // Debug Selection Register
#define REG_PCIE_HRPWM 0x0361 //PCIe RPWM
#define REG_PCIE_HCPWM 0x0363 //PCIe CPWM
#define REG_DBI_WDATA 0x0348 /* Backdoor REG for Access Configuration */
#define REG_DBI_RDATA 0x034C /* Backdoor REG for Access Configuration */
#define REG_DBI_CTRL 0x0350 /* Backdoor REG for Access Configuration */
#define REG_DBI_FLAG 0x0352 /* Backdoor REG for Access Configuration */
#define REG_MDIO 0x0354 /* MDIO for Access PCIE PHY */
#define REG_DBG_SEL 0x0360 /* Debug Selection Register */
#define REG_PCIE_HRPWM 0x0361 /* PCIe RPWM */
#define REG_PCIE_HCPWM 0x0363 /* PCIe CPWM */
#define REG_WATCH_DOG 0x0368
#define REG_RX_RXBD_NUM 0x0382
// RTL8723 series -------------------------------
#define REG_PCIE_HISR_EN 0x0394 //PCIE Local Interrupt Enable Register
#define REG_PCIE_HISR_EN 0x0394 /* PCIE Local Interrupt Enable Register */
#define REG_PCIE_HISR 0x03A0
#define REG_PCIE_HISRE 0x03A4
#define REG_PCIE_HIMR 0x03A8
@@ -1065,28 +1071,27 @@ Current IOREG MAP
#define RCR_APP_ICV BIT29 // MACRX will retain the ICV at the bottom of the packet.
#define RCR_APP_PHYST_RXFF BIT28 // PHY Status is appended before RX packet in RXFF
#define RCR_APP_BA_SSN BIT27 // SSN of previous TXBA is appended as after original RXDESC as the 4-th DW of RXDESC.
#define RCR_NONQOS_VHT BIT26 // Reserved
#define RCR_RSVD_BIT25 BIT25 // Reserved
#define RCR_VHT_DACK BIT26 /* This bit to control response type for vht single mpdu data packet. 1. ACK as response 0. BA as response */
#define RCR_TCPOFLD_EN BIT25 /* Enable TCP checksum offload */
#define RCR_ENMBID BIT24 // Enable Multiple BssId. Only response ACK to the packets whose DID(A1) matching to the addresses in the MBSSID CAM Entries.
#define RCR_LSIGEN BIT23 // Enable LSIG TXOP Protection function. Search KEYCAM for each rx packet to check if LSIGEN bit is set.
#define RCR_MFBEN BIT22 // Enable immediate MCS Feedback function. When Rx packet with MRQ = 1'b1, then search KEYCAM to find sender's MCS Feedback function and send response.
#define RCR_RSVD_BIT21 BIT21 // Reserved
#define RCR_RSVD_BIT20 BIT20 // Reserved
#define RCR_RSVD_BIT19 BIT19 // Reserved
#define RCR_DISCHKPPDLLEN BIT21 /* Do not check PPDU while the PPDU length is smaller than 14 byte. */
#define RCR_PKTCTL_DLEN BIT20 /* While rx path dead lock occurs, reset rx path */
#define RCR_DISGCLK BIT19 /* Disable macrx clock gating control (no used) */
#define RCR_TIM_PARSER_EN BIT18 // RX Beacon TIM Parser.
#define RCR_BM_DATA_EN BIT17 // Broadcast data packet interrupt enable.
#define RCR_UC_DATA_EN BIT16 // Unicast data packet interrupt enable.
#define RCR_RSVD_BIT15 BIT15 // Reserved
#define RCR_BC_MD_EN BIT17 /* Broadcast data packet more data bit check interrupt enable.*/
#define RCR_UC_MD_EN BIT16 /* Unicast data packet more data bit check interrupt enable. */
#define RCR_RXSK_PERPKT BIT15 /* Executing key search per MPDU */
#define RCR_HTC_LOC_CTRL BIT14 // MFC<--HTC=1 MFC-->HTC=0
#define RCR_AMF BIT13 // Accept management type frame
#define RCR_ACF BIT12 // Accept control type frame. Control frames BA, BAR, and PS-Poll (when in AP mode) are not controlled by this bit. They are controlled by ADF.
#define RCR_ADF BIT11 // Accept data type frame. This bit also regulates BA, BAR, and PS-Poll (AP mode only).
#define RCR_RSVD_BIT10 BIT10 // Reserved
#define RCR_DISDECMYPKT BIT10 /* This bit determines whether hw need to do decryption.1: If A1 match, do decryption.0: Do decryption. */
#define RCR_AICV BIT9 // Accept ICV error packet
#define RCR_ACRC32 BIT8 // Accept CRC32 error packet
#define RCR_CBSSID_BCN BIT7 // Accept BSSID match packet (Rx beacon, probe rsp)
#define RCR_CBSSID_DATA BIT6 // Accept BSSID match packet (Data)
#define RCR_CBSSID RCR_CBSSID_DATA // Accept BSSID match packet
#define RCR_APWRMGT BIT5 // Accept power management packet
#define RCR_ADD3 BIT4 // Accept address 3 match packet
#define RCR_AB BIT3 // Accept broadcast packet
@@ -1211,6 +1216,7 @@ Current IOREG MAP
#define RFINI_RDY BIT(5)
#define WINTINI_RDY BIT(6)
#define RAM_DL_SEL BIT(7)
#define CPU_DL_READY BIT(15) /* add flag by gw for fw download ready 20130826 */
#define ROM_DLEN BIT(19)
#define CPRST BIT(23)
@@ -1545,6 +1551,7 @@ Current IOREG MAP
#define SCR_TXBCUSEDK BIT(6) // Force Tx Broadcast packets Use Default Key
#define SCR_RXBCUSEDK BIT(7) // Force Rx Broadcast packets Use Default Key
#define SCR_CHK_KEYID BIT(8)
#define SCR_CHK_BMC BIT(9) /* add option to support a2+keyid+bcm */
//-----------------------------------------------------
//
@@ -1751,7 +1758,9 @@ Current IOREG MAP
#define LAST_ENTRY_OF_TX_PKT_BUFFER_8812 255
#define LAST_ENTRY_OF_TX_PKT_BUFFER_8723B 255
#define LAST_ENTRY_OF_TX_PKT_BUFFER_8192C 255
#define LAST_ENTRY_OF_TX_PKT_BUFFER_8703B 255
#define LAST_ENTRY_OF_TX_PKT_BUFFER_DUAL_MAC 127
#define LAST_ENTRY_OF_TX_PKT_BUFFER_8188F 255
#define POLLING_LLT_THRESHOLD 20
#if defined(CONFIG_RTL8723B) && defined(CONFIG_PCI_HCI)
@@ -1762,6 +1771,7 @@ Current IOREG MAP
// GPIO BIT
#define HAL_8812A_HW_GPIO_WPS_BIT BIT2
#define HAL_8192C_HW_GPIO_WPS_BIT BIT2
#define HAL_8192EU_HW_GPIO_WPS_BIT BIT7
#define HAL_8188E_HW_GPIO_WPS_BIT BIT7

600
include/hal_data.h
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File diff suppressed because it is too large Load Diff

93
include/hal_ic_cfg.h Normal file
View File

@@ -0,0 +1,93 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __HAL_IC_CFG_H__
#define __HAL_IC_CFG_H__
#define RTL8188E_SUPPORT 0
#define RTL8812A_SUPPORT 0
#define RTL8821A_SUPPORT 0
#define RTL8723B_SUPPORT 0
#define RTL8192E_SUPPORT 0
#define RTL8814A_SUPPORT 0
#define RTL8195A_SUPPORT 0
#define RTL8703B_SUPPORT 0
#define RTL8188F_SUPPORT 0
#define RTL8822B_SUPPORT 0
#define RTL8821B_SUPPORT 0
/*#if (RTL8188E_SUPPORT==1)*/
#define RATE_ADAPTIVE_SUPPORT 0
#define POWER_TRAINING_ACTIVE 0
#ifdef CONFIG_MULTIDRV
#endif
#ifdef CONFIG_RTL8188E
#undef RTL8188E_SUPPORT
#undef RATE_ADAPTIVE_SUPPORT
#undef POWER_TRAINING_ACTIVE
#define RTL8188E_SUPPORT 1
#define RATE_ADAPTIVE_SUPPORT 1
#define POWER_TRAINING_ACTIVE 1
#endif
#ifdef CONFIG_RTL8812A
#undef RTL8812A_SUPPORT
#define RTL8812A_SUPPORT 1
#endif
#ifdef CONFIG_RTL8821A
#undef RTL8821A_SUPPORT
#define RTL8821A_SUPPORT 1
#endif
#ifdef CONFIG_RTL8192E
#undef RTL8192E_SUPPORT
#define RTL8192E_SUPPORT 1
#endif
#ifdef CONFIG_RTL8723B
#undef RTL8723B_SUPPORT
#define RTL8723B_SUPPORT 1
#endif
#ifdef CONFIG_RTL8814A
#undef RTL8814A_SUPPORT
#define RTL8814A_SUPPORT 1
#endif
#ifdef CONFIG_RTL8703B
#undef RTL8703B_SUPPORT
#define RTL8703B_SUPPORT 1
#endif
#ifdef CONFIG_RTL8188F
#undef RTL8188F_SUPPORT
#define RTL8188F_SUPPORT 1
#endif
#ifdef CONFIG_RTL8822B
#undef RTL8822B_SUPPORT
#define RTL8822B_SUPPORT 1
#endif
#endif /*__HAL_IC_CFG_H__*/

421
include/hal_intf.h
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File diff suppressed because it is too large Load Diff

406
include/hal_pg.h
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File diff suppressed because it is too large Load Diff

14
include/hal_phy.h
View File

@@ -56,13 +56,6 @@
/*--------------------------Define Parameters-------------------------------*/
typedef enum _BAND_TYPE{
BAND_ON_2_4G = 0,
BAND_ON_5G,
BAND_ON_BOTH,
BANDMAX
}BAND_TYPE,*PBAND_TYPE;
typedef enum _RF_TYPE{
RF_TYPE_MIN = 0, // 0
RF_8225=1, // 1 11b/g RF for verification only
@@ -73,13 +66,6 @@ typedef enum _RF_TYPE{
RF_TYPE_MAX
}RF_TYPE_E,*PRF_TYPE_E;
typedef enum _RF_PATH{
RF_PATH_A = 0,
RF_PATH_B,
RF_PATH_C,
RF_PATH_D
}RF_PATH, *PRF_PATH;
#define TX_1S 0
#define TX_2S 1
#define TX_3S 2

141
include/ieee80211.h
View File

@@ -166,6 +166,10 @@ typedef enum _RATEID_IDX_ {
RATEID_IDX_B = 8,
RATEID_IDX_VHT_2SS = 9,
RATEID_IDX_VHT_1SS = 10,
RATEID_IDX_MIX1 = 11,
RATEID_IDX_MIX2 = 12,
RATEID_IDX_VHT_3SS = 13,
RATEID_IDX_BGN_3SS = 14,
} RATEID_IDX, *PRATEID_IDX;
typedef enum _RATR_TABLE_MODE{
@@ -207,13 +211,13 @@ enum NETWORK_TYPE
//Type for registry default wireless mode
WIRELESS_11AGN = (WIRELESS_11A|WIRELESS_11G|WIRELESS_11_24N|WIRELESS_11_5N), // tx: ofdm & MCS, rx: ofdm & MCS, hw: ofdm only
WIRELESS_11ABGN = (WIRELESS_11A|WIRELESS_11B|WIRELESS_11G|WIRELESS_11_24N|WIRELESS_11_5N),
WIRELESS_MODE_24G = (WIRELESS_11B|WIRELESS_11G|WIRELESS_11_24N|WIRELESS_11AC),
WIRELESS_MODE_24G = (WIRELESS_11B|WIRELESS_11G|WIRELESS_11_24N),
WIRELESS_MODE_5G = (WIRELESS_11A|WIRELESS_11_5N|WIRELESS_11AC),
WIRELESS_MODE_MAX = (WIRELESS_11A|WIRELESS_11B|WIRELESS_11G|WIRELESS_11_24N|WIRELESS_11_5N|WIRELESS_11AC),
};
#define SUPPORTED_24G_NETTYPE_MSK (WIRELESS_11B | WIRELESS_11G | WIRELESS_11_24N)
#define SUPPORTED_5G_NETTYPE_MSK (WIRELESS_11A | WIRELESS_11_5N)
#define SUPPORTED_24G_NETTYPE_MSK WIRELESS_MODE_24G
#define SUPPORTED_5G_NETTYPE_MSK WIRELESS_MODE_5G
#define IsLegacyOnly(NetType) ((NetType) == ((NetType) & (WIRELESS_11BG|WIRELESS_11A)))
@@ -836,11 +840,81 @@ enum MGN_RATE{
MGN_UNKNOWN
};
#define IS_HT_RATE(_rate) (_rate >= MGN_MCS0 && _rate <= MGN_MCS31)
#define IS_VHT_RATE(_rate) (_rate >= MGN_VHT1SS_MCS0 && _rate <= MGN_VHT4SS_MCS9)
#define IS_CCK_RATE(_rate) (MGN_1M == _rate || _rate == MGN_2M || _rate == MGN_5_5M || _rate == MGN_11M )
#define IS_OFDM_RATE(_rate) (MGN_6M <= _rate && _rate <= MGN_54M && _rate != MGN_11M)
#define IS_HT_RATE(_rate) ((_rate) >= MGN_MCS0 && (_rate) <= MGN_MCS31)
#define IS_VHT_RATE(_rate) ((_rate) >= MGN_VHT1SS_MCS0 && (_rate) <= MGN_VHT4SS_MCS9)
#define IS_CCK_RATE(_rate) ((_rate) == MGN_1M || (_rate) == MGN_2M || (_rate) == MGN_5_5M || (_rate) == MGN_11M)
#define IS_OFDM_RATE(_rate) ((_rate) >= MGN_6M && (_rate) <= MGN_54M && (_rate) != MGN_11M)
#define IS_HT1SS_RATE(_rate) ((_rate) >= MGN_MCS0 && (_rate) <= MGN_MCS7)
#define IS_HT2SS_RATE(_rate) ((_rate) >= MGN_MCS8 && (_rate) <= MGN_MCS15)
#define IS_HT3SS_RATE(_rate) ((_rate) >= MGN_MCS16 && (_rate) <= MGN_MCS23)
#define IS_HT4SS_RATE(_rate) ((_rate) >= MGN_MCS24 && (_rate) <= MGN_MCS31)
#define IS_VHT1SS_RATE(_rate) ((_rate) >= MGN_VHT1SS_MCS0 && (_rate) <= MGN_VHT1SS_MCS9)
#define IS_VHT2SS_RATE(_rate) ((_rate) >= MGN_VHT2SS_MCS0 && (_rate) <= MGN_VHT2SS_MCS9)
#define IS_VHT3SS_RATE(_rate) ((_rate) >= MGN_VHT3SS_MCS0 && (_rate) <= MGN_VHT3SS_MCS9)
#define IS_VHT4SS_RATE(_rate) ((_rate) >= MGN_VHT4SS_MCS0 && (_rate) <= MGN_VHT4SS_MCS9)
#define IS_1T_RATE(_rate) (IS_CCK_RATE((_rate)) || IS_OFDM_RATE((_rate)) || IS_HT1SS_RATE((_rate)) || IS_VHT1SS_RATE((_rate)))
#define IS_2T_RATE(_rate) (IS_HT2SS_RATE((_rate)) || IS_VHT2SS_RATE((_rate)))
#define IS_3T_RATE(_rate) (IS_HT3SS_RATE((_rate)) || IS_VHT3SS_RATE((_rate)))
#define IS_4T_RATE(_rate) (IS_HT4SS_RATE((_rate)) || IS_VHT4SS_RATE((_rate)))
typedef enum _RATE_SECTION {
CCK = 0,
OFDM = 1,
HT_MCS0_MCS7 = 2,
HT_MCS8_MCS15 = 3,
HT_MCS16_MCS23 = 4,
HT_MCS24_MCS31 = 5,
HT_1SS = HT_MCS0_MCS7,
HT_2SS = HT_MCS8_MCS15,
HT_3SS = HT_MCS16_MCS23,
HT_4SS = HT_MCS24_MCS31,
VHT_1SSMCS0_1SSMCS9 = 6,
VHT_2SSMCS0_2SSMCS9 = 7,
VHT_3SSMCS0_3SSMCS9 = 8,
VHT_4SSMCS0_4SSMCS9 = 9,
VHT_1SS = VHT_1SSMCS0_1SSMCS9,
VHT_2SS = VHT_2SSMCS0_2SSMCS9,
VHT_3SS = VHT_3SSMCS0_3SSMCS9,
VHT_4SS = VHT_4SSMCS0_4SSMCS9,
RATE_SECTION_NUM,
} RATE_SECTION;
const char *rate_section_str(u8 section);
#define IS_CCK_RATE_SECTION(section) ((section) == CCK)
#define IS_OFDM_RATE_SECTION(section) ((section) == OFDM)
#define IS_HT_RATE_SECTION(section) ((section) >= HT_1SS && (section) <= HT_4SS)
#define IS_VHT_RATE_SECTION(section) ((section) >= VHT_1SS && (section) <= VHT_4SS)
#define IS_1T_RATE_SECTION(section) ((section) == CCK || (section) == OFDM || (section) == HT_1SS || (section) == VHT_1SS)
#define IS_2T_RATE_SECTION(section) ((section) == HT_2SS || (section) == VHT_2SS)
#define IS_3T_RATE_SECTION(section) ((section) == HT_3SS || (section) == VHT_3SS)
#define IS_4T_RATE_SECTION(section) ((section) == HT_4SS || (section) == VHT_4SS)
extern u8 mgn_rates_cck[];
extern u8 mgn_rates_ofdm[];
extern u8 mgn_rates_mcs0_7[];
extern u8 mgn_rates_mcs8_15[];
extern u8 mgn_rates_mcs16_23[];
extern u8 mgn_rates_mcs24_31[];
extern u8 mgn_rates_vht1ss[];
extern u8 mgn_rates_vht2ss[];
extern u8 mgn_rates_vht3ss[];
extern u8 mgn_rates_vht4ss[];
struct rate_section_ent {
u8 tx_num; /* value of RF_TX_NUM */
u8 rate_num;
u8 *rates;
};
extern struct rate_section_ent rates_by_sections[];
#define rate_section_to_tx_num(section) (rates_by_sections[(section)].tx_num)
#define rate_section_rate_num(section) (rates_by_sections[(section)].rate_num)
/* NOTE: This data is for statistical purposes; not all hardware provides this
* information for frames received. Not setting these will not cause
@@ -1307,6 +1381,8 @@ enum ieee80211_state {
#define MAC_ARG(x) ((u8*)(x))[0],((u8*)(x))[1],((u8*)(x))[2],((u8*)(x))[3],((u8*)(x))[4],((u8*)(x))[5]
#define IP_FMT "%d.%d.%d.%d"
#define IP_ARG(x) ((u8*)(x))[0],((u8*)(x))[1],((u8*)(x))[2],((u8*)(x))[3]
#define PORT_FMT "%u"
#define PORT_ARG(x) ntohs(*((u16 *)(x)))
#ifdef PLATFORM_FREEBSD //Baron change func to macro
#define is_multicast_mac_addr(Addr) ((((Addr[0]) & 0x01) == 0x01) && ((Addr[0]) != 0xff))
@@ -1342,7 +1418,7 @@ typedef struct tx_pending_t{
#define MAXTID 16
#define TID_NUM 16
#define IEEE_A (1<<0)
#define IEEE_B (1<<1)
@@ -1461,6 +1537,13 @@ enum rtw_ieee80211_back_parties {
RTW_WLAN_BACK_TIMER = 2,
};
/*20/40 BSS Coexistence element */
#define RTW_WLAN_20_40_BSS_COEX_INFO_REQ BIT(0)
#define RTW_WLAN_20_40_BSS_COEX_40MHZ_INTOL BIT(1)
#define RTW_WLAN_20_40_BSS_COEX_20MHZ_WIDTH_REQ BIT(2)
#define RTW_WLAN_20_40_BSS_COEX_OBSS_EXEMPT_REQ BIT(3)
#define RTW_WLAN_20_40_BSS_COEX_OBSS_EXEMPT_GRNT BIT(4)
/* VHT features action code */
enum rtw_ieee80211_vht_actioncode{
RTW_WLAN_ACTION_VHT_COMPRESSED_BEAMFORMING = 0,
@@ -1679,31 +1762,43 @@ void dump_ht_cap_ie_content(void *sel, u8 *buf, u32 buf_len);
void dump_wps_ie(void *sel, u8 *ie, u32 ie_len);
#ifdef CONFIG_P2P
void rtw_ies_get_chbw(u8 *ies, int ies_len, u8 *ch, u8 *bw, u8 *offset);
void rtw_bss_get_chbw(WLAN_BSSID_EX *bss, u8 *ch, u8 *bw, u8 *offset);
bool rtw_is_chbw_grouped(u8 ch_a, u8 bw_a, u8 offset_a
, u8 ch_b, u8 bw_b, u8 offset_b);
void rtw_sync_chbw(u8 *req_ch, u8 *req_bw, u8 *req_offset
, u8 *g_ch, u8 *g_bw, u8 *g_offset);
u32 rtw_get_p2p_merged_ies_len(u8 *in_ie, u32 in_len);
int rtw_p2p_merge_ies(u8 *in_ie, u32 in_len, u8 *merge_ie);
void dump_p2p_ie(void *sel, u8 *ie, u32 ie_len);
u8 *rtw_get_p2p_ie(u8 *in_ie, int in_len, u8 *p2p_ie, uint *p2p_ielen);
u8 *rtw_get_p2p_ie_from_scan_queue(u8 *in_ie, int in_len, u8 *p2p_ie, uint *p2p_ielen, u8 frame_type);
u8 *rtw_get_p2p_attr(u8 *p2p_ie, uint p2p_ielen, u8 target_attr_id ,u8 *buf_attr, u32 *len_attr);
u8 *rtw_get_p2p_attr_content(u8 *p2p_ie, uint p2p_ielen, u8 target_attr_id ,u8 *buf_content, uint *len_content);
u32 rtw_set_p2p_attr_content(u8 *pbuf, u8 attr_id, u16 attr_len, u8 *pdata_attr);
void rtw_WLAN_BSSID_EX_remove_p2p_attr(WLAN_BSSID_EX *bss_ex, u8 attr_id);
#endif
uint rtw_del_p2p_ie(u8 *ies, uint ies_len_ori, const char *msg);
uint rtw_del_p2p_attr(u8 *ie, uint ielen_ori, u8 attr_id);
u8 *rtw_bss_ex_get_p2p_ie(WLAN_BSSID_EX *bss_ex, u8 *p2p_ie, uint *p2p_ielen);
void rtw_bss_ex_del_p2p_ie(WLAN_BSSID_EX *bss_ex);
void rtw_bss_ex_del_p2p_attr(WLAN_BSSID_EX *bss_ex, u8 attr_id);
#ifdef CONFIG_WFD
void dump_wfd_ie(void *sel, u8 *ie, u32 ie_len);
int rtw_get_wfd_ie(u8 *in_ie, int in_len, u8 *wfd_ie, uint *wfd_ielen);
int rtw_get_wfd_ie_from_scan_queue(u8 *in_ie, int in_len, u8 *p2p_ie, uint *p2p_ielen, u8 frame_type);
int rtw_get_wfd_attr_content(u8 *wfd_ie, uint wfd_ielen, u8 target_attr_id ,u8 *attr_content, uint *attr_contentlen);
#endif // CONFIG_WFD
u8 *rtw_get_wfd_ie(u8 *in_ie, int in_len, u8 *wfd_ie, uint *wfd_ielen);
u8 *rtw_get_wfd_attr(u8 *wfd_ie, uint wfd_ielen, u8 target_attr_id, u8 *buf_attr, u32 *len_attr);
u8 *rtw_get_wfd_attr_content(u8 *wfd_ie, uint wfd_ielen, u8 target_attr_id, u8 *buf_content, uint *len_content);
uint rtw_del_wfd_ie(u8 *ies, uint ies_len_ori, const char *msg);
uint rtw_del_wfd_attr(u8 *ie, uint ielen_ori, u8 attr_id);
u8 *rtw_bss_ex_get_wfd_ie(WLAN_BSSID_EX *bss_ex, u8 *wfd_ie, uint *wfd_ielen);
void rtw_bss_ex_del_wfd_ie(WLAN_BSSID_EX *bss_ex);
void rtw_bss_ex_del_wfd_attr(WLAN_BSSID_EX *bss_ex, u8 attr_id);
uint rtw_get_rateset_len(u8 *rateset);
struct registry_priv;
int rtw_generate_ie(struct registry_priv *pregistrypriv);
int rtw_get_bit_value_from_ieee_value(u8 val);
uint rtw_is_cckrates_included(u8 *rate);
@@ -1714,12 +1809,20 @@ int rtw_check_network_type(unsigned char *rate, int ratelen, int channel);
void rtw_get_bcn_info(struct wlan_network *pnetwork);
void rtw_macaddr_cfg(u8 *mac_addr);
u8 rtw_check_invalid_mac_address(u8 *mac_addr, u8 check_local_bit);
void rtw_macaddr_cfg(u8 *out, const u8 *hw_mac_addr);
u16 rtw_mcs_rate(u8 rf_type, u8 bw_40MHz, u8 short_GI, unsigned char * MCS_rate);
u8 rtw_ht_mcsset_to_nss(u8 *supp_mcs_set);
int rtw_action_frame_parse(const u8 *frame, u32 frame_len, u8* category, u8 *action);
const char *action_public_str(u8 action);
u8 key_2char2num(u8 hch, u8 lch);
u8 str_2char2num(u8 hch, u8 lch);
void macstr2num(u8 *dst, u8 *src);
u8 convert_ip_addr(u8 hch, u8 mch, u8 lch);
int wifirate2_ratetbl_inx(unsigned char rate);
#endif /* IEEE80211_H */

177
include/ioctl_cfg80211.h
View File

@@ -1,177 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __IOCTL_CFG80211_H__
#define __IOCTL_CFG80211_H__
#if defined(RTW_USE_CFG80211_STA_EVENT)
#undef CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER
#endif
struct rtw_wdev_invit_info {
u8 state; /* 0: req, 1:rep */
u8 peer_mac[ETH_ALEN];
u8 active;
u8 token;
u8 flags;
u8 status;
u8 req_op_ch;
u8 rsp_op_ch;
};
#define rtw_wdev_invit_info_init(invit_info) \
do { \
(invit_info)->state = 0xff; \
_rtw_memset((invit_info)->peer_mac, 0, ETH_ALEN); \
(invit_info)->active = 0xff; \
(invit_info)->token = 0; \
(invit_info)->flags = 0x00; \
(invit_info)->status = 0xff; \
(invit_info)->req_op_ch = 0; \
(invit_info)->rsp_op_ch = 0; \
} while (0)
struct rtw_wdev_nego_info {
u8 state; /* 0: req, 1:rep, 2:conf */
u8 peer_mac[ETH_ALEN];
u8 active;
u8 token;
u8 status;
u8 req_intent;
u8 req_op_ch;
u8 req_listen_ch;
u8 rsp_intent;
u8 rsp_op_ch;
u8 conf_op_ch;
};
#define rtw_wdev_nego_info_init(nego_info) \
do { \
(nego_info)->state = 0xff; \
_rtw_memset((nego_info)->peer_mac, 0, ETH_ALEN); \
(nego_info)->active = 0xff; \
(nego_info)->token = 0; \
(nego_info)->status = 0xff; \
(nego_info)->req_intent = 0xff; \
(nego_info)->req_op_ch = 0; \
(nego_info)->req_listen_ch = 0; \
(nego_info)->rsp_intent = 0xff; \
(nego_info)->rsp_op_ch = 0; \
(nego_info)->conf_op_ch = 0; \
} while (0)
struct rtw_wdev_priv
{
struct wireless_dev *rtw_wdev;
_adapter *padapter;
struct cfg80211_scan_request *scan_request;
_lock scan_req_lock;
struct net_device *pmon_ndev;//for monitor interface
char ifname_mon[IFNAMSIZ + 1]; //interface name for monitor interface
u8 p2p_enabled;
u8 provdisc_req_issued;
struct rtw_wdev_invit_info invit_info;
struct rtw_wdev_nego_info nego_info;
u8 bandroid_scan;
bool block;
bool power_mgmt;
#ifdef CONFIG_CONCURRENT_MODE
ATOMIC_T ro_ch_to;
ATOMIC_T switch_ch_to;
#endif
};
#define wiphy_to_adapter(x) (*((_adapter**)wiphy_priv(x)))
#define wdev_to_ndev(w) ((w)->netdev)
int rtw_wdev_alloc(_adapter *padapter, struct device *dev);
void rtw_wdev_free(struct wireless_dev *wdev);
void rtw_wdev_unregister(struct wireless_dev *wdev);
void rtw_cfg80211_init_wiphy(_adapter *padapter);
void rtw_cfg80211_unlink_bss(_adapter *padapter, struct wlan_network *pnetwork);
void rtw_cfg80211_surveydone_event_callback(_adapter *padapter);
struct cfg80211_bss *rtw_cfg80211_inform_bss(_adapter *padapter, struct wlan_network *pnetwork);
int rtw_cfg80211_check_bss(_adapter *padapter);
void rtw_cfg80211_ibss_indicate_connect(_adapter *padapter);
void rtw_cfg80211_indicate_connect(_adapter *padapter);
void rtw_cfg80211_indicate_disconnect(_adapter *padapter);
void rtw_cfg80211_indicate_scan_done(_adapter *adapter, bool aborted);
#ifdef CONFIG_AP_MODE
void rtw_cfg80211_indicate_sta_assoc(_adapter *padapter, u8 *pmgmt_frame, uint frame_len);
void rtw_cfg80211_indicate_sta_disassoc(_adapter *padapter, unsigned char *da, unsigned short reason);
#endif //CONFIG_AP_MODE
void rtw_cfg80211_issue_p2p_provision_request(_adapter *padapter, const u8 *buf, size_t len);
void rtw_cfg80211_rx_p2p_action_public(_adapter *padapter, u8 *pmgmt_frame, uint frame_len);
void rtw_cfg80211_rx_action_p2p(_adapter *padapter, u8 *pmgmt_frame, uint frame_len);
void rtw_cfg80211_rx_action(_adapter *adapter, u8 *frame, uint frame_len, const char*msg);
int rtw_cfg80211_set_mgnt_wpsp2pie(struct net_device *net, char *buf, int len, int type);
bool rtw_cfg80211_pwr_mgmt(_adapter *adapter);
#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,4,0)) && !defined(COMPAT_KERNEL_RELEASE)
#define rtw_cfg80211_rx_mgmt(adapter, freq, sig_dbm, buf, len, gfp) cfg80211_rx_mgmt((adapter)->pnetdev, freq, buf, len, gfp)
#elif (LINUX_VERSION_CODE < KERNEL_VERSION(3,6,0))
#define rtw_cfg80211_rx_mgmt(adapter, freq, sig_dbm, buf, len, gfp) cfg80211_rx_mgmt((adapter)->pnetdev, freq, sig_dbm, buf, len, gfp)
#elif (LINUX_VERSION_CODE < KERNEL_VERSION(3,12,0))
#define rtw_cfg80211_rx_mgmt(adapter, freq, sig_dbm, buf, len, gfp) cfg80211_rx_mgmt((adapter)->rtw_wdev, freq, sig_dbm, buf, len, gfp)
#else
#define rtw_cfg80211_rx_mgmt(adapter, freq, sig_dbm, buf, len, gfp) cfg80211_rx_mgmt((adapter)->rtw_wdev, freq, sig_dbm, buf, len,0,gfp)
#endif
#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,4,0)) && !defined(COMPAT_KERNEL_RELEASE)
#define rtw_cfg80211_send_rx_assoc(adapter, bss, buf, len) cfg80211_send_rx_assoc((adapter)->pnetdev, buf, len)
#else
#define rtw_cfg80211_send_rx_assoc(adapter, bss, buf, len) cfg80211_send_rx_assoc((adapter)->pnetdev, bss, buf, len)
#endif
#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,6,0))
#define rtw_cfg80211_mgmt_tx_status(adapter, cookie, buf, len, ack, gfp) cfg80211_mgmt_tx_status((adapter)->pnetdev, cookie, buf, len, ack, gfp)
#else
#define rtw_cfg80211_mgmt_tx_status(adapter, cookie, buf, len, ack, gfp) cfg80211_mgmt_tx_status((adapter)->rtw_wdev, cookie, buf, len, ack, gfp)
#endif
#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,6,0))
#define rtw_cfg80211_ready_on_channel(adapter, cookie, chan, channel_type, duration, gfp) cfg80211_ready_on_channel((adapter)->pnetdev, cookie, chan, channel_type, duration, gfp)
#define rtw_cfg80211_remain_on_channel_expired(adapter, cookie, chan, chan_type, gfp) cfg80211_remain_on_channel_expired((adapter)->pnetdev, cookie, chan, chan_type, gfp)
#elif (LINUX_VERSION_CODE < KERNEL_VERSION(3,8,0))
#define rtw_cfg80211_ready_on_channel(adapter, cookie, chan, channel_type, duration, gfp) cfg80211_ready_on_channel((adapter)->rtw_wdev, cookie, chan, channel_type, duration, gfp)
#define rtw_cfg80211_remain_on_channel_expired(adapter, cookie, chan, chan_type, gfp) cfg80211_remain_on_channel_expired((adapter)->rtw_wdev, cookie, chan, chan_type, gfp)
#else
#define rtw_cfg80211_ready_on_channel(adapter, cookie, chan, channel_type, duration, gfp) cfg80211_ready_on_channel((adapter)->rtw_wdev, cookie, chan, duration, gfp)
#define rtw_cfg80211_remain_on_channel_expired(adapter, cookie, chan, chan_type, gfp) cfg80211_remain_on_channel_expired((adapter)->rtw_wdev, cookie, chan, gfp)
#endif
#endif //__IOCTL_CFG80211_H__

2
include/mlme_osdep.h
View File

@@ -26,7 +26,7 @@ extern int time_after(u32 now, u32 old);
#endif
extern void rtw_init_mlme_timer(_adapter *padapter);
extern void rtw_os_indicate_disconnect( _adapter *adapter );
extern void rtw_os_indicate_disconnect(_adapter *adapter, u16 reason, u8 locally_generated);
extern void rtw_os_indicate_connect( _adapter *adapter );
void rtw_os_indicate_scan_done( _adapter *padapter, bool aborted);
extern void rtw_report_sec_ie(_adapter *adapter,u8 authmode,u8 *sec_ie);

16
include/osdep_intf.h
View File

@@ -105,12 +105,20 @@ void rtw_cancel_dynamic_chk_timer(_adapter *padapter);
#endif
void rtw_cancel_all_timer(_adapter *padapter);
uint loadparam(_adapter *adapter);
#ifdef PLATFORM_LINUX
int rtw_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
int rtw_init_netdev_name(struct net_device *pnetdev, const char *ifname);
struct net_device *rtw_init_netdev(_adapter *padapter);
void rtw_unregister_netdevs(struct dvobj_priv *dvobj);
void rtw_os_ndev_free(_adapter *adapter);
int rtw_os_ndev_init(_adapter *adapter, char *name);
void rtw_os_ndev_deinit(_adapter *adapter);
void rtw_os_ndevs_unregister(struct dvobj_priv *dvobj);
int rtw_os_ndevs_init(struct dvobj_priv *dvobj);
void rtw_os_ndevs_deinit(struct dvobj_priv *dvobj);
#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35))
u16 rtw_recv_select_queue(struct sk_buff *skb);
@@ -120,6 +128,11 @@ int rtw_ndev_notifier_register(void);
void rtw_ndev_notifier_unregister(void);
#include "../os_dep/linux/rtw_proc.h"
#ifdef CONFIG_IOCTL_CFG80211
#include "../os_dep/linux/ioctl_cfg80211.h"
#endif //CONFIG_IOCTL_CFG80211
#endif //PLATFORM_LINUX
@@ -147,7 +160,6 @@ void rtw_drv_free_vir_ifaces(struct dvobj_priv *dvobj);
#endif //CONFIG_MULTI_VIR_IFACES
#endif
int rtw_drv_register_netdev(_adapter *padapter);
void rtw_ndev_destructor(_nic_hdl ndev);
#ifdef CONFIG_ARP_KEEP_ALIVE

18
include/osdep_service.h
View File

@@ -118,7 +118,8 @@ enum mstat_f {
MSTAT_FUNC_RX_IO = 0x03<<8,
MSTAT_FUNC_TX = 0x04<<8,
MSTAT_FUNC_RX = 0x05<<8,
MSTAT_FUNC_MAX = 0x06<<8,
MSTAT_FUNC_CFG_VENDOR = 0x06<<8,
MSTAT_FUNC_MAX = 0x07<<8,
};
#define mstat_tf_idx(flags) ((flags)&0xff)
@@ -255,7 +256,8 @@ void _rtw_usb_buffer_free(struct usb_device *dev, size_t size, void *addr, dma_a
extern void* rtw_malloc2d(int h, int w, size_t size);
extern void rtw_mfree2d(void *pbuf, int h, int w, int size);
extern void _rtw_memcpy(void* dec, void* sour, u32 sz);
extern void _rtw_memcpy(void *dec, const void *sour, u32 sz);
extern void _rtw_memmove(void *dst, const void *src, u32 sz);
extern int _rtw_memcmp(void *dst, void *src, u32 sz);
extern void _rtw_memset(void *pbuf, int c, u32 sz);
@@ -282,7 +284,8 @@ extern void _rtw_spinunlock(_lock *plock);
extern void _rtw_spinlock_ex(_lock *plock);
extern void _rtw_spinunlock_ex(_lock *plock);
extern void _rtw_init_queue(_queue *pqueue);
extern void _rtw_init_queue(_queue *pqueue);
extern void _rtw_deinit_queue(_queue *pqueue);
extern u32 _rtw_queue_empty(_queue *pqueue);
extern u32 rtw_end_of_queue_search(_list *queue, _list *pelement);
@@ -475,6 +478,8 @@ __inline static u32 bitshift(u32 bitmask)
}
#define rtw_min(a, b) ((a>b)?b:a)
#define rtw_is_range_a_in_b(hi_a, lo_a, hi_b, lo_b) (((hi_a) <= (hi_b)) && ((lo_a) >= (lo_b)))
#define rtw_is_range_overlap(hi_a, lo_a, hi_b, lo_b) (((hi_a) > (lo_b)) && ((lo_a) < (hi_b)))
#ifndef MAC_FMT
#define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x"
@@ -513,7 +518,7 @@ extern int ATOMIC_DEC_RETURN(ATOMIC_T *v);
//File operation APIs, just for linux now
extern int rtw_is_file_readable(char *path);
extern int rtw_retrive_from_file(char *path, u8* buf, u32 sz);
extern int rtw_retrieve_from_file(char *path, u8 *buf, u32 sz);
extern int rtw_store_to_file(char *path, u8* buf, u32 sz);
@@ -610,6 +615,11 @@ struct rtw_cbuf *rtw_cbuf_alloc(u32 size);
void rtw_cbuf_free(struct rtw_cbuf *cbuf);
// String handler
BOOLEAN IsHexDigit(char chTmp);
BOOLEAN is_alpha(char chTmp);
char alpha_to_upper(char c);
/*
* Write formatted output to sized buffer
*/

34
include/osdep_service_linux.h
View File

@@ -62,6 +62,12 @@
#include <linux/tqueue.h>
#endif
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 7, 0))
#include <uapi/linux/limits.h>
#else
#include <linux/limits.h>
#endif
#ifdef RTK_DMP_PLATFORM
#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,12))
#include <linux/pageremap.h>
@@ -69,10 +75,16 @@
#include <asm/io.h>
#endif
#ifdef CONFIG_NET_RADIO
#define CONFIG_WIRELESS_EXT
#endif
/* Monitor mode */
#include <net/ieee80211_radiotap.h>
#include <linux/ieee80211.h>
#ifdef CONFIG_IOCTL_CFG80211
// #include <linux/ieee80211.h>
#include <net/ieee80211_radiotap.h>
#include <net/cfg80211.h>
/* #include <linux/ieee80211.h> */
#include <net/cfg80211.h>
#endif //CONFIG_IOCTL_CFG80211
#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX
@@ -86,7 +98,7 @@
#ifdef CONFIG_EFUSE_CONFIG_FILE
#include <linux/fs.h>
#endif //CONFIG_EFUSE_CONFIG_FILE
#endif
#ifdef CONFIG_USB_HCI
#include <linux/usb.h>
@@ -97,6 +109,14 @@
#endif
#endif
#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
#include <net/sock.h>
#include <net/tcp.h>
#include <linux/udp.h>
#include <linux/in.h>
#include <linux/netlink.h>
#endif //CONFIG_BT_COEXIST_SOCKET_TRX
#ifdef CONFIG_USB_HCI
typedef struct urb * PURB;
#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,22))
@@ -262,11 +282,11 @@ __inline static void _set_timer(_timer *ptimer,u32 delay_time)
__inline static void _cancel_timer(_timer *ptimer,u8 *bcancelled)
{
del_timer_sync(ptimer);
*bcancelled= _TRUE;//TRUE ==1; FALSE==0
*bcancelled = 1;
}
__inline static void _init_workitem(_workitem *pwork, void *pfunc, PVOID cntx)
static inline void _init_workitem(_workitem *pwork, void *pfunc, void *cntx)
{
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
INIT_WORK(pwork, pfunc);
@@ -353,7 +373,7 @@ static inline void rtw_netif_stop_queue(struct net_device *pnetdev)
#endif
}
static inline void rtw_merge_string(char *dst, int dst_len, char *src1, char *src2)
static inline void rtw_merge_string(char *dst, int dst_len, const char *src1, const char *src2)
{
int len = 0;
len += snprintf(dst+len, dst_len - len, "%s", src1);

22
include/pci_hal.h
View File

@@ -20,31 +20,27 @@
#ifndef __PCI_HAL_H__
#define __PCI_HAL_H__
#ifdef CONFIG_RTL8192C
void rtl8192ce_set_hal_ops(_adapter * padapter);
#endif
#ifdef CONFIG_RTL8192D
void rtl8192de_set_hal_ops(_adapter * padapter);
#endif
#ifdef CONFIG_RTL8188E
void rtl8188ee_set_hal_ops(_adapter * padapter);
void rtl8188ee_set_hal_ops(_adapter *padapter);
#endif
#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
void rtl8812ae_set_hal_ops(_adapter * padapter);
void rtl8812ae_set_hal_ops(_adapter *padapter);
#endif
#if defined(CONFIG_RTL8192E)
void rtl8192ee_set_hal_ops(_adapter * padapter);
void rtl8192ee_set_hal_ops(_adapter *padapter);
#endif
#ifdef CONFIG_RTL8723B
void rtl8723be_set_hal_ops(_adapter * padapter);
void rtl8723be_set_hal_ops(_adapter *padapter);
#endif
void rtw_set_hal_ops(_adapter *padapter);
#ifdef CONFIG_RTL8814A
void rtl8814ae_set_hal_ops(_adapter *padapter);
#endif
u8 rtw_set_hal_ops(_adapter *padapter);
#endif //__PCIE_HAL_H__

60
include/pci_ops.h
View File

@@ -22,9 +22,9 @@
#ifdef CONFIG_RTL8188E
u32 rtl8188ee_init_desc_ring(_adapter * padapter);
u32 rtl8188ee_free_desc_ring(_adapter * padapter);
void rtl8188ee_reset_desc_ring(_adapter * padapter);
u32 rtl8188ee_init_desc_ring(_adapter *padapter);
u32 rtl8188ee_free_desc_ring(_adapter *padapter);
void rtl8188ee_reset_desc_ring(_adapter *padapter);
int rtl8188ee_interrupt(PADAPTER Adapter);
void rtl8188ee_xmit_tasklet(void *priv);
void rtl8188ee_recv_tasklet(void *priv);
@@ -32,35 +32,10 @@ void rtl8188ee_prepare_bcn_tasklet(void *priv);
void rtl8188ee_set_intf_ops(struct _io_ops *pops);
#endif
#ifdef CONFIG_RTL8192C
u32 rtl8192ce_init_desc_ring(_adapter * padapter);
u32 rtl8192ce_free_desc_ring(_adapter * padapter);
void rtl8192ce_reset_desc_ring(_adapter * padapter);
int rtl8192ce_interrupt(PADAPTER Adapter);
void rtl8192ce_xmit_tasklet(void *priv);
void rtl8192ce_recv_tasklet(void *priv);
void rtl8192ce_prepare_bcn_tasklet(void *priv);
void rtl8192ce_set_intf_ops(struct _io_ops *pops);
#endif
#ifdef CONFIG_RTL8192D
u32 rtl8192de_init_desc_ring(_adapter * padapter);
u32 rtl8192de_free_desc_ring(_adapter * padapter);
void rtl8192de_reset_desc_ring(_adapter * padapter);
int rtl8192de_interrupt(PADAPTER Adapter);
void rtl8192de_xmit_tasklet(void *priv);
void rtl8192de_recv_tasklet(void *priv);
void rtl8192de_prepare_bcn_tasklet(void *priv);
void rtl8192de_set_intf_ops(struct _io_ops *pops);
u32 MpReadPCIDwordDBI8192D(IN PADAPTER Adapter, IN u16 Offset, IN u8 Direct);
void MpWritePCIDwordDBI8192D(IN PADAPTER Adapter, IN u16 Offset, IN u32 Value, IN u8 Direct);
#endif
#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
u32 rtl8812ae_init_desc_ring(_adapter * padapter);
u32 rtl8812ae_free_desc_ring(_adapter * padapter);
void rtl8812ae_reset_desc_ring(_adapter * padapter);
u32 rtl8812ae_init_desc_ring(_adapter *padapter);
u32 rtl8812ae_free_desc_ring(_adapter *padapter);
void rtl8812ae_reset_desc_ring(_adapter *padapter);
int rtl8812ae_interrupt(PADAPTER Adapter);
void rtl8812ae_xmit_tasklet(void *priv);
void rtl8812ae_recv_tasklet(void *priv);
@@ -69,9 +44,9 @@ void rtl8812ae_set_intf_ops(struct _io_ops *pops);
#endif
#ifdef CONFIG_RTL8192E
u32 rtl8192ee_init_desc_ring(_adapter * padapter);
u32 rtl8192ee_free_desc_ring(_adapter * padapter);
void rtl8192ee_reset_desc_ring(_adapter * padapter);
u32 rtl8192ee_init_desc_ring(_adapter *padapter);
u32 rtl8192ee_free_desc_ring(_adapter *padapter);
void rtl8192ee_reset_desc_ring(_adapter *padapter);
void rtl8192ee_recv_tasklet(void *priv);
void rtl8192ee_prepare_bcn_tasklet(void *priv);
int rtl8192ee_interrupt(PADAPTER Adapter);
@@ -79,14 +54,25 @@ void rtl8192ee_set_intf_ops(struct _io_ops *pops);
#endif
#ifdef CONFIG_RTL8723B
u32 rtl8723be_init_desc_ring(_adapter * padapter);
u32 rtl8723be_free_desc_ring(_adapter * padapter);
void rtl8723be_reset_desc_ring(_adapter * padapter);
u32 rtl8723be_init_desc_ring(_adapter *padapter);
u32 rtl8723be_free_desc_ring(_adapter *padapter);
void rtl8723be_reset_desc_ring(_adapter *padapter);
int rtl8723be_interrupt(PADAPTER Adapter);
void rtl8723be_recv_tasklet(void *priv);
void rtl8723be_prepare_bcn_tasklet(void *priv);
void rtl8723be_set_intf_ops(struct _io_ops *pops);
#endif
#ifdef CONFIG_RTL8814A
u32 rtl8814ae_init_desc_ring(_adapter *padapter);
u32 rtl8814ae_free_desc_ring(_adapter *padapter);
void rtl8814ae_reset_desc_ring(_adapter *padapter);
int rtl8814ae_interrupt(PADAPTER Adapter);
void rtl8814ae_xmit_tasklet(void *priv);
void rtl8814ae_recv_tasklet(void *priv);
void rtl8814ae_prepare_bcn_tasklet(void *priv);
void rtl8814ae_set_intf_ops(struct _io_ops *pops);
#endif
#endif

6
include/recv_osdep.h
View File

@@ -29,8 +29,12 @@ extern s32 rtw_recv_entry(union recv_frame *precv_frame);
extern int rtw_recv_indicatepkt(_adapter *adapter, union recv_frame *precv_frame);
extern void rtw_recv_returnpacket(IN _nic_hdl cnxt, IN _pkt *preturnedpkt);
extern int rtw_recv_monitor(_adapter *padapter, union recv_frame *precv_frame);
extern void rtw_hostapd_mlme_rx(_adapter *padapter, union recv_frame *precv_frame);
extern void rtw_handle_tkip_mic_err(_adapter *padapter,u8 bgroup);
struct sta_info;
extern void rtw_handle_tkip_mic_err(_adapter *padapter, struct sta_info *sta, u8 bgroup);
int rtw_init_recv_priv(struct recv_priv *precvpriv, _adapter *padapter);

74
include/rtl8188e_cmd.h
View File

@@ -142,10 +142,11 @@ typedef struct _RSVDPAGE_LOC_88E {
void rtl8188e_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode);
void rtl8188e_set_FwJoinBssReport_cmd(PADAPTER padapter, u8 mstatus);
u8 rtl8188e_set_rssi_cmd(PADAPTER padapter, u8 *param);
u8 rtl8188e_set_raid_cmd(_adapter*padapter, u32 bitmap, u8* arg);
void rtl8188e_Add_RateATid(PADAPTER padapter, u32 bitmap, u8* arg, u8 rssi_level);
u8 rtl8188e_set_raid_cmd(_adapter *padapter, u32 bitmap, u8 *arg);
void rtl8188e_Add_RateATid(PADAPTER padapter, u64 rate_bitmap, u8 *arg, u8 rssi_level);
s32 FillH2CCmd_88E(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
//u8 rtl8192c_set_FwSelectSuspend_cmd(PADAPTER padapter, u8 bfwpoll, u16 period);
u8 GetTxBufferRsvdPageNum8188E(_adapter *padapter, bool wowlan);
#ifdef CONFIG_P2P
@@ -153,7 +154,6 @@ void rtl8188e_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);
#endif //CONFIG_P2P
void CheckFwRsvdPageContent(PADAPTER padapter);
void rtl8188e_set_FwMediaStatus_cmd(PADAPTER padapter, u16 mstatus_rpt );
#ifdef CONFIG_TSF_RESET_OFFLOAD
//u8 rtl8188e_reset_tsf(_adapter *padapter, u8 reset_port);
@@ -163,74 +163,6 @@ int reset_tsf(PADAPTER Adapter, u8 reset_port );
//#define H2C_8188E_RSVDPAGE_LOC_LEN 5
//#define H2C_8188E_AOAC_RSVDPAGE_LOC_LEN 7
#ifdef CONFIG_WOWLAN
typedef struct _SETWOWLAN_PARM{
u8 mode;
u8 gpio_index;
u8 gpio_duration;
u8 second_mode;
u8 reserve;
}SETWOWLAN_PARM, *PSETWOWLAN_PARM;
typedef struct _SETAOAC_GLOBAL_INFO{
u8 pairwiseEncAlg;
u8 groupEncAlg;
}SETAOAC_GLOBAL_INFO, *PSETAOAC_GLOBAL_INFO;
/* move to hal_com_h2c.h
#define eqMacAddr(a,b) ( ((a)[0]==(b)[0] && (a)[1]==(b)[1] && (a)[2]==(b)[2] && (a)[3]==(b)[3] && (a)[4]==(b)[4] && (a)[5]==(b)[5]) ? 1:0 )
#define cpMacAddr(des,src) ((des)[0]=(src)[0],(des)[1]=(src)[1],(des)[2]=(src)[2],(des)[3]=(src)[3],(des)[4]=(src)[4],(des)[5]=(src)[5])
#define cpIpAddr(des,src) ((des)[0]=(src)[0],(des)[1]=(src)[1],(des)[2]=(src)[2],(des)[3]=(src)[3])
//
// ARP packet
//
// LLC Header
#define GET_ARP_PKT_LLC_TYPE(__pHeader) ReadEF2Byte( ((u8*)(__pHeader)) + 6)
//ARP element
#define GET_ARP_PKT_OPERATION(__pHeader) ReadEF2Byte( ((u8*)(__pHeader)) + 6)
#define GET_ARP_PKT_SENDER_MAC_ADDR(__pHeader, _val) cpMacAddr((u8*)(_val), ((u8*)(__pHeader))+8)
#define GET_ARP_PKT_SENDER_IP_ADDR(__pHeader, _val) cpIpAddr((u8*)(_val), ((u8*)(__pHeader))+14)
#define GET_ARP_PKT_TARGET_MAC_ADDR(__pHeader, _val) cpMacAddr((u8*)(_val), ((u8*)(__pHeader))+18)
#define SET_ARP_PKT_HW(__pHeader, __Value) WriteEF2Byte( ((u8*)(__pHeader)) + 0, __Value)
#define SET_ARP_PKT_PROTOCOL(__pHeader, __Value) WriteEF2Byte( ((u8*)(__pHeader)) + 2, __Value)
#define SET_ARP_PKT_HW_ADDR_LEN(__pHeader, __Value) WriteEF1Byte( ((u8*)(__pHeader)) + 4, __Value)
#define SET_ARP_PKT_PROTOCOL_ADDR_LEN(__pHeader, __Value) WriteEF1Byte( ((u8*)(__pHeader)) + 5, __Value)
#define SET_ARP_PKT_OPERATION(__pHeader, __Value) WriteEF2Byte( ((u8*)(__pHeader)) + 6, __Value)
#define SET_ARP_PKT_SENDER_MAC_ADDR(__pHeader, _val) cpMacAddr(((u8*)(__pHeader))+8, (u8*)(_val))
#define SET_ARP_PKT_SENDER_IP_ADDR(__pHeader, _val) cpIpAddr(((u8*)(__pHeader))+14, (u8*)(_val))
#define SET_ARP_PKT_TARGET_MAC_ADDR(__pHeader, _val) cpMacAddr(((u8*)(__pHeader))+18, (u8*)(_val))
#define SET_ARP_PKT_TARGET_IP_ADDR(__pHeader, _val) cpIpAddr(((u8*)(__pHeader))+24, (u8*)(_val))
#define FW_WOWLAN_FUN_EN BIT(0)
#define FW_WOWLAN_PATTERN_MATCH BIT(1)
#define FW_WOWLAN_MAGIC_PKT BIT(2)
#define FW_WOWLAN_UNICAST BIT(3)
#define FW_WOWLAN_ALL_PKT_DROP BIT(4)
#define FW_WOWLAN_GPIO_ACTIVE BIT(5)
#define FW_WOWLAN_REKEY_WAKEUP BIT(6)
#define FW_WOWLAN_DEAUTH_WAKEUP BIT(7)
#define FW_WOWLAN_GPIO_WAKEUP_EN BIT(0)
#define FW_FW_PARSE_MAGIC_PKT BIT(1)
#define FW_WOWLAN_KEEP_ALIVE_EN BIT(0)
#define FW_WOWLAN_KEEP_ALIVE_PKT_TYPE BIT(2)
#define FW_REMOTE_WAKE_CTRL_EN BIT(0)
#define FW_ARP_EN BIT(1)
#define FW_REALWOWLAN_EN BIT(5)
#define FW_WOW_FW_UNICAST_EN BIT(7)
#define FW_ADOPT_USER BIT(1)
*/
void rtl8188es_set_wowlan_cmd(_adapter* padapter, u8 enable);
void SetFwRelatedForWoWLAN8188ES(_adapter* padapter, u8 bHostIsGoingtoSleep);
#endif//CONFIG_WOWLAN
//---------------------------------------------------------------------------------------------------------//
//---------------------------------- H2C CMD CONTENT --------------------------------------------------//
//---------------------------------------------------------------------------------------------------------//

4
include/rtl8188e_dm.h
View File

@@ -29,9 +29,5 @@ void rtl8188e_HalDmWatchDog(IN PADAPTER Adapter);
//void rtl8192c_dm_RF_Saving(IN PADAPTER pAdapter, IN u8 bForceInNormal);
#ifdef CONFIG_ANTENNA_DIVERSITY
void AntDivCompare8188E(PADAPTER Adapter, WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src);
u8 AntDivBeforeLink8188E(PADAPTER Adapter );
#endif
#endif

58
include/rtl8188e_hal.h
View File

@@ -21,11 +21,7 @@
#define __RTL8188E_HAL_H__
//#include "hal_com.h"
#if 1
#include "hal_data.h"
#else
#include "../hal/OUTSRC/odm_precomp.h"
#endif
//include HAL Related header after HAL Related compiling flags
#include "rtl8188e_spec.h"
@@ -143,11 +139,19 @@ typedef struct _RT_8188E_FIRMWARE_HDR
//#define MAX_RX_DMA_BUFFER_SIZE_88E 0x2400 //9k for 88E nornal chip , //MaxRxBuff=10k-max(TxReportSize(64*8), WOLPattern(16*24))
#define MAX_RX_DMA_BUFFER_SIZE_88E(__Adapter) ((!IS_VENDOR_8188E_I_CUT_SERIES(__Adapter))?0x2400:0x3C00)
#define RX_DMA_SIZE_88E(__Adapter) ((!IS_VENDOR_8188E_I_CUT_SERIES(__Adapter))?0x2800:0x4000)
#ifdef CONFIG_WOWLAN
#define RESV_FMWF WKFMCAM_SIZE*MAX_WKFM_NUM /* 16 entries, for each is 24 bytes*/
#else
#define RESV_FMWF 0
#endif
#define MAX_TX_REPORT_BUFFER_SIZE 0x0400 // 1k
#define RX_DMA_RESERVD_FW_FEATURE 0x200 /* for tx report (64*8) */
#define MAX_RX_DMA_BUFFER_SIZE_88E(__Adapter) RX_DMA_SIZE_88E(__Adapter)-RX_DMA_RESERVD_FW_FEATURE
#define MAX_TX_REPORT_BUFFER_SIZE 0x0400 /* 1k */
// Note: We will divide number of page equally for each queue other than public queue!
// 22k = 22528 bytes = 176 pages (@page = 128 bytes)
@@ -163,17 +167,23 @@ typedef struct _RT_8188E_FIRMWARE_HDR
#define WOWLAN_PAGE_NUM_88E 0x00
#endif
#define TX_TOTAL_PAGE_NUMBER_88E(_Adapter) ( (IS_VENDOR_8188E_I_CUT_SERIES(_Adapter)?0x100:0xB0) - BCNQ_PAGE_NUM_88E - WOWLAN_PAGE_NUM_88E)
#define TX_PAGE_BOUNDARY_88E(_Adapter) (TX_TOTAL_PAGE_NUMBER_88E(_Adapter) + 1)
/* Note:
Tx FIFO Size : previous CUT:22K /I_CUT after:32KB
Tx page Size : 128B
Total page numbers : 176(0xB0) / 256(0x100)
*/
#define TOTAL_PAGE_NUMBER_88E(_Adapter) ((IS_VENDOR_8188E_I_CUT_SERIES(_Adapter)?0x100:0xB0) - 1)/* must reserved 1 page for dma issue */
#define TX_TOTAL_PAGE_NUMBER_88E(_Adapter) (TOTAL_PAGE_NUMBER_88E(_Adapter) - BCNQ_PAGE_NUM_88E - WOWLAN_PAGE_NUM_88E)
#define TX_PAGE_BOUNDARY_88E(_Adapter) (TX_TOTAL_PAGE_NUMBER_88E(_Adapter) + 1) /* beacon header start address */
#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_88E(_Adapter) TX_TOTAL_PAGE_NUMBER_88E(_Adapter)
#define WMM_NORMAL_TX_PAGE_BOUNDARY_88E(_Adapter) (WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_88E(_Adapter) + 1)
// For Normal Chip Setting
// (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8723B
#define NORMAL_PAGE_NUM_HPQ_88E 0x10
#define NORMAL_PAGE_NUM_LPQ_88E 0x10
#define NORMAL_PAGE_NUM_NPQ_88E 0x10
#define NORMAL_PAGE_NUM_HPQ_88E 0x0
#define NORMAL_PAGE_NUM_LPQ_88E 0x09
#define NORMAL_PAGE_NUM_NPQ_88E 0x0
// Note: For Normal Chip Setting, modify later
#define WMM_NORMAL_PAGE_NUM_HPQ_88E 0x29
@@ -241,6 +251,17 @@ typedef struct _RT_8188E_FIRMWARE_HDR
//#define RT_IS_FUNC_DISABLED(__pAdapter, __FuncBits) ( (__pAdapter)->DisabledFunctions & (__FuncBits) )
#ifdef CONFIG_PCI_HCI
/* according to the define in the rtw_xmit.h, rtw_recv.h */
#define TX_DESC_NUM_8188EE TXDESC_NUM /* 128 */
#ifdef CONFIG_CONCURRENT_MODE
/*#define BE_QUEUE_TX_DESC_NUM_8188EE (TXDESC_NUM<<1)*/ /* 256 */
#define BE_QUEUE_TX_DESC_NUM_8188EE ((TXDESC_NUM<<1)+(TXDESC_NUM>>1)) /* 320 */
/*#define BE_QUEUE_TX_DESC_NUM_8188EE ((TXDESC_NUM<<1)+TXDESC_NUM)*/ /* 384 */
#else
#define BE_QUEUE_TX_DESC_NUM_8188EE TXDESC_NUM /* 128 */
/*#define BE_QUEUE_TX_DESC_NUM_8188EE (TXDESC_NUM+(TXDESC_NUM>>1)) *//* 192 */
#endif
void InterruptRecognized8188EE(PADAPTER Adapter, PRT_ISR_CONTENT pIsrContent);
void UpdateInterruptMask8188EE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
#endif //CONFIG_PCI_HCI
@@ -268,24 +289,25 @@ void Hal_ReadThermalMeter_88E(PADAPTER Adapter,u8* PROMContent,BOOLEAN Autoload
void Hal_EfuseParseXtal_8188E(PADAPTER pAdapter,u8* hwinfo,BOOLEAN AutoLoadFail);
void Hal_EfuseParseBoardType88E(PADAPTER pAdapter,u8* hwinfo,BOOLEAN AutoLoadFail);
void Hal_ReadPowerSavingMode88E(PADAPTER pAdapter,u8* hwinfo,BOOLEAN AutoLoadFail);
void Hal_ReadPAType_8188E(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
void Hal_ReadAmplifierType_8188E(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
void Hal_ReadRFEType_8188E(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
BOOLEAN HalDetectPwrDownMode88E(PADAPTER Adapter);
#ifdef CONFIG_WOWLAN
#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
void Hal_DetectWoWMode(PADAPTER pAdapter);
#endif //CONFIG_WOWLAN
//RT_CHANNEL_DOMAIN rtl8723a_HalMapChannelPlan(PADAPTER padapter, u8 HalChannelPlan);
//VERSION_8192C rtl8723a_ReadChipVersion(PADAPTER padapter);
//void rtl8723a_ReadBluetoothCoexistInfo(PADAPTER padapter, u8 *PROMContent, BOOLEAN AutoloadFail);
void Hal_InitChannelPlan(PADAPTER padapter);
#ifdef CONFIG_RF_GAIN_OFFSET
#ifdef CONFIG_RF_POWER_TRIM
void Hal_ReadRFGainOffset(PADAPTER pAdapter,u8* hwinfo,BOOLEAN AutoLoadFail);
#endif //CONFIG_RF_GAIN_OFFSET
#endif /*CONFIG_RF_POWER_TRIM*/
void rtl8188e_init_default_value(_adapter *adapter);
void rtl8188e_set_hal_ops(struct hal_ops *pHalFunc);
void init_hal_spec_8188e(_adapter *adapter);
// register
void SetBcnCtrlReg(PADAPTER padapter, u8 SetBits, u8 ClearBits);

52
include/rtl8188e_recv.h
View File

@@ -20,7 +20,48 @@
#ifndef __RTL8188E_RECV_H__
#define __RTL8188E_RECV_H__
#include <rtl8192c_recv.h>
#define RECV_BLK_SZ 512
#define RECV_BLK_CNT 16
#define RECV_BLK_TH RECV_BLK_CNT
#if defined(CONFIG_USB_HCI)
#ifndef MAX_RECVBUF_SZ
#ifdef PLATFORM_OS_CE
#define MAX_RECVBUF_SZ (8192+1024) // 8K+1k
#else
#ifndef CONFIG_MINIMAL_MEMORY_USAGE
//#define MAX_RECVBUF_SZ (32768) // 32k
//#define MAX_RECVBUF_SZ (16384) //16K
//#define MAX_RECVBUF_SZ (10240) //10K
#ifdef CONFIG_PLATFORM_MSTAR
#define MAX_RECVBUF_SZ (8192) // 8K
#else
#define MAX_RECVBUF_SZ (15360) // 15k < 16k
#endif
//#define MAX_RECVBUF_SZ (8192+1024) // 8K+1k
#else
#define MAX_RECVBUF_SZ (4000) // about 4K
#endif
#endif
#endif //!MAX_RECVBUF_SZ
#elif defined(CONFIG_PCI_HCI)
//#ifndef CONFIG_MINIMAL_MEMORY_USAGE
// #define MAX_RECVBUF_SZ (9100)
//#else
#define MAX_RECVBUF_SZ (4000) // about 4K
//#endif
#elif defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
#define MAX_RECVBUF_SZ (10240)
#endif
// Rx smooth factor
#define Rx_Smooth_Factor (20)
#define TX_RPT1_PKT_LEN 8
@@ -116,13 +157,11 @@ void rtl8188es_recv_hdl(PADAPTER padapter, struct recv_buf *precvbuf);
#endif
#ifdef CONFIG_USB_HCI
#define INTERRUPT_MSG_FORMAT_LEN 60
void rtl8188eu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf);
s32 rtl8188eu_init_recv_priv(PADAPTER padapter);
void rtl8188eu_free_recv_priv(PADAPTER padapter);
void rtl8188eu_recv_hdl(PADAPTER padapter, struct recv_buf *precvbuf);
void rtl8188eu_recv_tasklet(void *priv);
#endif
#ifdef CONFIG_PCI_HCI
@@ -130,10 +169,7 @@ s32 rtl8188ee_init_recv_priv(PADAPTER padapter);
void rtl8188ee_free_recv_priv(PADAPTER padapter);
#endif
void rtl8188e_query_rx_phy_status(union recv_frame *prframe, struct phy_stat *pphy_stat);
void rtl8188e_process_phy_info(PADAPTER padapter, void *prframe);
void update_recvframe_phyinfo_88e(union recv_frame *precvframe,struct phy_stat *pphy_status);
void update_recvframe_attrib_88e( union recv_frame *precvframe, struct recv_stat *prxstat);
void rtl8188e_query_rx_desc_status(union recv_frame *precvframe, struct recv_stat *prxstat);
#endif
#endif /* __RTL8188E_RECV_H__ */

10
include/rtl8188e_spec.h
View File

@@ -101,11 +101,11 @@
// 0x0600h ~ 0x07FFh WMAC Configuration
//
//-----------------------------------------------------
#ifdef CONFIG_RF_GAIN_OFFSET
#ifdef CONFIG_RF_POWER_TRIM
#define EEPROM_RF_GAIN_OFFSET 0xC1
#define EEPROM_RF_GAIN_VAL 0xF6
#define EEPROM_THERMAL_OFFSET 0xF5
#endif //CONFIG_RF_GAIN_OFFSET
#endif /*CONFIG_RF_POWER_TRIM*/
//----------------------------------------------------------------------------
// 88E Driver Initialization Offload REG_FDHM0(Offset 0x88, 8 bits)
//----------------------------------------------------------------------------
@@ -148,7 +148,11 @@
//========================================================
#define MACID_NUM_88E 64
#define CAM_ENTRY_NUM_88E 32
#define SEC_CAM_ENT_NUM_88E 32
#define NSS_NUM_88E 1
#define BAND_CAP_88E (BAND_CAP_2G)
#define BW_CAP_88E (BW_CAP_20M | BW_CAP_40M)
#define PROTO_CAP_88E (PROTO_CAP_11B|PROTO_CAP_11G|PROTO_CAP_11N)
//----------------------------------------------------------------------------
// 8192C EEPROM/EFUSE share register definition.

2
include/rtl8188e_xmit.h
View File

@@ -243,6 +243,8 @@ struct txrpt_ccx_88e {
void rtl8188e_fill_fake_txdesc(PADAPTER padapter,u8*pDesc,u32 BufferLen,
u8 IsPsPoll,u8 IsBTQosNull, u8 bDataFrame);
void rtl8188e_cal_txdesc_chksum(struct tx_desc *ptxdesc);
#if defined(CONFIG_SDIO_HCI)||defined (CONFIG_GSPI_HCI)
s32 rtl8188es_init_xmit_priv(PADAPTER padapter);
void rtl8188es_free_xmit_priv(PADAPTER padapter);

221
include/rtl8188f_cmd.h Normal file
View File

@@ -0,0 +1,221 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTL8188F_CMD_H__
#define __RTL8188F_CMD_H__
//---------------------------------------------------------------------------------------------------------//
//---------------------------------- H2C CMD DEFINITION ------------------------------------------------//
//---------------------------------------------------------------------------------------------------------//
enum h2c_cmd_8188F{
//Common Class: 000
H2C_8188F_RSVD_PAGE = 0x00,
H2C_8188F_MEDIA_STATUS_RPT = 0x01,
H2C_8188F_SCAN_ENABLE = 0x02,
H2C_8188F_KEEP_ALIVE = 0x03,
H2C_8188F_DISCON_DECISION = 0x04,
H2C_8188F_PSD_OFFLOAD = 0x05,
H2C_8188F_AP_OFFLOAD = 0x08,
H2C_8188F_BCN_RSVDPAGE = 0x09,
H2C_8188F_PROBERSP_RSVDPAGE = 0x0A,
H2C_8188F_FCS_RSVDPAGE = 0x10,
H2C_8188F_FCS_INFO = 0x11,
H2C_8188F_AP_WOW_GPIO_CTRL = 0x13,
//PoweSave Class: 001
H2C_8188F_SET_PWR_MODE = 0x20,
H2C_8188F_PS_TUNING_PARA = 0x21,
H2C_8188F_PS_TUNING_PARA2 = 0x22,
H2C_8188F_P2P_LPS_PARAM = 0x23,
H2C_8188F_P2P_PS_OFFLOAD = 0x24,
H2C_8188F_PS_SCAN_ENABLE = 0x25,
H2C_8188F_SAP_PS_ = 0x26,
H2C_8188F_INACTIVE_PS_ = 0x27, //Inactive_PS
H2C_8188F_FWLPS_IN_IPS_ = 0x28,
//Dynamic Mechanism Class: 010
H2C_8188F_MACID_CFG = 0x40,
H2C_8188F_TXBF = 0x41,
H2C_8188F_RSSI_SETTING = 0x42,
H2C_8188F_AP_REQ_TXRPT = 0x43,
H2C_8188F_INIT_RATE_COLLECT = 0x44,
H2C_8188F_RA_PARA_ADJUST = 0x46,
//BT Class: 011
H2C_8188F_B_TYPE_TDMA = 0x60,
H2C_8188F_BT_INFO = 0x61,
H2C_8188F_FORCE_BT_TXPWR = 0x62,
H2C_8188F_BT_IGNORE_WLANACT = 0x63,
H2C_8188F_DAC_SWING_VALUE = 0x64,
H2C_8188F_ANT_SEL_RSV = 0x65,
H2C_8188F_WL_OPMODE = 0x66,
H2C_8188F_BT_MP_OPER = 0x67,
H2C_8188F_BT_CONTROL = 0x68,
H2C_8188F_BT_WIFI_CTRL = 0x69,
H2C_8188F_BT_FW_PATCH = 0x6A,
H2C_8188F_BT_WLAN_CALIBRATION = 0x6D,
//WOWLAN Class: 100
H2C_8188F_WOWLAN = 0x80,
H2C_8188F_REMOTE_WAKE_CTRL = 0x81,
H2C_8188F_AOAC_GLOBAL_INFO = 0x82,
H2C_8188F_AOAC_RSVD_PAGE = 0x83,
H2C_8188F_AOAC_RSVD_PAGE2 = 0x84,
H2C_8188F_D0_SCAN_OFFLOAD_CTRL = 0x85,
H2C_8188F_D0_SCAN_OFFLOAD_INFO = 0x86,
H2C_8188F_CHNL_SWITCH_OFFLOAD = 0x87,
H2C_8188F_P2P_OFFLOAD_RSVD_PAGE = 0x8A,
H2C_8188F_P2P_OFFLOAD = 0x8B,
H2C_8188F_RESET_TSF = 0xC0,
H2C_8188F_MAXID,
};
//---------------------------------------------------------------------------------------------------------//
//---------------------------------- H2C CMD CONTENT --------------------------------------------------//
//---------------------------------------------------------------------------------------------------------//
//_RSVDPAGE_LOC_CMD_0x00
#define SET_8188F_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
#define SET_8188F_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
#define SET_8188F_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
#define SET_8188F_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
#define SET_8188F_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
//_KEEP_ALIVE_CMD_0x03
#define SET_8188F_H2CCMD_KEEPALIVE_PARM_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
#define SET_8188F_H2CCMD_KEEPALIVE_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
#define SET_8188F_H2CCMD_KEEPALIVE_PARM_PKT_TYPE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
#define SET_8188F_H2CCMD_KEEPALIVE_PARM_CHECK_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
//_DISCONNECT_DECISION_CMD_0x04
#define SET_8188F_H2CCMD_DISCONDECISION_PARM_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
#define SET_8188F_H2CCMD_DISCONDECISION_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
#define SET_8188F_H2CCMD_DISCONDECISION_PARM_CHECK_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
#define SET_8188F_H2CCMD_DISCONDECISION_PARM_TRY_PKT_NUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
// _PWR_MOD_CMD_0x20
#define SET_8188F_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
#define SET_8188F_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value)
#define SET_8188F_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value)
#define SET_8188F_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
#define SET_8188F_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
#define SET_8188F_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value)
#define SET_8188F_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
#define SET_8188F_H2CCMD_PWRMODE_PARM_BYTE5(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)
#define GET_8188F_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd) LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)
// _PS_TUNE_PARAM_CMD_0x21
#define SET_8188F_H2CCMD_PSTUNE_PARM_BCN_TO_LIMIT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
#define SET_8188F_H2CCMD_PSTUNE_PARM_DTIM_TIMEOUT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
#define SET_8188F_H2CCMD_PSTUNE_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 1, __Value)
#define SET_8188F_H2CCMD_PSTUNE_PARM_PS_TIMEOUT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 1, 7, __Value)
#define SET_8188F_H2CCMD_PSTUNE_PARM_DTIM_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
//_MACID_CFG_CMD_0x40
#define SET_8188F_H2CCMD_MACID_CFG_MACID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
#define SET_8188F_H2CCMD_MACID_CFG_RAID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 5, __Value)
#define SET_8188F_H2CCMD_MACID_CFG_SGI_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 7, 1, __Value)
#define SET_8188F_H2CCMD_MACID_CFG_BW(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 2, __Value)
#define SET_8188F_H2CCMD_MACID_CFG_NO_UPDATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 3, 1, __Value)
#define SET_8188F_H2CCMD_MACID_CFG_VHT_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 4, 2, __Value)
#define SET_8188F_H2CCMD_MACID_CFG_DISPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 6, 1, __Value)
#define SET_8188F_H2CCMD_MACID_CFG_DISRA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 7, 1, __Value)
#define SET_8188F_H2CCMD_MACID_CFG_RATE_MASK0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
#define SET_8188F_H2CCMD_MACID_CFG_RATE_MASK1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
#define SET_8188F_H2CCMD_MACID_CFG_RATE_MASK2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+5, 0, 8, __Value)
#define SET_8188F_H2CCMD_MACID_CFG_RATE_MASK3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+6, 0, 8, __Value)
//_RSSI_SETTING_CMD_0x42
#define SET_8188F_H2CCMD_RSSI_SETTING_MACID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
#define SET_8188F_H2CCMD_RSSI_SETTING_RSSI(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 7, __Value)
#define SET_8188F_H2CCMD_RSSI_SETTING_ULDL_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
// _AP_REQ_TXRPT_CMD_0x43
#define SET_8188F_H2CCMD_APREQRPT_PARM_MACID1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
#define SET_8188F_H2CCMD_APREQRPT_PARM_MACID2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
// _FORCE_BT_TXPWR_CMD_0x62
#define SET_8188F_H2CCMD_BT_PWR_IDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
// _FORCE_BT_MP_OPER_CMD_0x67
#define SET_8188F_H2CCMD_BT_MPOPER_VER(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)
#define SET_8188F_H2CCMD_BT_MPOPER_REQNUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value)
#define SET_8188F_H2CCMD_BT_MPOPER_IDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
#define SET_8188F_H2CCMD_BT_MPOPER_PARAM1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
#define SET_8188F_H2CCMD_BT_MPOPER_PARAM2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
#define SET_8188F_H2CCMD_BT_MPOPER_PARAM3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
// _BT_FW_PATCH_0x6A
#define SET_8188F_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value) SET_BITS_TO_LE_2BYTE((pu1Byte)(__pH2CCmd), 0, 16, __Value)
#define SET_8188F_H2CCMD_BT_FW_PATCH_ADDR0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
#define SET_8188F_H2CCMD_BT_FW_PATCH_ADDR1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
#define SET_8188F_H2CCMD_BT_FW_PATCH_ADDR2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
#define SET_8188F_H2CCMD_BT_FW_PATCH_ADDR3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)
//---------------------------------------------------------------------------------------------------------//
//------------------------------------------- Structure --------------------------------------------------//
//---------------------------------------------------------------------------------------------------------//
//---------------------------------------------------------------------------------------------------------//
//---------------------------------- Function Statement --------------------------------------------------//
//---------------------------------------------------------------------------------------------------------//
// host message to firmware cmd
void rtl8188f_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode);
void rtl8188f_set_FwJoinBssRpt_cmd(PADAPTER padapter, u8 mstatus);
void rtl8188f_set_rssi_cmd(PADAPTER padapter, u8 *param);
void rtl8188f_Add_RateATid(PADAPTER pAdapter, u64 bitmap, u8* arg, u8 rssi_level);
void rtl8188f_fw_try_ap_cmd(PADAPTER padapter, u32 need_ack);
//s32 rtl8188f_set_lowpwr_lps_cmd(PADAPTER padapter, u8 enable);
void rtl8188f_set_FwPsTuneParam_cmd(PADAPTER padapter);
void rtl8188f_set_FwMacIdConfig_cmd(_adapter* padapter, u8 mac_id, u8 raid, u8 bw, u8 sgi, u32 mask);
void rtl8188f_set_FwBtMpOper_cmd(PADAPTER padapter, u8 idx, u8 ver, u8 reqnum, u8 *param);
void rtl8188f_download_rsvd_page(PADAPTER padapter, u8 mstatus);
#ifdef CONFIG_BT_COEXIST
void rtl8188f_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter);
#endif // CONFIG_BT_COEXIST
#ifdef CONFIG_P2P
void rtl8188f_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);
#endif //CONFIG_P2P
void CheckFwRsvdPageContent(PADAPTER padapter);
#ifdef CONFIG_TDLS
#ifdef CONFIG_TDLS_CH_SW
void rtl8188f_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable);
#endif
#endif
#ifdef CONFIG_P2P_WOWLAN
void rtl8188f_set_p2p_wowlan_offload_cmd(PADAPTER padapter);
#endif
void rtl8188f_set_FwPwrModeInIPS_cmd(PADAPTER padapter, u8 cmd_param);
#ifdef CONFIG_TSF_RESET_OFFLOAD
u8 rtl8188f_reset_tsf(_adapter *padapter, u8 reset_port);
#endif // CONFIG_TSF_RESET_OFFLOAD
s32 FillH2CCmd8188F(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
u8 GetTxBufferRsvdPageNum8188F(_adapter *padapter, bool wowlan);
#endif

18
include/rtl8723a_dm.h → include/rtl8188f_dm.h
View File

@@ -17,12 +17,12 @@
*
*
******************************************************************************/
#ifndef __RTL8723A_DM_H__
#define __RTL8723A_DM_H__
#ifndef __RTL8188F_DM_H__
#define __RTL8188F_DM_H__
//============================================================
// Description:
//
// This file is for 8723A dynamic mechanism only
// This file is for 8188F dynamic mechanism only
//
//
//============================================================
@@ -30,16 +30,18 @@
//============================================================
// structure and define
//============================================================
//============================================================
// function prototype
//============================================================
void rtl8723a_init_dm_priv(PADAPTER padapter);
void rtl8723a_deinit_dm_priv(PADAPTER padapter);
void rtl8723a_InitHalDm(PADAPTER padapter);
void rtl8723a_HalDmWatchDog(PADAPTER padapter);
void rtl8188f_init_dm_priv(PADAPTER padapter);
void rtl8188f_deinit_dm_priv(PADAPTER padapter);
void rtl8188f_InitHalDm(PADAPTER padapter);
void rtl8188f_HalDmWatchDog(PADAPTER padapter);
void rtl8188f_HalDmWatchDog_in_LPS(PADAPTER padapter);
void rtl8188f_hal_dm_in_lps(PADAPTER padapter);
#endif

321
include/rtl8188f_hal.h Normal file
View File

@@ -0,0 +1,321 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTL8188F_HAL_H__
#define __RTL8188F_HAL_H__
#include "hal_data.h"
#include "rtl8188f_spec.h"
#include "rtl8188f_rf.h"
#include "rtl8188f_dm.h"
#include "rtl8188f_recv.h"
#include "rtl8188f_xmit.h"
#include "rtl8188f_cmd.h"
#include "rtl8188f_led.h"
#include "Hal8188FPwrSeq.h"
#include "Hal8188FPhyReg.h"
#include "Hal8188FPhyCfg.h"
#ifdef DBG_CONFIG_ERROR_DETECT
#include "rtl8188f_sreset.h"
#endif
//---------------------------------------------------------------------
// RTL8188F From file
//---------------------------------------------------------------------
#define RTL8188F_FW_IMG "rtl8188f/FW_NIC.bin"
#define RTL8188F_FW_WW_IMG "rtl8188f/FW_WoWLAN.bin"
#define RTL8188F_PHY_REG "rtl8188f/PHY_REG.txt"
#define RTL8188F_PHY_RADIO_A "rtl8188f/RadioA.txt"
#define RTL8188F_PHY_RADIO_B "rtl8188f/RadioB.txt"
#define RTL8188F_TXPWR_TRACK "rtl8188f/TxPowerTrack.txt"
#define RTL8188F_AGC_TAB "rtl8188f/AGC_TAB.txt"
#define RTL8188F_PHY_MACREG "rtl8188f/MAC_REG.txt"
#define RTL8188F_PHY_REG_PG "rtl8188f/PHY_REG_PG.txt"
#define RTL8188F_PHY_REG_MP "rtl8188f/PHY_REG_MP.txt"
#define RTL8188F_TXPWR_LMT "rtl8188f/TXPWR_LMT.txt"
//---------------------------------------------------------------------
// RTL8188F From header
//---------------------------------------------------------------------
#if MP_DRIVER == 1
#define Rtl8188F_FwBTImgArray Rtl8188FFwBTImgArray
#define Rtl8188F_FwBTImgArrayLength Rtl8188FFwBTImgArrayLength
#define Rtl8188F_FwMPImageArray Rtl8188FFwMPImgArray
#define Rtl8188F_FwMPImgArrayLength Rtl8188FMPImgArrayLength
#define Rtl8188F_PHY_REG_Array_MP Rtl8188F_PHYREG_Array_MP
#define Rtl8188F_PHY_REG_Array_MPLength Rtl8188F_PHYREG_Array_MPLength
#endif
#define FW_8188F_SIZE 0x8000
#define FW_8188F_START_ADDRESS 0x1000
#define FW_8188F_END_ADDRESS 0x1FFF //0x5FFF
#define IS_FW_HEADER_EXIST_8188F(_pFwHdr) ((le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x88F0)
typedef struct _RT_FIRMWARE {
FIRMWARE_SOURCE eFWSource;
#ifdef CONFIG_EMBEDDED_FWIMG
u8* szFwBuffer;
#else
u8 szFwBuffer[FW_8188F_SIZE];
#endif
u32 ulFwLength;
} RT_FIRMWARE_8188F, *PRT_FIRMWARE_8188F;
//
// This structure must be cared byte-ordering
//
// Added by tynli. 2009.12.04.
typedef struct _RT_8188F_FIRMWARE_HDR
{
// 8-byte alinment required
//--- LONG WORD 0 ----
u16 Signature; // 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut
u8 Category; // AP/NIC and USB/PCI
u8 Function; // Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions
u16 Version; // FW Version
u16 Subversion; // FW Subversion, default 0x00
//--- LONG WORD 1 ----
u8 Month; // Release time Month field
u8 Date; // Release time Date field
u8 Hour; // Release time Hour field
u8 Minute; // Release time Minute field
u16 RamCodeSize; // The size of RAM code
u16 Rsvd2;
//--- LONG WORD 2 ----
u32 SvnIdx; // The SVN entry index
u32 Rsvd3;
//--- LONG WORD 3 ----
u32 Rsvd4;
u32 Rsvd5;
}RT_8188F_FIRMWARE_HDR, *PRT_8188F_FIRMWARE_HDR;
#define DRIVER_EARLY_INT_TIME_8188F 0x05
#define BCN_DMA_ATIME_INT_TIME_8188F 0x02
// for 8188F
// TX 32K, RX 16K, Page size 128B for TX, 8B for RX
#define PAGE_SIZE_TX_8188F 128
#define PAGE_SIZE_RX_8188F 8
#define RX_DMA_SIZE_8188F 0x4000 // 16K
#ifdef CONFIG_FW_C2H_DEBUG
#define RX_DMA_RESERVED_SIZE_8188F 0x100 // 256B, reserved for c2h debug message
#else
#define RX_DMA_RESERVED_SIZE_8188F 0x80 // 128B, reserved for tx report
#endif
#ifdef CONFIG_WOWLAN
#define RESV_FMWF WKFMCAM_SIZE*MAX_WKFM_NUM /* 16 entries, for each is 24 bytes*/
#else
#define RESV_FMWF 0
#endif
#define RX_DMA_BOUNDARY_8188F (RX_DMA_SIZE_8188F - RX_DMA_RESERVED_SIZE_8188F - 1)
// Note: We will divide number of page equally for each queue other than public queue!
//For General Reserved Page Number(Beacon Queue is reserved page)
//Beacon:2, PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1
#define BCNQ_PAGE_NUM_8188F 0x08
#ifdef CONFIG_CONCURRENT_MODE
#define BCNQ1_PAGE_NUM_8188F 0x08 // 0x04
#else
#define BCNQ1_PAGE_NUM_8188F 0x00
#endif
#ifdef CONFIG_PNO_SUPPORT
#undef BCNQ1_PAGE_NUM_8188F
#define BCNQ1_PAGE_NUM_8188F 0x00 // 0x04
#endif
//For WoWLan , more reserved page
//ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, PNO: 6
#ifdef CONFIG_WOWLAN
#define WOWLAN_PAGE_NUM_8188F 0x07
#else
#define WOWLAN_PAGE_NUM_8188F 0x00
#endif
#ifdef CONFIG_PNO_SUPPORT
#undef WOWLAN_PAGE_NUM_8188F
#define WOWLAN_PAGE_NUM_8188F 0x15
#endif
#ifdef CONFIG_AP_WOWLAN
#define AP_WOWLAN_PAGE_NUM_8188F 0x02
#endif
#define TX_TOTAL_PAGE_NUMBER_8188F (0xFF - BCNQ_PAGE_NUM_8188F - BCNQ1_PAGE_NUM_8188F - WOWLAN_PAGE_NUM_8188F)
#define TX_PAGE_BOUNDARY_8188F (TX_TOTAL_PAGE_NUMBER_8188F + 1)
#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8188F TX_TOTAL_PAGE_NUMBER_8188F
#define WMM_NORMAL_TX_PAGE_BOUNDARY_8188F (WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8188F + 1)
// For Normal Chip Setting
// (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8188F
#define NORMAL_PAGE_NUM_HPQ_8188F 0x0C
#define NORMAL_PAGE_NUM_LPQ_8188F 0x02
#define NORMAL_PAGE_NUM_NPQ_8188F 0x02
// Note: For Normal Chip Setting, modify later
#define WMM_NORMAL_PAGE_NUM_HPQ_8188F 0x30
#define WMM_NORMAL_PAGE_NUM_LPQ_8188F 0x20
#define WMM_NORMAL_PAGE_NUM_NPQ_8188F 0x20
#include "HalVerDef.h"
#include "hal_com.h"
#define EFUSE_OOB_PROTECT_BYTES 15
#define HAL_EFUSE_MEMORY
#define HWSET_MAX_SIZE_8188F 512
#define EFUSE_REAL_CONTENT_LEN_8188F 512
#define EFUSE_MAP_LEN_8188F 512
#define EFUSE_MAX_SECTION_8188F 64
#define EFUSE_IC_ID_OFFSET 506 //For some inferiority IC purpose. added by Roger, 2009.09.02.
#define AVAILABLE_EFUSE_ADDR(addr) (addr < EFUSE_REAL_CONTENT_LEN_8188F)
#define EFUSE_ACCESS_ON 0x69 // For RTL8188 only.
#define EFUSE_ACCESS_OFF 0x00 // For RTL8188 only.
//========================================================
// EFUSE for BT definition
//========================================================
#define EFUSE_BT_REAL_BANK_CONTENT_LEN 512
#define EFUSE_BT_REAL_CONTENT_LEN 1536 // 512*3
#define EFUSE_BT_MAP_LEN 1024 // 1k bytes
#define EFUSE_BT_MAX_SECTION 128 // 1024/8
#define EFUSE_PROTECT_BYTES_BANK 16
typedef struct _C2H_EVT_HDR
{
u8 CmdID;
u8 CmdLen;
u8 CmdSeq;
} __attribute__((__packed__)) C2H_EVT_HDR, *PC2H_EVT_HDR;
#define INCLUDE_MULTI_FUNC_BT(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)
#define INCLUDE_MULTI_FUNC_GPS(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)
// rtl8188a_hal_init.c
s32 rtl8188f_FirmwareDownload(PADAPTER padapter, BOOLEAN bUsedWoWLANFw);
void rtl8188f_FirmwareSelfReset(PADAPTER padapter);
void rtl8188f_InitializeFirmwareVars(PADAPTER padapter);
void rtl8188f_InitAntenna_Selection(PADAPTER padapter);
void rtl8188f_DeinitAntenna_Selection(PADAPTER padapter);
void rtl8188f_CheckAntenna_Selection(PADAPTER padapter);
void rtl8188f_init_default_value(PADAPTER padapter);
s32 rtl8188f_InitLLTTable(PADAPTER padapter);
s32 CardDisableHWSM(PADAPTER padapter, u8 resetMCU);
s32 CardDisableWithoutHWSM(PADAPTER padapter);
// EFuse
u8 GetEEPROMSize8188F(PADAPTER padapter);
void Hal_InitPGData(PADAPTER padapter, u8 *PROMContent);
void Hal_EfuseParseIDCode(PADAPTER padapter, u8 *hwinfo);
void Hal_EfuseParseTxPowerInfo_8188F(PADAPTER padapter, u8 *PROMContent, BOOLEAN AutoLoadFail);
/* void Hal_EfuseParseBTCoexistInfo_8188F(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); */
void Hal_EfuseParseEEPROMVer_8188F(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
void Hal_EfuseParseChnlPlan_8188F(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
void Hal_EfuseParseCustomerID_8188F(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
void Hal_EfuseParsePowerSavingMode_8188F(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
void Hal_EfuseParseAntennaDiversity_8188F(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
void Hal_EfuseParseXtal_8188F(PADAPTER pAdapter, u8 *hwinfo, u8 AutoLoadFail);
void Hal_EfuseParseThermalMeter_8188F(PADAPTER padapter, u8 *hwinfo, u8 AutoLoadFail);
void Hal_EfuseParseKFreeData_8188F(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
#if 0 /* Do not need for rtl8188f */
VOID Hal_EfuseParseVoltage_8188F(PADAPTER pAdapter,u8* hwinfo,BOOLEAN AutoLoadFail);
#endif
#ifdef CONFIG_C2H_PACKET_EN
void rtl8188f_c2h_packet_handler(PADAPTER padapter, u8 *pbuf, u16 length);
#endif
void rtl8188f_set_pll_ref_clk_sel(_adapter *adapter, u8 sel);
void rtl8188f_set_hal_ops(struct hal_ops *pHalFunc);
void init_hal_spec_8188f(_adapter *adapter);
void SetHwReg8188F(PADAPTER padapter, u8 variable, u8 *val);
void GetHwReg8188F(PADAPTER padapter, u8 variable, u8 *val);
#ifdef CONFIG_C2H_PACKET_EN
void SetHwRegWithBuf8188F(PADAPTER padapter, u8 variable, u8 *pbuf, int len);
#endif // CONFIG_C2H_PACKET_EN
u8 SetHalDefVar8188F(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
u8 GetHalDefVar8188F(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
// register
void rtl8188f_InitBeaconParameters(PADAPTER padapter);
void rtl8188f_InitBeaconMaxError(PADAPTER padapter, u8 InfraMode);
void _InitBurstPktLen_8188FS(PADAPTER Adapter);
void _8051Reset8188(PADAPTER padapter);
#ifdef CONFIG_WOWLAN
void Hal_DetectWoWMode(PADAPTER pAdapter);
#endif //CONFIG_WOWLAN
void rtl8188f_start_thread(_adapter *padapter);
void rtl8188f_stop_thread(_adapter *padapter);
#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)
void rtl8188fs_init_checkbthang_workqueue(_adapter * adapter);
void rtl8188fs_free_checkbthang_workqueue(_adapter * adapter);
void rtl8188fs_cancle_checkbthang_workqueue(_adapter * adapter);
void rtl8188fs_hal_check_bt_hang(_adapter * adapter);
#endif
#ifdef CONFIG_GPIO_WAKEUP
void HalSetOutPutGPIO(PADAPTER padapter, u8 index, u8 OutPutValue);
#endif
int FirmwareDownloadBT(IN PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware);
void CCX_FwC2HTxRpt_8188f(PADAPTER padapter, u8 *pdata, u8 len);
#ifdef CONFIG_FW_C2H_DEBUG
void Debug_FwC2H_8188f(PADAPTER padapter, u8 *pdata, u8 len);
#endif //CONFIG_FW_C2H_DEBUG
s32 c2h_id_filter_ccx_8188f(u8 *buf);
s32 c2h_handler_8188f(PADAPTER padapter, u8 *pC2hEvent);
u8 MRateToHwRate8188F(u8 rate);
u8 HwRateToMRate8188F(u8 rate);
#ifdef CONFIG_PCI_HCI
BOOLEAN InterruptRecognized8188FE(PADAPTER Adapter);
VOID UpdateInterruptMask8188FE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
#endif
#endif

94
include/rtl8723a_led.h → include/rtl8188f_led.h
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@@ -1,45 +1,49 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTL8723A_LED_H__
#define __RTL8723A_LED_H__
//================================================================================
// Interface to manipulate LED objects.
//================================================================================
#ifdef CONFIG_USB_HCI
void rtl8723au_InitSwLeds(PADAPTER padapter);
void rtl8723au_DeInitSwLeds(PADAPTER padapter);
#endif
#ifdef CONFIG_PCI_HCI
void rtl8723ae_InitSwLeds(PADAPTER padapter);
void rtl8723ae_DeInitSwLeds(PADAPTER padapter);
#endif
#ifdef CONFIG_SDIO_HCI
void rtl8723as_InitSwLeds(PADAPTER padapter);
void rtl8723as_DeInitSwLeds(PADAPTER padapter);
#endif
#ifdef CONFIG_GSPI_HCI
void rtl8723as_InitSwLeds(PADAPTER padapter);
void rtl8723as_DeInitSwLeds(PADAPTER padapter);
#endif
#endif
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTL8188F_LED_H__
#define __RTL8188F_LED_H__
#include <drv_conf.h>
#include <osdep_service.h>
#include <drv_types.h>
//================================================================================
// Interface to manipulate LED objects.
//================================================================================
#ifdef CONFIG_USB_HCI
void rtl8188fu_InitSwLeds(PADAPTER padapter);
void rtl8188fu_DeInitSwLeds(PADAPTER padapter);
#endif
#ifdef CONFIG_SDIO_HCI
void rtl8188fs_InitSwLeds(PADAPTER padapter);
void rtl8188fs_DeInitSwLeds(PADAPTER padapter);
#endif
#ifdef CONFIG_GSPI_HCI
void rtl8188fs_InitSwLeds(PADAPTER padapter);
void rtl8188fs_DeInitSwLeds(PADAPTER padapter);
#endif
#ifdef CONFIG_PCI_HCI
void rtl8188fe_InitSwLeds(PADAPTER padapter);
void rtl8188fe_DeInitSwLeds(PADAPTER padapter);
#endif
#endif

73
include/rtl8188f_recv.h Normal file
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@@ -0,0 +1,73 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTL8188F_RECV_H__
#define __RTL8188F_RECV_H__
#if defined(CONFIG_USB_HCI)
#ifndef MAX_RECVBUF_SZ
#ifdef PLATFORM_OS_CE
#define MAX_RECVBUF_SZ (8192+1024) // 8K+1k
#else
#ifdef CONFIG_MINIMAL_MEMORY_USAGE
#define MAX_RECVBUF_SZ (4000) // about 4K
#else
#ifdef CONFIG_PLATFORM_MSTAR
#define MAX_RECVBUF_SZ (8192) // 8K
#elif defined(CONFIG_PLATFORM_HISILICON)
#define MAX_RECVBUF_SZ (16384) /* 16k */
#else
#define MAX_RECVBUF_SZ (32768) /* 32k */
#endif
//#define MAX_RECVBUF_SZ (20480) //20K
//#define MAX_RECVBUF_SZ (10240) //10K
//#define MAX_RECVBUF_SZ (16384) // 16k - 92E RX BUF :16K
//#define MAX_RECVBUF_SZ (8192+1024) // 8K+1k
#endif
#endif
#endif //!MAX_RECVBUF_SZ
#elif defined(CONFIG_PCI_HCI)
#define MAX_RECVBUF_SZ (4000) // about 4K
#elif defined(CONFIG_SDIO_HCI)
#define MAX_RECVBUF_SZ (RX_DMA_BOUNDARY_8188F + 1)
#endif /* CONFIG_SDIO_HCI */
// Rx smooth factor
#define Rx_Smooth_Factor (20)
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
s32 rtl8188fs_init_recv_priv(PADAPTER padapter);
void rtl8188fs_free_recv_priv(PADAPTER padapter);
#endif
#ifdef CONFIG_USB_HCI
int rtl8188fu_init_recv_priv(_adapter *padapter);
void rtl8188fu_free_recv_priv (_adapter *padapter);
void rtl8188fu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf);
#endif
#ifdef CONFIG_PCI_HCI
s32 rtl8188fe_init_recv_priv(PADAPTER padapter);
void rtl8188fe_free_recv_priv(PADAPTER padapter);
#endif
void rtl8188f_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc);
#endif /* __RTL8188F_RECV_H__ */

12
include/rtl8723a_rf.h → include/rtl8188f_rf.h
View File

@@ -17,11 +17,15 @@
*
*
******************************************************************************/
#ifndef __RTL8723A_RF_H__
#define __RTL8723A_RF_H__
#ifndef __RTL8188F_RF_H__
#define __RTL8188F_RF_H__
#include "rtl8192c_rf.h"
int PHY_RF6052_Config8723A( IN PADAPTER Adapter );
int PHY_RF6052_Config8188F( IN PADAPTER Adapter );
VOID
PHY_RF6052SetBandwidth8188F(
IN PADAPTER Adapter,
IN CHANNEL_WIDTH Bandwidth);
#endif

303
include/rtl8188f_spec.h Normal file
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@@ -0,0 +1,303 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*******************************************************************************/
#ifndef __RTL8188F_SPEC_H__
#define __RTL8188F_SPEC_H__
#include <drv_conf.h>
#define HAL_NAV_UPPER_UNIT_8188F 128 // micro-second
//-----------------------------------------------------
//
// 0x0000h ~ 0x00FFh System Configuration
//
//-----------------------------------------------------
#define REG_RSV_CTRL_8188F 0x001C // 3 Byte
#define REG_BT_WIFI_ANTENNA_SWITCH_8188F 0x0038
#define REG_HSISR_8188F 0x005c
#define REG_PAD_CTRL1_8188F 0x0064
#define REG_AFE_CTRL_4_8188F 0x0078
#define REG_HMEBOX_DBG_0_8188F 0x0088
#define REG_HMEBOX_DBG_1_8188F 0x008A
#define REG_HMEBOX_DBG_2_8188F 0x008C
#define REG_HMEBOX_DBG_3_8188F 0x008E
#define REG_HIMR0_8188F 0x00B0
#define REG_HISR0_8188F 0x00B4
#define REG_HIMR1_8188F 0x00B8
#define REG_HISR1_8188F 0x00BC
#define REG_PMC_DBG_CTRL2_8188F 0x00CC
//-----------------------------------------------------
//
// 0x0100h ~ 0x01FFh MACTOP General Configuration
//
//-----------------------------------------------------
#define REG_C2HEVT_CMD_ID_8188F 0x01A0
#define REG_C2HEVT_CMD_LEN_8188F 0x01AE
#define REG_WOWLAN_WAKE_REASON 0x01C7
#define REG_WOWLAN_GTK_DBG1 0x630
#define REG_WOWLAN_GTK_DBG2 0x634
#define REG_HMEBOX_EXT0_8188F 0x01F0
#define REG_HMEBOX_EXT1_8188F 0x01F4
#define REG_HMEBOX_EXT2_8188F 0x01F8
#define REG_HMEBOX_EXT3_8188F 0x01FC
//-----------------------------------------------------
//
// 0x0200h ~ 0x027Fh TXDMA Configuration
//
//-----------------------------------------------------
//-----------------------------------------------------
//
// 0x0280h ~ 0x02FFh RXDMA Configuration
//
//-----------------------------------------------------
#define REG_RXDMA_CONTROL_8188F 0x0286 // Control the RX DMA.
#define REG_RXDMA_MODE_CTRL_8188F 0x0290
//-----------------------------------------------------
//
// 0x0300h ~ 0x03FFh PCIe
//
//-----------------------------------------------------
#define REG_PCIE_CTRL_REG_8188F 0x0300
#define REG_INT_MIG_8188F 0x0304 // Interrupt Migration
#define REG_BCNQ_DESA_8188F 0x0308 // TX Beacon Descriptor Address
#define REG_HQ_DESA_8188F 0x0310 // TX High Queue Descriptor Address
#define REG_MGQ_DESA_8188F 0x0318 // TX Manage Queue Descriptor Address
#define REG_VOQ_DESA_8188F 0x0320 // TX VO Queue Descriptor Address
#define REG_VIQ_DESA_8188F 0x0328 // TX VI Queue Descriptor Address
#define REG_BEQ_DESA_8188F 0x0330 // TX BE Queue Descriptor Address
#define REG_BKQ_DESA_8188F 0x0338 // TX BK Queue Descriptor Address
#define REG_RX_DESA_8188F 0x0340 // RX Queue Descriptor Address
#define REG_DBI_WDATA_8188F 0x0348 // DBI Write Data
#define REG_DBI_RDATA_8188F 0x034C // DBI Read Data
#define REG_DBI_ADDR_8188F 0x0350 // DBI Address
#define REG_DBI_FLAG_8188F 0x0352 // DBI Read/Write Flag
#define REG_MDIO_WDATA_8188F 0x0354 // MDIO for Write PCIE PHY
#define REG_MDIO_RDATA_8188F 0x0356 // MDIO for Reads PCIE PHY
#define REG_MDIO_CTL_8188F 0x0358 // MDIO for Control
#define REG_DBG_SEL_8188F 0x0360 // Debug Selection Register
#define REG_PCIE_HRPWM_8188F 0x0361 //PCIe RPWM
#define REG_PCIE_HCPWM_8188F 0x0363 //PCIe CPWM
#define REG_PCIE_MULTIFET_CTRL_8188F 0x036A //PCIE Multi-Fethc Control
//-----------------------------------------------------
//
// 0x0400h ~ 0x047Fh Protocol Configuration
//
//-----------------------------------------------------
#define REG_TXPKTBUF_BCNQ_BDNY_8188F 0x0424
#define REG_TXPKTBUF_MGQ_BDNY_8188F 0x0425
#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8188F 0x045D
#ifdef CONFIG_WOWLAN
#define REG_TXPKTBUF_IV_LOW 0x0484
#define REG_TXPKTBUF_IV_HIGH 0x0488
#endif
#define REG_AMPDU_BURST_MODE_8188F 0x04BC
//-----------------------------------------------------
//
// 0x0500h ~ 0x05FFh EDCA Configuration
//
//-----------------------------------------------------
#define REG_SECONDARY_CCA_CTRL_8188F 0x0577
//-----------------------------------------------------
//
// 0x0600h ~ 0x07FFh WMAC Configuration
//
//-----------------------------------------------------
//============================================================
// SDIO Bus Specification
//============================================================
//-----------------------------------------------------
// SDIO CMD Address Mapping
//-----------------------------------------------------
//-----------------------------------------------------
// I/O bus domain (Host)
//-----------------------------------------------------
//-----------------------------------------------------
// SDIO register
//-----------------------------------------------------
#define SDIO_REG_HIQ_FREEPG_8188F 0x0020
#define SDIO_REG_MID_FREEPG_8188F 0x0022
#define SDIO_REG_LOW_FREEPG_8188F 0x0024
#define SDIO_REG_PUB_FREEPG_8188F 0x0026
#define SDIO_REG_EXQ_FREEPG_8188F 0x0028
#define SDIO_REG_AC_OQT_FREEPG_8188F 0x002A
#define SDIO_REG_NOAC_OQT_FREEPG_8188F 0x002B
#define SDIO_REG_HCPWM1_8188F 0x0038
/* indirect access */
#define SDIO_REG_INDIRECT_REG_CFG_8188F 0x40
#define SET_INDIRECT_REG_ADDR(_cmd, _addr) SET_BITS_TO_LE_2BYTE(((u8 *)(_cmd)) + 0, 0, 16, (_addr))
#define SET_INDIRECT_REG_SIZE_1BYTE(_cmd) SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 0, 2, 0)
#define SET_INDIRECT_REG_SIZE_2BYTE(_cmd) SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 0, 2, 1)
#define SET_INDIRECT_REG_SIZE_4BYTE(_cmd) SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 0, 2, 2)
#define SET_INDIRECT_REG_WRITE(_cmd) SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 2, 1, 1)
#define SET_INDIRECT_REG_READ(_cmd) SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 3, 1, 1)
#define GET_INDIRECT_REG_RDY(_cmd) LE_BITS_TO_1BYTE(((u8 *)(_cmd)) + 2, 4, 1)
#define SDIO_REG_INDIRECT_REG_DATA_8188F 0x44
//============================================================================
// 8188 Regsiter Bit and Content definition
//============================================================================
//2 HSISR
// interrupt mask which needs to clear
#define MASK_HSISR_CLEAR (HSISR_GPIO12_0_INT |\
HSISR_SPS_OCP_INT |\
HSISR_RON_INT |\
HSISR_PDNINT |\
HSISR_GPIO9_INT)
//-----------------------------------------------------
//
// 0x0100h ~ 0x01FFh MACTOP General Configuration
//
//-----------------------------------------------------
//-----------------------------------------------------
//
// 0x0200h ~ 0x027Fh TXDMA Configuration
//
//-----------------------------------------------------
//-----------------------------------------------------
//
// 0x0280h ~ 0x02FFh RXDMA Configuration
//
//-----------------------------------------------------
#define BIT_USB_RXDMA_AGG_EN BIT(31)
#define RXDMA_AGG_MODE_EN BIT(1)
#ifdef CONFIG_WOWLAN
#define RXPKT_RELEASE_POLL BIT(16)
#define RXDMA_IDLE BIT(17)
#define RW_RELEASE_EN BIT(18)
#endif
//-----------------------------------------------------
//
// 0x0400h ~ 0x047Fh Protocol Configuration
//
//-----------------------------------------------------
//----------------------------------------------------------------------------
// 8188F REG_CCK_CHECK (offset 0x454)
//----------------------------------------------------------------------------
#define BIT_BCN_PORT_SEL BIT5
//-----------------------------------------------------
//
// 0x0500h ~ 0x05FFh EDCA Configuration
//
//-----------------------------------------------------
//-----------------------------------------------------
//
// 0x0600h ~ 0x07FFh WMAC Configuration
//
//-----------------------------------------------------
//----------------------------------------------------------------------------
// 8195 IMR/ISR bits (offset 0xB0, 8bits)
//----------------------------------------------------------------------------
#define IMR_DISABLED_8188F 0
// IMR DW0(0x00B0-00B3) Bit 0-31
#define IMR_TIMER2_8188F BIT31 // Timeout interrupt 2
#define IMR_TIMER1_8188F BIT30 // Timeout interrupt 1
#define IMR_PSTIMEOUT_8188F BIT29 // Power Save Time Out Interrupt
#define IMR_GTINT4_8188F BIT28 // When GTIMER4 expires, this bit is set to 1
#define IMR_GTINT3_8188F BIT27 // When GTIMER3 expires, this bit is set to 1
#define IMR_TXBCN0ERR_8188F BIT26 // Transmit Beacon0 Error
#define IMR_TXBCN0OK_8188F BIT25 // Transmit Beacon0 OK
#define IMR_TSF_BIT32_TOGGLE_8188F BIT24 // TSF Timer BIT32 toggle indication interrupt
#define IMR_BCNDMAINT0_8188F BIT20 // Beacon DMA Interrupt 0
#define IMR_BCNDERR0_8188F BIT16 // Beacon Queue DMA OK0
#define IMR_HSISR_IND_ON_INT_8188F BIT15 // HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1)
#define IMR_BCNDMAINT_E_8188F BIT14 // Beacon DMA Interrupt Extension for Win7
#define IMR_ATIMEND_8188F BIT12 // CTWidnow End or ATIM Window End
#define IMR_C2HCMD_8188F BIT10 // CPU to Host Command INT Status, Write 1 clear
#define IMR_CPWM2_8188F BIT9 // CPU power Mode exchange INT Status, Write 1 clear
#define IMR_CPWM_8188F BIT8 // CPU power Mode exchange INT Status, Write 1 clear
#define IMR_HIGHDOK_8188F BIT7 // High Queue DMA OK
#define IMR_MGNTDOK_8188F BIT6 // Management Queue DMA OK
#define IMR_BKDOK_8188F BIT5 // AC_BK DMA OK
#define IMR_BEDOK_8188F BIT4 // AC_BE DMA OK
#define IMR_VIDOK_8188F BIT3 // AC_VI DMA OK
#define IMR_VODOK_8188F BIT2 // AC_VO DMA OK
#define IMR_RDU_8188F BIT1 // Rx Descriptor Unavailable
#define IMR_ROK_8188F BIT0 // Receive DMA OK
// IMR DW1(0x00B4-00B7) Bit 0-31
#define IMR_BCNDMAINT7_8188F BIT27 // Beacon DMA Interrupt 7
#define IMR_BCNDMAINT6_8188F BIT26 // Beacon DMA Interrupt 6
#define IMR_BCNDMAINT5_8188F BIT25 // Beacon DMA Interrupt 5
#define IMR_BCNDMAINT4_8188F BIT24 // Beacon DMA Interrupt 4
#define IMR_BCNDMAINT3_8188F BIT23 // Beacon DMA Interrupt 3
#define IMR_BCNDMAINT2_8188F BIT22 // Beacon DMA Interrupt 2
#define IMR_BCNDMAINT1_8188F BIT21 // Beacon DMA Interrupt 1
#define IMR_BCNDOK7_8188F BIT20 // Beacon Queue DMA OK Interrup 7
#define IMR_BCNDOK6_8188F BIT19 // Beacon Queue DMA OK Interrup 6
#define IMR_BCNDOK5_8188F BIT18 // Beacon Queue DMA OK Interrup 5
#define IMR_BCNDOK4_8188F BIT17 // Beacon Queue DMA OK Interrup 4
#define IMR_BCNDOK3_8188F BIT16 // Beacon Queue DMA OK Interrup 3
#define IMR_BCNDOK2_8188F BIT15 // Beacon Queue DMA OK Interrup 2
#define IMR_BCNDOK1_8188F BIT14 // Beacon Queue DMA OK Interrup 1
#define IMR_ATIMEND_E_8188F BIT13 // ATIM Window End Extension for Win7
#define IMR_TXERR_8188F BIT11 // Tx Error Flag Interrupt Status, write 1 clear.
#define IMR_RXERR_8188F BIT10 // Rx Error Flag INT Status, Write 1 clear
#define IMR_TXFOVW_8188F BIT9 // Transmit FIFO Overflow
#define IMR_RXFOVW_8188F BIT8 // Receive FIFO Overflow
#ifdef CONFIG_PCI_HCI
//#define IMR_RX_MASK (IMR_ROK_8188F|IMR_RDU_8188F|IMR_RXFOVW_8188F)
#define IMR_TX_MASK (IMR_VODOK_8188F|IMR_VIDOK_8188F|IMR_BEDOK_8188F|IMR_BKDOK_8188F|IMR_MGNTDOK_8188F|IMR_HIGHDOK_8188F)
#define RT_BCN_INT_MASKS (IMR_BCNDMAINT0_8188F | IMR_TXBCN0OK_8188F | IMR_TXBCN0ERR_8188F | IMR_BCNDERR0_8188F)
#define RT_AC_INT_MASKS (IMR_VIDOK_8188F | IMR_VODOK_8188F | IMR_BEDOK_8188F|IMR_BKDOK_8188F)
#endif
//========================================================
// General definitions
//========================================================
#define MACID_NUM_8188F 16
#define SEC_CAM_ENT_NUM_8188F 16
#define NSS_NUM_8188F 1
#define BAND_CAP_8188F (BAND_CAP_2G)
#define BW_CAP_8188F (BW_CAP_20M | BW_CAP_40M)
#define PROTO_CAP_8188F (PROTO_CAP_11B|PROTO_CAP_11G|PROTO_CAP_11N)
#endif /* __RTL8188F_SPEC_H__ */

10
include/rtl8723a_sreset.h → include/rtl8188f_sreset.h
View File

@@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@@ -17,14 +17,14 @@
*
*
******************************************************************************/
#ifndef _RTL8723A_SRESET_H_
#define _RTL8723A_SRESET_H_
#ifndef _RTL8188F_SRESET_H_
#define _RTL8188F_SRESET_H_
#include <rtw_sreset.h>
#ifdef DBG_CONFIG_ERROR_DETECT
extern void rtl8723a_sreset_xmit_status_check(_adapter *padapter);
extern void rtl8723a_sreset_linked_status_check(_adapter *padapter);
extern void rtl8188f_sreset_xmit_status_check(_adapter *padapter);
extern void rtl8188f_sreset_linked_status_check(_adapter *padapter);
#endif
#endif

336
include/rtl8188f_xmit.h Normal file
View File

@@ -0,0 +1,336 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTL8188F_XMIT_H__
#define __RTL8188F_XMIT_H__
#define MAX_TID (15)
#ifndef __INC_HAL8188FDESC_H
#define __INC_HAL8188FDESC_H
#define RX_STATUS_DESC_SIZE_8188F 24
#define RX_DRV_INFO_SIZE_UNIT_8188F 8
//DWORD 0
#define SET_RX_STATUS_DESC_PKT_LEN_8188F(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE( __pRxStatusDesc, 0, 14, __Value)
#define SET_RX_STATUS_DESC_EOR_8188F(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE( __pRxStatusDesc, 30, 1, __Value)
#define SET_RX_STATUS_DESC_OWN_8188F(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE( __pRxStatusDesc, 31, 1, __Value)
#define GET_RX_STATUS_DESC_PKT_LEN_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 0, 14)
#define GET_RX_STATUS_DESC_CRC32_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 14, 1)
#define GET_RX_STATUS_DESC_ICV_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 15, 1)
#define GET_RX_STATUS_DESC_DRVINFO_SIZE_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 16, 4)
#define GET_RX_STATUS_DESC_SECURITY_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 20, 3)
#define GET_RX_STATUS_DESC_QOS_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 23, 1)
#define GET_RX_STATUS_DESC_SHIFT_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 24, 2)
#define GET_RX_STATUS_DESC_PHY_STATUS_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 26, 1)
#define GET_RX_STATUS_DESC_SWDEC_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 27, 1)
#define GET_RX_STATUS_DESC_LAST_SEG_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 28, 1)
#define GET_RX_STATUS_DESC_FIRST_SEG_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 29, 1)
#define GET_RX_STATUS_DESC_EOR_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 30, 1)
#define GET_RX_STATUS_DESC_OWN_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 31, 1)
//DWORD 1
#define GET_RX_STATUS_DESC_MACID_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 0, 7)
#define GET_RX_STATUS_DESC_TID_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 8, 4)
#define GET_RX_STATUS_DESC_AMSDU_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 13, 1)
#define GET_RX_STATUS_DESC_RXID_MATCH_8188F(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 14, 1)
#define GET_RX_STATUS_DESC_PAGGR_8188F(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 15, 1)
#define GET_RX_STATUS_DESC_A1_FIT_8188F(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 16, 4)
#define GET_RX_STATUS_DESC_CHKERR_8188F(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 20, 1)
#define GET_RX_STATUS_DESC_IPVER_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 21, 1)
#define GET_RX_STATUS_DESC_IS_TCPUDP__8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 22, 1)
#define GET_RX_STATUS_DESC_CHK_VLD_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 23, 1)
#define GET_RX_STATUS_DESC_PAM_8188F(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 24, 1)
#define GET_RX_STATUS_DESC_PWR_8188F(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 25, 1)
#define GET_RX_STATUS_DESC_MORE_DATA_8188F(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 26, 1)
#define GET_RX_STATUS_DESC_MORE_FRAG_8188F(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 27, 1)
#define GET_RX_STATUS_DESC_TYPE_8188F(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 28, 2)
#define GET_RX_STATUS_DESC_MC_8188F(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 30, 1)
#define GET_RX_STATUS_DESC_BC_8188F(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 31, 1)
//DWORD 2
#define GET_RX_STATUS_DESC_SEQ_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+8, 0, 12)
#define GET_RX_STATUS_DESC_FRAG_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+8, 12, 4)
#define GET_RX_STATUS_DESC_RX_IS_QOS_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+8, 16, 1)
#define GET_RX_STATUS_DESC_WLANHD_IV_LEN_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+8, 18, 6)
#define GET_RX_STATUS_DESC_RPT_SEL_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+8, 28, 1)
//DWORD 3
#define GET_RX_STATUS_DESC_RX_RATE_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+12, 0, 7)
#define GET_RX_STATUS_DESC_HTC_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+12, 10, 1)
#define GET_RX_STATUS_DESC_EOSP_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+12, 11, 1)
#define GET_RX_STATUS_DESC_BSSID_FIT_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+12, 12, 2)
#ifdef CONFIG_USB_RX_AGGREGATION
#define GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+12, 16, 8)
#endif
#define GET_RX_STATUS_DESC_PATTERN_MATCH_8188F(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+12, 29, 1)
#define GET_RX_STATUS_DESC_UNICAST_MATCH_8188F(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+12, 30, 1)
#define GET_RX_STATUS_DESC_MAGIC_MATCH_8188F(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+12, 31, 1)
//DWORD 6
#define GET_RX_STATUS_DESC_SPLCP_8188F(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+16, 0, 1)
#define GET_RX_STATUS_DESC_LDPC_8188F(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+16, 1, 1)
#define GET_RX_STATUS_DESC_STBC_8188F(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+16, 2, 1)
#define GET_RX_STATUS_DESC_BW_8188F(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+16, 4, 2)
//DWORD 5
#define GET_RX_STATUS_DESC_TSFL_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+20, 0, 32)
#define GET_RX_STATUS_DESC_BUFF_ADDR_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+24, 0, 32)
#define GET_RX_STATUS_DESC_BUFF_ADDR64_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+28, 0, 32)
#define SET_RX_STATUS_DESC_BUFF_ADDR_8188F(__pRxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxDesc+24, 0, 32, __Value)
// Dword 0
#define GET_TX_DESC_OWN_8188F(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc, 31, 1)
#define SET_TX_DESC_PKT_SIZE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value)
#define SET_TX_DESC_OFFSET_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value)
#define SET_TX_DESC_BMC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value)
#define SET_TX_DESC_HTC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value)
#define SET_TX_DESC_LAST_SEG_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 26, 1, __Value)
#define SET_TX_DESC_FIRST_SEG_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value)
#define SET_TX_DESC_LINIP_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 28, 1, __Value)
#define SET_TX_DESC_NO_ACM_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value)
#define SET_TX_DESC_GF_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value)
#define SET_TX_DESC_OWN_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)
// Dword 1
#define SET_TX_DESC_MACID_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value)
#define SET_TX_DESC_QUEUE_SEL_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value)
#define SET_TX_DESC_RDG_NAV_EXT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value)
#define SET_TX_DESC_LSIG_TXOP_EN_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value)
#define SET_TX_DESC_PIFS_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value)
#define SET_TX_DESC_RATE_ID_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value)
#define SET_TX_DESC_EN_DESC_ID_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value)
#define SET_TX_DESC_SEC_TYPE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value)
#define SET_TX_DESC_PKT_OFFSET_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value)
// Dword 2
#define SET_TX_DESC_PAID_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0, 9, __Value)
#define SET_TX_DESC_CCA_RTS_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value)
#define SET_TX_DESC_AGG_ENABLE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value)
#define SET_TX_DESC_RDG_ENABLE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value)
#define SET_TX_DESC_AGG_BREAK_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value)
#define SET_TX_DESC_MORE_FRAG_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value)
#define SET_TX_DESC_RAW_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value)
#define SET_TX_DESC_SPE_RPT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value)
#define SET_TX_DESC_AMPDU_DENSITY_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value)
#define SET_TX_DESC_BT_INT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value)
#define SET_TX_DESC_GID_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 6, __Value)
// Dword 3
#define SET_TX_DESC_WHEADER_LEN_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 0, 4, __Value)
#define SET_TX_DESC_CHK_EN_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 4, 1, __Value)
#define SET_TX_DESC_EARLY_MODE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 5, 1, __Value)
#define SET_TX_DESC_HWSEQ_SEL_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value)
#define SET_TX_DESC_USE_RATE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value)
#define SET_TX_DESC_DISABLE_RTS_FB_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value)
#define SET_TX_DESC_DISABLE_FB_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value)
#define SET_TX_DESC_CTS2SELF_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value)
#define SET_TX_DESC_RTS_ENABLE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value)
#define SET_TX_DESC_HW_RTS_ENABLE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value)
#define SET_TX_DESC_NAV_USE_HDR_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 15, 1, __Value)
#define SET_TX_DESC_USE_MAX_LEN_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value)
#define SET_TX_DESC_MAX_AGG_NUM_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value)
#define SET_TX_DESC_NDPA_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 22, 2, __Value)
#define SET_TX_DESC_AMPDU_MAX_TIME_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value)
// Dword 4
#define SET_TX_DESC_TX_RATE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value)
#define SET_TX_DESC_DATA_RATE_FB_LIMIT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value)
#define SET_TX_DESC_RTS_RATE_FB_LIMIT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value)
#define SET_TX_DESC_RETRY_LIMIT_ENABLE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value)
#define SET_TX_DESC_DATA_RETRY_LIMIT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value)
#define SET_TX_DESC_RTS_RATE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value)
// Dword 5
#define SET_TX_DESC_DATA_SC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value)
#define SET_TX_DESC_DATA_SHORT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value)
#define SET_TX_DESC_DATA_BW_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value)
#define SET_TX_DESC_DATA_LDPC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 7, 1, __Value)
#define SET_TX_DESC_DATA_STBC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value)
#define SET_TX_DESC_CTROL_STBC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value)
#define SET_TX_DESC_RTS_SHORT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value)
#define SET_TX_DESC_RTS_SC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value)
// Dword 6
#define SET_TX_DESC_SW_DEFINE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value)
#define SET_TX_DESC_MBSSID_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 12, 4, __Value)
#define SET_TX_DESC_ANTSEL_A_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value)
#define SET_TX_DESC_ANTSEL_B_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 19, 3, __Value)
#define SET_TX_DESC_ANTSEL_C_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 22, 3, __Value)
#define SET_TX_DESC_ANTSEL_D_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 25, 3, __Value)
// Dword 7
#if(DEV_BUS_TYPE == RT_PCI_INTERFACE)
#define SET_TX_DESC_TX_BUFFER_SIZE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
#else
#define SET_TX_DESC_TX_DESC_CHECKSUM_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
#endif
#define SET_TX_DESC_USB_TXAGG_NUM_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value)
#if(DEV_BUS_TYPE == RT_SDIO_INTERFACE)
#define SET_TX_DESC_SDIO_TXSEQ_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 16, 8, __Value)
#endif
// Dword 8
#define SET_TX_DESC_HWSEQ_EN_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value)
// Dword 9
#define SET_TX_DESC_SEQ_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value)
// Dword 10
#define SET_TX_DESC_TX_BUFFER_ADDRESS_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+40, 0, 32, __Value)
#define GET_TX_DESC_TX_BUFFER_ADDRESS_8188F(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+40, 0, 32)
// Dword 11
#define SET_TX_DESC_NEXT_DESC_ADDRESS_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+48, 0, 32, __Value)
#define SET_EARLYMODE_PKTNUM_8188F(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value)
#define SET_EARLYMODE_LEN0_8188F(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value)
#define SET_EARLYMODE_LEN1_1_8188F(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value)
#define SET_EARLYMODE_LEN1_2_8188F(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value)
#define SET_EARLYMODE_LEN2_8188F(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15, __Value)
#define SET_EARLYMODE_LEN3_8188F(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value)
#endif
//-----------------------------------------------------------
//
// Rate
//
//-----------------------------------------------------------
// CCK Rates, TxHT = 0
#define DESC8188F_RATE1M 0x00
#define DESC8188F_RATE2M 0x01
#define DESC8188F_RATE5_5M 0x02
#define DESC8188F_RATE11M 0x03
// OFDM Rates, TxHT = 0
#define DESC8188F_RATE6M 0x04
#define DESC8188F_RATE9M 0x05
#define DESC8188F_RATE12M 0x06
#define DESC8188F_RATE18M 0x07
#define DESC8188F_RATE24M 0x08
#define DESC8188F_RATE36M 0x09
#define DESC8188F_RATE48M 0x0a
#define DESC8188F_RATE54M 0x0b
// MCS Rates, TxHT = 1
#define DESC8188F_RATEMCS0 0x0c
#define DESC8188F_RATEMCS1 0x0d
#define DESC8188F_RATEMCS2 0x0e
#define DESC8188F_RATEMCS3 0x0f
#define DESC8188F_RATEMCS4 0x10
#define DESC8188F_RATEMCS5 0x11
#define DESC8188F_RATEMCS6 0x12
#define DESC8188F_RATEMCS7 0x13
#define DESC8188F_RATEMCS8 0x14
#define DESC8188F_RATEMCS9 0x15
#define DESC8188F_RATEMCS10 0x16
#define DESC8188F_RATEMCS11 0x17
#define DESC8188F_RATEMCS12 0x18
#define DESC8188F_RATEMCS13 0x19
#define DESC8188F_RATEMCS14 0x1a
#define DESC8188F_RATEMCS15 0x1b
#define DESC8188F_RATEVHTSS1MCS0 0x2c
#define DESC8188F_RATEVHTSS1MCS1 0x2d
#define DESC8188F_RATEVHTSS1MCS2 0x2e
#define DESC8188F_RATEVHTSS1MCS3 0x2f
#define DESC8188F_RATEVHTSS1MCS4 0x30
#define DESC8188F_RATEVHTSS1MCS5 0x31
#define DESC8188F_RATEVHTSS1MCS6 0x32
#define DESC8188F_RATEVHTSS1MCS7 0x33
#define DESC8188F_RATEVHTSS1MCS8 0x34
#define DESC8188F_RATEVHTSS1MCS9 0x35
#define DESC8188F_RATEVHTSS2MCS0 0x36
#define DESC8188F_RATEVHTSS2MCS1 0x37
#define DESC8188F_RATEVHTSS2MCS2 0x38
#define DESC8188F_RATEVHTSS2MCS3 0x39
#define DESC8188F_RATEVHTSS2MCS4 0x3a
#define DESC8188F_RATEVHTSS2MCS5 0x3b
#define DESC8188F_RATEVHTSS2MCS6 0x3c
#define DESC8188F_RATEVHTSS2MCS7 0x3d
#define DESC8188F_RATEVHTSS2MCS8 0x3e
#define DESC8188F_RATEVHTSS2MCS9 0x3f
#define RX_HAL_IS_CCK_RATE_8188F(pDesc)\
(GET_RX_STATUS_DESC_RX_RATE_8188F(pDesc) == DESC8188F_RATE1M ||\
GET_RX_STATUS_DESC_RX_RATE_8188F(pDesc) == DESC8188F_RATE2M ||\
GET_RX_STATUS_DESC_RX_RATE_8188F(pDesc) == DESC8188F_RATE5_5M ||\
GET_RX_STATUS_DESC_RX_RATE_8188F(pDesc) == DESC8188F_RATE11M)
void rtl8188f_update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem);
void rtl8188f_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame);
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
s32 rtl8188fs_init_xmit_priv(PADAPTER padapter);
void rtl8188fs_free_xmit_priv(PADAPTER padapter);
s32 rtl8188fs_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
s32 rtl8188fs_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
s32 rtl8188fs_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
s32 rtl8188fs_xmit_buf_handler(PADAPTER padapter);
thread_return rtl8188fs_xmit_thread(thread_context context);
#define hal_xmit_handler rtl8188fs_xmit_buf_handler
#endif
#ifdef CONFIG_USB_HCI
s32 rtl8188fu_xmit_buf_handler(PADAPTER padapter);
#define hal_xmit_handler rtl8188fu_xmit_buf_handler
s32 rtl8188fu_init_xmit_priv(PADAPTER padapter);
void rtl8188fu_free_xmit_priv(PADAPTER padapter);
s32 rtl8188fu_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
s32 rtl8188fu_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
s32 rtl8188fu_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
//s32 rtl8812au_xmit_buf_handler(PADAPTER padapter);
void rtl8188fu_xmit_tasklet(void *priv);
s32 rtl8188fu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
void _dbg_dump_tx_info(_adapter *padapter,int frame_tag,struct tx_desc *ptxdesc);
#endif
#ifdef CONFIG_PCI_HCI
s32 rtl8188fe_init_xmit_priv(PADAPTER padapter);
void rtl8188fe_free_xmit_priv(PADAPTER padapter);
struct xmit_buf *rtl8188fe_dequeue_xmitbuf(struct rtw_tx_ring *ring);
void rtl8188fe_xmitframe_resume(_adapter *padapter);
s32 rtl8188fe_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
s32 rtl8188fe_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
s32 rtl8188fe_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
void rtl8188fe_xmit_tasklet(void *priv);
#endif
u8 BWMapping_8188F(PADAPTER Adapter, struct pkt_attrib *pattrib);
u8 SCMapping_8188F(PADAPTER Adapter, struct pkt_attrib *pattrib);
#endif

100
include/rtl8192c_cmd.h
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@@ -1,100 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTL8192C_CMD_H_
#define __RTL8192C_CMD_H_
enum cmd_msg_element_id
{
NONE_CMDMSG_EID,
AP_OFFLOAD_EID=0,
SET_PWRMODE_EID=1,
JOINBSS_RPT_EID=2,
RSVD_PAGE_EID=3,
RSSI_4_EID = 4,
RSSI_SETTING_EID=5,
MACID_CONFIG_EID=6,
MACID_PS_MODE_EID=7,
P2P_PS_OFFLOAD_EID=8,
SELECTIVE_SUSPEND_ROF_CMD=9,
P2P_PS_CTW_CMD_EID=32,
H2C_92C_IO_OFFLOAD=44,
H2C_92C_TSF_SYNC=67,
H2C_92C_DISABLE_BCN_FUNC=68,
H2C_92C_RESET_TSF = 75,
H2C_92C_CMD_MAX
};
struct cmd_msg_parm {
u8 eid; //element id
u8 sz; // sz
u8 buf[6];
};
typedef struct _SETPWRMODE_PARM{
u8 Mode;
u8 SmartPS;
u8 BcnPassTime; // unit: 100ms
}SETPWRMODE_PARM, *PSETPWRMODE_PARM;
struct H2C_SS_RFOFF_PARAM{
u8 ROFOn; // 1: on, 0:off
u16 gpio_period; // unit: 1024 us
}__attribute__ ((packed));
typedef struct JOINBSSRPT_PARM_92C{
u8 OpMode; // RT_MEDIA_STATUS
}JOINBSSRPT_PARM_92C, *PJOINBSSRPT_PARM_92C;
typedef struct _RSVDPAGE_LOC_92C{
u8 LocProbeRsp;
u8 LocPsPoll;
u8 LocNullData;
}RSVDPAGE_LOC_92C, *PRSVDPAGE_LOC_92C;
// host message to firmware cmd
void rtl8192c_set_FwPwrMode_cmd(_adapter*padapter, u8 Mode);
void rtl8192c_set_FwJoinBssReport_cmd(_adapter* padapter, u8 mstatus);
u8 rtl8192c_set_rssi_cmd(_adapter*padapter, u8 *param);
void rtl8192c_set_raid_cmd(_adapter*padapter, u32 mask, u8* arg);
void rtl8192c_Add_RateATid(PADAPTER pAdapter, u32 bitmap, u8* arg, u8 rssi_level);
u8 rtl8192c_set_FwSelectSuspend_cmd(_adapter*padapter,u8 bfwpoll, u16 period);
int rtl8192c_FillH2CCmd(_adapter* padapter, u8 ElementID, u32 CmdLen, u8* pCmdBuffer);
#ifdef CONFIG_P2P
void rtl8192c_set_p2p_ps_offload_cmd(_adapter* padapter, u8 p2p_ps_state);
#endif //CONFIG_P2P
#ifdef CONFIG_IOL
int rtl8192c_IOL_exec_cmds_sync(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt);
#endif //CONFIG_IOL
#ifdef CONFIG_BEACON_DISABLE_OFFLOAD
u8 rtl8192c_dis_beacon_fun_cmd(_adapter* padapter);
#endif // CONFIG_BEACON_DISABLE_OFFLOAD
#ifdef CONFIG_TSF_RESET_OFFLOAD
int reset_tsf(PADAPTER Adapter, u8 reset_port );
#endif // CONFIG_TSF_RESET_OFFLOAD
#endif // __RTL8192C_CMD_H_

104
include/rtl8192c_dm.h
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@@ -1,104 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTL8192C_DM_H__
#define __RTL8192C_DM_H__
//============================================================
// Description:
//
// This file is for 92CE/92CU dynamic mechanism only
//
//
//============================================================
//============================================================
// function prototype
//============================================================
typedef enum _BT_CurState{
BT_OFF = 0,
BT_ON = 1,
} BT_CurState, *PBT_CurState;
typedef enum _BT_ServiceType{
BT_SCO = 0,
BT_A2DP = 1,
BT_HID = 2,
BT_HID_Idle = 3,
BT_Scan = 4,
BT_Idle = 5,
BT_OtherAction = 6,
BT_Busy = 7,
BT_OtherBusy = 8,
BT_PAN = 9,
} BT_ServiceType, *PBT_ServiceType;
struct btcoexist_priv {
u8 BT_Coexist;
u8 BT_Ant_Num;
u8 BT_CoexistType;
u8 BT_State;
u8 BT_CUR_State; //0:on, 1:off
u8 BT_Ant_isolation; //0:good, 1:bad
u8 BT_PapeCtrl; //0:SW, 1:SW/HW dynamic
u8 BT_Service;
u8 BT_Ampdu; // 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU.
u8 BT_RadioSharedType;
u32 Ratio_Tx;
u32 Ratio_PRI;
u8 BtRfRegOrigin1E;
u8 BtRfRegOrigin1F;
u8 BtRssiState;
u32 BtEdcaUL;
u32 BtEdcaDL;
u32 BT_EDCA[2];
u8 bCOBT;
u8 bInitSet;
u8 bBTBusyTraffic;
u8 bBTTrafficModeSet;
u8 bBTNonTrafficModeSet;
//BTTraffic BT21TrafficStatistics;
u32 CurrentState;
u32 PreviousState;
u8 BtPreRssiState;
u8 bFWCoexistAllOff;
u8 bSWCoexistAllOff;
};
//============================================================
// structure and define
//============================================================
//============================================================
// function prototype
//============================================================
#ifdef CONFIG_BT_COEXIST
void rtl8192c_set_dm_bt_coexist(_adapter *padapter, u8 bStart);
void rtl8192c_issue_delete_ba(_adapter *padapter, u8 dir);
#endif
void rtl8192c_init_dm_priv(IN PADAPTER Adapter);
void rtl8192c_deinit_dm_priv(IN PADAPTER Adapter);
void rtl8192c_InitHalDm( IN PADAPTER Adapter);
void rtl8192c_HalDmWatchDog(IN PADAPTER Adapter);
#endif //__HAL8190PCIDM_H__

416
include/rtl8192c_hal.h
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@@ -1,416 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTL8192C_HAL_H__
#define __RTL8192C_HAL_H__
//#include "hal_com.h"
#if 1
#include "hal_data.h"
#else
#include "../hal/OUTSRC/odm_precomp.h"
#endif
#include "drv_types.h"
#include "rtl8192c_spec.h"
#include "Hal8192CPhyReg.h"
#include "Hal8192CPhyCfg.h"
#include "rtl8192c_rf.h"
#include "rtl8192c_dm.h"
#include "rtl8192c_recv.h"
#include "rtl8192c_xmit.h"
#include "rtl8192c_cmd.h"
#include "rtl8192c_led.h"
#ifdef DBG_CONFIG_ERROR_DETECT
#include "rtl8192c_sreset.h"
#endif
#ifdef CONFIG_PCI_HCI
#define RTL819X_DEFAULT_RF_TYPE RF_2T2R
//#define RTL819X_DEFAULT_RF_TYPE RF_1T2R
#define RTL819X_TOTAL_RF_PATH 2
//2TODO: The following need to check!!
#define RTL8192C_FW_TSMC_IMG "rtl8192CE\\rtl8192cfwT.bin"
#define RTL8192C_FW_UMC_IMG "rtl8192CE\\rtl8192cfwU.bin"
#define RTL8192C_FW_UMC_B_IMG "rtl8192CE\\rtl8192cfwU_B.bin"
#define RTL8188C_PHY_REG "rtl8192CE\\PHY_REG_1T.txt"
#define RTL8188C_PHY_RADIO_A "rtl8192CE\\radio_a_1T.txt"
#define RTL8188C_PHY_RADIO_B "rtl8192CE\\radio_b_1T.txt"
#define RTL8188C_AGC_TAB "rtl8192CE\\AGC_TAB_1T.txt"
#define RTL8188C_PHY_MACREG "rtl8192CE\\MACREG_1T.txt"
#define RTL8192C_PHY_REG "rtl8192CE\\PHY_REG_2T.txt"
#define RTL8192C_PHY_RADIO_A "rtl8192CE\\radio_a_2T.txt"
#define RTL8192C_PHY_RADIO_B "rtl8192CE\\radio_b_2T.txt"
#define RTL8192C_AGC_TAB "rtl8192CE\\AGC_TAB_2T.txt"
#define RTL8192C_PHY_MACREG "rtl8192CE\\MACREG_2T.txt"
#define RTL819X_PHY_MACPHY_REG "rtl8192CE\\MACPHY_reg.txt"
#define RTL819X_PHY_MACPHY_REG_PG "rtl8192CE\\MACPHY_reg_PG.txt"
#define RTL819X_PHY_MACREG "rtl8192CE\\MAC_REG.txt"
#define RTL819X_PHY_REG "rtl8192CE\\PHY_REG.txt"
#define RTL819X_PHY_REG_1T2R "rtl8192CE\\PHY_REG_1T2R.txt"
#define RTL819X_PHY_REG_to1T1R "rtl8192CE\\phy_to1T1R_a.txt"
#define RTL819X_PHY_REG_to1T2R "rtl8192CE\\phy_to1T2R.txt"
#define RTL819X_PHY_REG_to2T2R "rtl8192CE\\phy_to2T2R.txt"
#define RTL819X_PHY_REG_PG "rtl8192CE\\PHY_REG_PG.txt"
#define RTL819X_AGC_TAB "rtl8192CE\\AGC_TAB.txt"
#define RTL819X_PHY_RADIO_A "rtl8192CE\\radio_a.txt"
#define RTL819X_PHY_RADIO_A_1T "rtl8192CE\\radio_a_1t.txt"
#define RTL819X_PHY_RADIO_A_2T "rtl8192CE\\radio_a_2t.txt"
#define RTL819X_PHY_RADIO_B "rtl8192CE\\radio_b.txt"
#define RTL819X_PHY_RADIO_B_GM "rtl8192CE\\radio_b_gm.txt"
#define RTL819X_PHY_RADIO_C "rtl8192CE\\radio_c.txt"
#define RTL819X_PHY_RADIO_D "rtl8192CE\\radio_d.txt"
#define RTL819X_EEPROM_MAP "rtl8192CE\\8192ce.map"
#define RTL819X_EFUSE_MAP "rtl8192CE\\8192ce.map"
//---------------------------------------------------------------------
// RTL8723E From file
//---------------------------------------------------------------------
// The file name "_2T" is for 92CE, "_1T" is for 88CE. Modified by tynli. 2009.11.24.
#define Rtl819XFwTSMCImageArray Rtl8192CEFwTSMCImgArray
#define Rtl819XFwUMCACutImageArray Rtl8192CEFwUMCACutImgArray
#define Rtl819XFwUMCBCutImageArray Rtl8192CEFwUMCBCutImgArray
// #define Rtl8723FwUMCImageArray Rtl8192CEFwUMC8723ImgArray
#define Rtl819XMAC_Array Rtl8192CEMAC_2T_Array
#define Rtl819XAGCTAB_2TArray Rtl8192CEAGCTAB_2TArray
#define Rtl819XAGCTAB_1TArray Rtl8192CEAGCTAB_1TArray
#define Rtl819XPHY_REG_2TArray Rtl8192CEPHY_REG_2TArray
#define Rtl819XPHY_REG_1TArray Rtl8192CEPHY_REG_1TArray
#define Rtl819XRadioA_2TArray Rtl8192CERadioA_2TArray
#define Rtl819XRadioA_1TArray Rtl8192CERadioA_1TArray
#define Rtl819XRadioB_2TArray Rtl8192CERadioB_2TArray
#define Rtl819XRadioB_1TArray Rtl8192CERadioB_1TArray
#define Rtl819XPHY_REG_Array_PG Rtl8192CEPHY_REG_Array_PG
#define Rtl819XPHY_REG_Array_MP Rtl8192CEPHY_REG_Array_MP
#define PHY_REG_2TArrayLength Rtl8192CEPHY_REG_2TArrayLength
#define PHY_REG_1TArrayLength Rtl8192CEPHY_REG_1TArrayLength
#define PHY_ChangeTo_1T1RArrayLength Rtl8192CEPHY_ChangeTo_1T1RArrayLength
#define PHY_ChangeTo_1T2RArrayLength Rtl8192CEPHY_ChangeTo_1T2RArrayLength
#define PHY_ChangeTo_2T2RArrayLength Rtl8192CEPHY_ChangeTo_2T2RArrayLength
#define PHY_REG_Array_PGLength Rtl8192CEPHY_REG_Array_PGLength
//#define PHY_REG_Array_PG_mCardLength Rtl8192CEPHY_REG_Array_PG_mCardLength
#define PHY_REG_Array_MPLength Rtl8192CEPHY_REG_Array_MPLength
#define PHY_REG_Array_MPLength Rtl8192CEPHY_REG_Array_MPLength
//#define PHY_REG_1T_mCardArrayLength Rtl8192CEPHY_REG_1T_mCardArrayLength
//#define PHY_REG_2T_mCardArrayLength Rtl8192CEPHY_REG_2T_mCardArrayLength
//#define PHY_REG_Array_PG_HPLength Rtl8192CEPHY_REG_Array_PG_HPLength
#define RadioA_2TArrayLength Rtl8192CERadioA_2TArrayLength
#define RadioB_2TArrayLength Rtl8192CERadioB_2TArrayLength
#define RadioA_1TArrayLength Rtl8192CERadioA_1TArrayLength
#define RadioB_1TArrayLength Rtl8192CERadioB_1TArrayLength
//#define RadioA_1T_mCardArrayLength Rtl8192CERadioA_1T_mCardArrayLength
//#define RadioB_1T_mCardArrayLength Rtl8192CERadioB_1T_mCardArrayLength
//#define RadioA_1T_HPArrayLength Rtl8192CERadioA_1T_HPArrayLength
#define RadioB_GM_ArrayLength Rtl8192CERadioB_GM_ArrayLength
#define MAC_2T_ArrayLength Rtl8192CEMAC_2T_ArrayLength
#define MACPHY_Array_PGLength Rtl8192CEMACPHY_Array_PGLength
#define AGCTAB_2TArrayLength Rtl8192CEAGCTAB_2TArrayLength
#define AGCTAB_1TArrayLength Rtl8192CEAGCTAB_1TArrayLength
//#define AGCTAB_1T_HPArrayLength Rtl8192CEAGCTAB_1T_HPArrayLength
#elif defined(CONFIG_USB_HCI)
//2TODO: We should define 8192S firmware related macro settings here!!
#define RTL819X_DEFAULT_RF_TYPE RF_1T2R
#define RTL819X_TOTAL_RF_PATH 2
//TODO: The following need to check!!
#define RTL8192C_FW_TSMC_IMG "rtl8192CU\\rtl8192cfwT.bin"
#define RTL8192C_FW_UMC_IMG "rtl8192CU\\rtl8192cfwU.bin"
#define RTL8192C_FW_UMC_B_IMG "rtl8192CU\\rtl8192cfwU_B.bin"
//#define RTL819X_FW_BOOT_IMG "rtl8192CU\\boot.img"
//#define RTL819X_FW_MAIN_IMG "rtl8192CU\\main.img"
//#define RTL819X_FW_DATA_IMG "rtl8192CU\\data.img"
#define RTL8188C_PHY_REG "rtl8188CU\\PHY_REG.txt"
#define RTL8188C_PHY_RADIO_A "rtl8188CU\\radio_a.txt"
#define RTL8188C_PHY_RADIO_B "rtl8188CU\\radio_b.txt"
#define RTL8188C_PHY_RADIO_A_mCard "rtl8192CU\\radio_a_1T_mCard.txt"
#define RTL8188C_PHY_RADIO_B_mCard "rtl8192CU\\radio_b_1T_mCard.txt"
#define RTL8188C_PHY_RADIO_A_HP "rtl8192CU\\radio_a_1T_HP.txt"
#define RTL8188C_AGC_TAB "rtl8188CU\\AGC_TAB.txt"
#define RTL8188C_PHY_MACREG "rtl8188CU\\MACREG.txt"
#define RTL8192C_PHY_REG "rtl8192CU\\PHY_REG.txt"
#define RTL8192C_PHY_RADIO_A "rtl8192CU\\radio_a.txt"
#define RTL8192C_PHY_RADIO_B "rtl8192CU\\radio_b.txt"
#define RTL8192C_AGC_TAB "rtl8192CU\\AGC_TAB.txt"
#define RTL8192C_PHY_MACREG "rtl8192CU\\MACREG.txt"
#define RTL819X_PHY_REG_PG "rtl8192CU\\PHY_REG_PG.txt"
//---------------------------------------------------------------------
// RTL8723U From file
//---------------------------------------------------------------------
// The file name "_2T" is for 92CU, "_1T" is for 88CU. Modified by tynli. 2009.11.24.
#define Rtl819XFwImageArray Rtl8192CUFwTSMCImgArray
#define Rtl819XFwTSMCImageArray Rtl8192CUFwTSMCImgArray
#define Rtl819XFwUMCACutImageArray Rtl8192CUFwUMCACutImgArray
#define Rtl819XFwUMCBCutImageArray Rtl8192CUFwUMCBCutImgArray
#define Rtl819XMAC_Array Rtl8192CUMAC_2T_Array
#define Rtl819XAGCTAB_2TArray Rtl8192CUAGCTAB_2TArray
#define Rtl819XAGCTAB_1TArray Rtl8192CUAGCTAB_1TArray
#define Rtl819XAGCTAB_1T_HPArray Rtl8192CUAGCTAB_1T_HPArray
#define Rtl819XPHY_REG_2TArray Rtl8192CUPHY_REG_2TArray
#define Rtl819XPHY_REG_1TArray Rtl8192CUPHY_REG_1TArray
#define Rtl819XPHY_REG_1T_mCardArray Rtl8192CUPHY_REG_1T_mCardArray
#define Rtl819XPHY_REG_2T_mCardArray Rtl8192CUPHY_REG_2T_mCardArray
#define Rtl819XPHY_REG_1T_HPArray Rtl8192CUPHY_REG_1T_HPArray
#define Rtl819XRadioA_2TArray Rtl8192CURadioA_2TArray
#define Rtl819XRadioA_1TArray Rtl8192CURadioA_1TArray
#define Rtl819XRadioA_1T_mCardArray Rtl8192CURadioA_1T_mCardArray
#define Rtl819XRadioB_2TArray Rtl8192CURadioB_2TArray
#define Rtl819XRadioB_1TArray Rtl8192CURadioB_1TArray
#define Rtl819XRadioB_1T_mCardArray Rtl8192CURadioB_1T_mCardArray
#define Rtl819XRadioA_1T_HPArray Rtl8192CURadioA_1T_HPArray
#define Rtl819XPHY_REG_Array_PG Rtl8192CUPHY_REG_Array_PG
#define Rtl819XPHY_REG_Array_PG_mCard Rtl8192CUPHY_REG_Array_PG_mCard
#define Rtl819XPHY_REG_Array_PG_HP Rtl8192CUPHY_REG_Array_PG_HP
#define Rtl819XPHY_REG_Array_MP Rtl8192CUPHY_REG_Array_MP
#define PHY_REG_2TArrayLength Rtl8192CUPHY_REG_2TArrayLength
#define PHY_REG_1TArrayLength Rtl8192CUPHY_REG_1TArrayLength
#define PHY_ChangeTo_1T1RArrayLength Rtl8192CUPHY_ChangeTo_1T1RArrayLength
#define PHY_ChangeTo_1T2RArrayLength Rtl8192CUPHY_ChangeTo_1T2RArrayLength
#define PHY_ChangeTo_2T2RArrayLength Rtl8192CUPHY_ChangeTo_2T2RArrayLength
#define PHY_REG_Array_PGLength Rtl8192CUPHY_REG_Array_PGLength
#define PHY_REG_Array_PG_mCardLength Rtl8192CUPHY_REG_Array_PG_mCardLength
#define PHY_REG_Array_MPLength Rtl8192CUPHY_REG_Array_MPLength
#define PHY_REG_Array_MPLength Rtl8192CUPHY_REG_Array_MPLength
#define PHY_REG_1T_mCardArrayLength Rtl8192CUPHY_REG_1T_mCardArrayLength
#define PHY_REG_2T_mCardArrayLength Rtl8192CUPHY_REG_2T_mCardArrayLength
#define PHY_REG_Array_PG_HPLength Rtl8192CUPHY_REG_Array_PG_HPLength
#define RadioA_2TArrayLength Rtl8192CURadioA_2TArrayLength
#define RadioB_2TArrayLength Rtl8192CURadioB_2TArrayLength
#define RadioA_1TArrayLength Rtl8192CURadioA_1TArrayLength
#define RadioB_1TArrayLength Rtl8192CURadioB_1TArrayLength
#define RadioA_1T_mCardArrayLength Rtl8192CURadioA_1T_mCardArrayLength
#define RadioB_1T_mCardArrayLength Rtl8192CURadioB_1T_mCardArrayLength
#define RadioA_1T_HPArrayLength Rtl8192CURadioA_1T_HPArrayLength
#define RadioB_GM_ArrayLength Rtl8192CURadioB_GM_ArrayLength
#define MAC_2T_ArrayLength Rtl8192CUMAC_2T_ArrayLength
#define MACPHY_Array_PGLength Rtl8192CUMACPHY_Array_PGLength
#define AGCTAB_2TArrayLength Rtl8192CUAGCTAB_2TArrayLength
#define AGCTAB_1TArrayLength Rtl8192CUAGCTAB_1TArrayLength
#define AGCTAB_1T_HPArrayLength Rtl8192CUAGCTAB_1T_HPArrayLength
#define PHY_REG_1T_HPArrayLength Rtl8192CUPHY_REG_1T_HPArrayLength
#endif
#define FW_8192C_SIZE 16384+32//16k
#define FW_8192C_START_ADDRESS 0x1000
//#define FW_8192C_END_ADDRESS 0x3FFF //Filen said this is for test chip
#define FW_8192C_END_ADDRESS 0x1FFF
#define IS_FW_HEADER_EXIST_92C(_pFwHdr) ((le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x92C0 ||\
(le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x88C0 ||\
(le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x2300)
typedef struct _RT_FIRMWARE_8192C{
FIRMWARE_SOURCE eFWSource;
u8* szFwBuffer;
u32 ulFwLength;
} RT_FIRMWARE_8192C, *PRT_FIRMWARE_8192C;
//
// This structure must be cared byte-ordering
//
// Added by tynli. 2009.12.04.
typedef struct _RT_8192C_FIRMWARE_HDR {//8-byte alinment required
//--- LONG WORD 0 ----
u16 Signature; // 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut
u8 Category; // AP/NIC and USB/PCI
u8 Function; // Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions
u16 Version; // FW Version
u8 Subversion; // FW Subversion, default 0x00
u16 Rsvd1;
//--- LONG WORD 1 ----
u8 Month; // Release time Month field
u8 Date; // Release time Date field
u8 Hour; // Release time Hour field
u8 Minute; // Release time Minute field
u16 RamCodeSize; // The size of RAM code
u16 Rsvd2;
//--- LONG WORD 2 ----
u32 SvnIdx; // The SVN entry index
u32 Rsvd3;
//--- LONG WORD 3 ----
u32 Rsvd4;
u32 Rsvd5;
}RT_8192C_FIRMWARE_HDR, *PRT_8192C_FIRMWARE_HDR;
#define DRIVER_EARLY_INT_TIME_8192C 0x05
#define BCN_DMA_ATIME_INT_TIME_8192C 0x02
// Note: We will divide number of page equally for each queue other than public queue!
#define TX_TOTAL_PAGE_NUMBER_8192C 0xF8
#define TX_PAGE_BOUNDARY (TX_TOTAL_PAGE_NUMBER_8192C + 1)
// For Normal Chip Setting
// (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8192C
#define NORMAL_PAGE_NUM_PUBQ 0xE7
#define NORMAL_PAGE_NUM_HPQ 0x0C
#define NORMAL_PAGE_NUM_LPQ 0x02
#define NORMAL_PAGE_NUM_NPQ 0x02
// For Test Chip Setting
// (HPQ + LPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8192C
#define TEST_PAGE_NUM_PUBQ 0x7E
// For Test Chip Setting
#define WMM_TEST_TX_TOTAL_PAGE_NUMBER 0xF5
#define WMM_TEST_TX_PAGE_BOUNDARY (WMM_TEST_TX_TOTAL_PAGE_NUMBER + 1) //F6
#define WMM_TEST_PAGE_NUM_PUBQ 0xA3
#define WMM_TEST_PAGE_NUM_HPQ 0x29
#define WMM_TEST_PAGE_NUM_LPQ 0x29
//Note: For Normal Chip Setting ,modify later
#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER 0xF5
#define WMM_NORMAL_TX_PAGE_BOUNDARY (WMM_TEST_TX_TOTAL_PAGE_NUMBER + 1) //F6
#define WMM_NORMAL_PAGE_NUM_PUBQ 0xB0
#define WMM_NORMAL_PAGE_NUM_HPQ 0x29
#define WMM_NORMAL_PAGE_NUM_LPQ 0x1C
#define WMM_NORMAL_PAGE_NUM_NPQ 0x1C
//-------------------------------------------------------------------------
// Chip specific
//-------------------------------------------------------------------------
#define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3)
#define CHIP_BONDING_92C_1T2R 0x1
#define CHIP_BONDING_88C_USB_MCARD 0x2
#define CHIP_BONDING_88C_USB_HP 0x1
//-------------------------------------------------------------------------
// Channel Plan
//-------------------------------------------------------------------------
#define EFUSE_REAL_CONTENT_LEN 512
#define EFUSE_MAP_LEN 128
#define EFUSE_MAX_SECTION 16
#define EFUSE_IC_ID_OFFSET 506 //For some inferiority IC purpose. added by Roger, 2009.09.02.
#define AVAILABLE_EFUSE_ADDR(addr) (addr < EFUSE_REAL_CONTENT_LEN)
//
// <Roger_Notes> To prevent out of boundary programming case, leave 1byte and program full section
// 9bytes + 1byt + 5bytes and pre 1byte.
// For worst case:
// | 1byte|----8bytes----|1byte|--5bytes--|
// | | Reserved(14bytes) |
//
#define EFUSE_OOB_PROTECT_BYTES 15 // PG data exclude header, dummy 6 bytes frome CP test and reserved 1byte.
#define EFUSE_MAP_LEN_8723 256
#define EFUSE_MAX_SECTION_8723 32
//========================================================
// EFUSE for BT definition
//========================================================
#define EFUSE_BT_REAL_CONTENT_LEN 1536 // 512*3
#define EFUSE_BT_MAP_LEN 1024 // 1k bytes
#define EFUSE_BT_MAX_SECTION 128 // 1024/8
#define EFUSE_PROTECT_BYTES_BANK 16
enum c2h_id_8192c {
C2H_DBG = 0,
C2H_TSF = 1,
C2H_AP_RPT_RSP = 2,
C2H_CCX_TX_RPT = 3,
C2H_BT_RSSI = 4,
C2H_BT_OP_MODE = 5,
C2H_EXT_RA_RPT = 6,
C2H_HW_INFO_EXCH = 10,
C2H_C2H_H2C_TEST = 11,
C2H_BT_INFO = 12,
C2H_BT_MP_INFO = 15,
MAX_C2HEVENT
};
#ifdef CONFIG_PCI_HCI
//
// Function disabled.
//
#define DF_TX_BIT BIT0
#define DF_RX_BIT BIT1
#define DF_IO_BIT BIT2
#define DF_IO_D3_BIT BIT3
#define RT_DF_TYPE u32
//#define RT_DISABLE_FUNC(__pAdapter, __FuncBits) ((__pAdapter)->DisabledFunctions |= ((RT_DF_TYPE)(__FuncBits)))
//#define RT_ENABLE_FUNC(__pAdapter, __FuncBits) ((__pAdapter)->DisabledFunctions &= (~((RT_DF_TYPE)(__FuncBits))))
//#define RT_IS_FUNC_DISABLED(__pAdapter, __FuncBits) ( (__pAdapter)->DisabledFunctions & (__FuncBits) )
#define IS_MULTI_FUNC_CHIP(_Adapter) (((((PHAL_DATA_TYPE)(_Adapter->HalData))->MultiFunc) & (RT_MULTI_FUNC_BT|RT_MULTI_FUNC_GPS)) ? _TRUE : _FALSE)
void InterruptRecognized8192CE(PADAPTER Adapter, PRT_ISR_CONTENT pIsrContent);
VOID UpdateInterruptMask8192CE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
#endif
#define INCLUDE_MULTI_FUNC_BT(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)
#define INCLUDE_MULTI_FUNC_GPS(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)
VOID rtl8192c_FirmwareSelfReset(IN PADAPTER Adapter);
int FirmwareDownload92C(IN PADAPTER Adapter);
VOID InitializeFirmwareVars92C(PADAPTER Adapter);
u8 GetEEPROMSize8192C(PADAPTER Adapter);
void rtl8192c_EfuseParseChnlPlan(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
HAL_VERSION rtl8192c_ReadChipVersion(IN PADAPTER Adapter);
void rtl8192c_ReadBluetoothCoexistInfo(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
VOID rtl8192c_EfuseParseIDCode(PADAPTER pAdapter, u8 *hwinfo);
void rtl8192c_init_default_value(_adapter *adapter);
void rtl8192c_set_hal_ops(struct hal_ops *pHalFunc);
s32 c2h_id_filter_ccx_8192c(u8 *buf);
void SetHwReg8192C(PADAPTER padapter, u8 variable, u8 *val);
void GetHwReg8192C(PADAPTER padapter, u8 variable, u8 *val);
#endif

45
include/rtl8192c_rf.h
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef _RTL8192C_RF_H_
#define _RTL8192C_RF_H_
//
// RF RL6052 Series API
//
void rtl8192c_RF_ChangeTxPath( IN PADAPTER Adapter,
IN u16 DataRate);
void rtl8192c_PHY_RF6052SetBandwidth(
IN PADAPTER Adapter,
IN CHANNEL_WIDTH Bandwidth);
VOID rtl8192c_PHY_RF6052SetCckTxPower(
IN PADAPTER Adapter,
IN u8* pPowerlevel);
VOID rtl8192c_PHY_RF6052SetOFDMTxPower(
IN PADAPTER Adapter,
IN u8* pPowerLevel,
IN u8 Channel);
int PHY_RF6052_Config8192C( IN PADAPTER Adapter );
/*--------------------------Exported Function prototype---------------------*/
#endif/* End of HalRf.h */

127
include/rtl8192c_spec.h
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTL8192C_SPEC_H__
#define __RTL8192C_SPEC_H__
#include <drv_conf.h>
//============================================================
// 8192C Regsiter offset definition
//============================================================
//============================================================
//
//============================================================
//-----------------------------------------------------
//
// 0x0000h ~ 0x00FFh System Configuration
//
//-----------------------------------------------------
#define REG_HMEBOX_EXT_0 0x0088
#define REG_HMEBOX_EXT_1 0x008A
#define REG_HMEBOX_EXT_2 0x008C
#define REG_HMEBOX_EXT_3 0x008E
//-----------------------------------------------------
//
// 0x0100h ~ 0x01FFh MACTOP General Configuration
//
//-----------------------------------------------------
//-----------------------------------------------------
//
// 0x0200h ~ 0x027Fh TXDMA Configuration
//
//-----------------------------------------------------
//-----------------------------------------------------
//
// 0x0280h ~ 0x02FFh RXDMA Configuration
//
//-----------------------------------------------------
//-----------------------------------------------------
//
// 0x0300h ~ 0x03FFh PCIe
//
//-----------------------------------------------------
//-----------------------------------------------------
//
// 0x0400h ~ 0x047Fh Protocol Configuration
//
//-----------------------------------------------------
//-----------------------------------------------------
//
// 0x0500h ~ 0x05FFh EDCA Configuration
//
//-----------------------------------------------------
//-----------------------------------------------------
//
// 0x0600h ~ 0x07FFh WMAC Configuration
//
//-----------------------------------------------------
//-----------------------------------------------------
//
// Redifine register definition for compatibility
//
//-----------------------------------------------------
// TODO: use these definition when using REG_xxx naming rule.
// NOTE: DO NOT Remove these definition. Use later.
#ifdef CONFIG_PCI_HCI
#define IMR_RX_MASK (IMR_ROK|IMR_RDU|IMR_RXFOVW)
#define IMR_TX_MASK (IMR_VODOK|IMR_VIDOK|IMR_BEDOK|IMR_BKDOK|IMR_MGNTDOK|IMR_HIGHDOK|IMR_BDOK)
#define RT_BCN_INT_MASKS (IMR_BcnInt | IMR_TBDOK | IMR_TBDER)
#define RT_AC_INT_MASKS (IMR_VIDOK | IMR_VODOK | IMR_BEDOK|IMR_BKDOK)
#endif
//----------------------------------------------------------------------------
// 8192C EEPROM/EFUSE share register definition.
//----------------------------------------------------------------------------
#ifdef CONFIG_PCI_HCI
//
// Interface type.
//
#endif
#define EFUSE_ACCESS_ON 0x69 // For RTL8723 only.
#define EFUSE_ACCESS_OFF 0x00 // For RTL8723 only.
//========================================================
// General definitions
//========================================================
#define MACID_NUM_92C 32
#define CAM_ENTRY_NUM_92C 32
#include "basic_types.h"
#endif /* __RTL8192C_SPEC_H__ */

156
include/rtl8192c_xmit.h
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef _RTL8192C_XMIT_H_
#define _RTL8192C_XMIT_H_
//
//defined for TX DESC Operation
//
#define MAX_TID (15)
//OFFSET 0
#define OFFSET_SZ 0
#define OFFSET_SHT 16
#define BMC BIT(24)
#define LSG BIT(26)
#define FSG BIT(27)
#define OWN BIT(31)
//OFFSET 4
#define PKT_OFFSET_SZ 0
#define BK BIT(6)
#define QSEL_SHT 8
#define Rate_ID_SHT 16
#define NAVUSEHDR BIT(20)
#define PKT_OFFSET_SHT 26
#define HWPC BIT(31)
//OFFSET 8
#define AGG_EN BIT(29)
//OFFSET 12
#define SEQ_SHT 16
//OFFSET 16
#define QoS BIT(6)
#define HW_SEQ_EN BIT(7)
#define USERATE BIT(8)
#define DISDATAFB BIT(10)
#define DATA_SHORT BIT(24)
#define DATA_BW BIT(25)
//OFFSET 20
#define SGI BIT(6)
struct txrpt_ccx_8192c {
/* offset 0 */
u8 retry_cnt:6;
u8 rsvd_0:2;
/* offset 1 */
u8 rts_retry_cnt:6;
u8 rsvd_1:2;
/* offset 2 */
u8 ccx_qtime0;
u8 ccx_qtime1;
/* offset 4 */
u8 missed_pkt_num:5;
u8 rsvd_4:3;
/* offset 5 */
u8 mac_id:5;
u8 des1_fragssn:3;
/* offset 6 */
u8 rpt_pkt_num:5;
u8 pkt_drop:1;
u8 lifetime_over:1;
u8 retry_over:1;
/* offset 7*/
u8 edca_tx_queue:4;
u8 rsvd_7:1;
u8 bmc:1;
u8 pkt_ok:1;
u8 int_ccx:1;
};
#define txrpt_ccx_qtime_8192c(txrpt_ccx) ((txrpt_ccx)->ccx_qtime0+((txrpt_ccx)->ccx_qtime1<<8))
#ifdef CONFIG_XMIT_ACK
void dump_txrpt_ccx_8192c(void *buf);
void handle_txrpt_ccx_8192c(_adapter *adapter, void *buf);
#else
#define dump_txrpt_ccx_8192c(buf) do {} while(0)
#define handle_txrpt_ccx_8192c(adapter, buf) do {} while(0)
#endif
#ifdef CONFIG_USB_HCI
s32 rtl8192cu_init_xmit_priv(_adapter * padapter);
void rtl8192cu_free_xmit_priv(_adapter * padapter);
void rtl8192cu_cal_txdesc_chksum(struct tx_desc *ptxdesc);
s32 rtl8192cu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
s32 rtl8192cu_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe);
s32 rtl8192cu_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe);
s32 rtl8192cu_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
#ifdef CONFIG_HOSTAPD_MLME
s32 rtl8192cu_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt);
#endif
#endif
#ifdef CONFIG_PCI_HCI
s32 rtl8192ce_init_xmit_priv(_adapter * padapter);
void rtl8192ce_free_xmit_priv(_adapter * padapter);
s32 rtl8192ce_enqueue_xmitbuf(struct rtw_tx_ring *ring, struct xmit_buf *pxmitbuf);
struct xmit_buf *rtl8192ce_dequeue_xmitbuf(struct rtw_tx_ring *ring);
void rtl8192ce_xmitframe_resume(_adapter *padapter);
s32 rtl8192ce_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe);
s32 rtl8192ce_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe);
s32 rtl8192ce_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
#ifdef CONFIG_HOSTAPD_MLME
s32 rtl8192ce_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt);
#endif
#endif
#endif

97
include/rtl8192d_cmd.h
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTL8192D_CMD_H_
#define __RTL8192D_CMD_H_
//--------------------------------------------
//3 Host Message Box
//--------------------------------------------
// User Define Message [31:8]
//_SETPWRMODE_PARM
#define SET_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT(__pH2CCmd, 0, 8, __Value)
#define SET_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+1, 0, 8, __Value)
#define SET_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+2, 0, 8, __Value)
//JOINBSSRPT_PARM
#define SET_H2CCMD_JOINBSSRPT_PARM_OPMODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT(__pH2CCmd, 0, 8, __Value)
//_RSVDPAGE_LOC
#define SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT(__pH2CCmd, 0, 8, __Value)
#define SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+1, 0, 8, __Value)
#define SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+2, 0, 8, __Value)
#define SET_H2CCMD_P2P_PS_OFFLOAD_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
#define SET_H2CCMD_P2P_PS_OFFLOAD_ROLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
#define SET_H2CCMD_P2P_PS_OFFLOAD_CTW(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
#define SET_H2CCMD_P2P_PS_OFFLOAD_NOA0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)
#define SET_H2CCMD_P2P_PS_OFFLOAD_NOA1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value)
#define SET_H2CCMD_P2P_PS_OFFLOAD_ALLSTASLEEP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value)
#define SET_H2CCMD_P2P_PS_OFFLOAD_DISCOVERY(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 6, 1, __Value)
// Description: Determine the types of H2C commands that are the same in driver and Fw.
// Fisrt constructed by tynli. 2009.10.09.
typedef enum _RTL8192D_H2C_CMD
{
H2C_92D_AP_OFFLOAD = 0, /*0*/
H2C_SETPWRMODE = 1, /*1*/
H2C_JOINBSSRPT = 2, /*2*/
H2C_RSVDPAGE = 3,
H2C_RSSI_REPORT = 5,
H2C_RA_MASK = 6,
H2C_92D_P2P_PS_OFFLOAD = 8,
H2C_MAC_MODE_SEL = 9,
H2C_PWRM=15,
H2C_P2P_PS_CTW_CMD = 24,
H2C_PathDiv = 26, //PathDiv--NeilChen--2011.07.15
H2C_92D_TSF_SYNC=36,
H2C_92D_RESET_TSF = 43,
H2C_CMD_MAX
}RTL8192D_H2C_CMD;
struct cmd_msg_parm {
u8 eid; //element id
u8 sz; // sz
u8 buf[6];
};
int FillH2CCmd92D(_adapter* padapter, u8 ElementID, u32 CmdLen, u8* pCmdBuffer);
// host message to firmware cmd
void rtl8192d_set_FwPwrMode_cmd(_adapter*padapter, u8 Mode);
void rtl8192d_set_FwJoinBssReport_cmd(_adapter* padapter, u8 mstatus);
u8 rtl8192d_set_rssi_cmd(_adapter*padapter, u8 *param);
void rtl8192d_set_raid_cmd(_adapter*padapter, u32 mask, u8* arg);
void rtl8192d_Add_RateATid(PADAPTER pAdapter, u32 bitmap, u8* arg, u8 rssi_level);
#ifdef CONFIG_P2P
void rtl8192d_set_p2p_ps_offload_cmd(_adapter* padapter, u8 p2p_ps_state);
#endif //CONFIG_P2P
#ifdef CONFIG_TSF_RESET_OFFLOAD
int reset_tsf(PADAPTER Adapter, u8 reset_port );
#endif // CONFIG_TSF_RESET_OFFLOAD
#endif

410
include/rtl8192d_hal.h
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@@ -1,410 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTL8192D_HAL_H__
#define __RTL8192D_HAL_H__
//#include "hal_com.h"
#if 1
#include "hal_data.h"
#else
#include "../hal/OUTSRC/odm_precomp.h"
#endif
#include "rtl8192d_spec.h"
#include "Hal8192DPhyReg.h"
#include "Hal8192DPhyCfg.h"
#include "rtl8192d_rf.h"
#include "rtl8192d_dm.h"
#include "rtl8192d_recv.h"
#include "rtl8192d_xmit.h"
#include "rtl8192d_cmd.h"
#include "rtl8192d_led.h"
#ifdef CONFIG_PCI_HCI
#define RTL819X_DEFAULT_RF_TYPE RF_2T2R
//---------------------------------------------------------------------
// RTL8192DE From file
//---------------------------------------------------------------------
#define RTL8192D_FW_IMG "rtl8192DE\\rtl8192dfw.bin"
#define RTL8192D_PHY_REG "rtl8192DE\\PHY_REG.txt"
#define RTL8192D_PHY_REG_PG "rtl8192DE\\PHY_REG_PG.txt"
#define RTL8192D_PHY_REG_MP "rtl8192DE\\PHY_REG_MP.txt"
#define RTL8192D_AGC_TAB "rtl8192DE\\AGC_TAB.txt"
#define RTL8192D_AGC_TAB_2G "rtl8192DE\\AGC_TAB_2G.txt"
#define RTL8192D_AGC_TAB_5G "rtl8192DE\\AGC_TAB_5G.txt"
#define RTL8192D_PHY_RADIO_A "rtl8192DE\\radio_a.txt"
#define RTL8192D_PHY_RADIO_B "rtl8192DE\\radio_b.txt"
#define RTL8192D_PHY_RADIO_A_intPA "rtl8192DE\\radio_a_intPA.txt"
#define RTL8192D_PHY_RADIO_B_intPA "rtl8192DE\\radio_b_intPA.txt"
#define RTL8192D_PHY_MACREG "rtl8192DE\\MAC_REG.txt"
//---------------------------------------------------------------------
// RTL8192DE From header
//---------------------------------------------------------------------
// Fw Array
#define Rtl8192D_FwImageArray Rtl8192DEFwImgArray
// MAC/BB/PHY Array
#define Rtl8192D_MAC_Array Rtl8192DEMAC_2T_Array
#define Rtl8192D_AGCTAB_Array Rtl8192DEAGCTAB_Array
#define Rtl8192D_AGCTAB_5GArray Rtl8192DEAGCTAB_5GArray
#define Rtl8192D_AGCTAB_2GArray Rtl8192DEAGCTAB_2GArray
#define Rtl8192D_AGCTAB_2TArray Rtl8192DEAGCTAB_2TArray
#define Rtl8192D_AGCTAB_1TArray Rtl8192DEAGCTAB_1TArray
#define Rtl8192D_PHY_REG_2TArray Rtl8192DEPHY_REG_2TArray
#define Rtl8192D_PHY_REG_1TArray Rtl8192DEPHY_REG_1TArray
#define Rtl8192D_PHY_REG_Array_PG Rtl8192DEPHY_REG_Array_PG
#define Rtl8192D_PHY_REG_Array_MP Rtl8192DEPHY_REG_Array_MP
#define Rtl8192D_RadioA_2TArray Rtl8192DERadioA_2TArray
#define Rtl8192D_RadioA_1TArray Rtl8192DERadioA_1TArray
#define Rtl8192D_RadioB_2TArray Rtl8192DERadioB_2TArray
#define Rtl8192D_RadioB_1TArray Rtl8192DERadioB_1TArray
#define Rtl8192D_RadioA_2T_intPAArray Rtl8192DERadioA_2T_intPAArray
#define Rtl8192D_RadioB_2T_intPAArray Rtl8192DERadioB_2T_intPAArray
// Array length
#define Rtl8192D_FwImageArrayLength Rtl8192DEImgArrayLength
#define Rtl8192D_MAC_ArrayLength Rtl8192DEMAC_2T_ArrayLength
#define Rtl8192D_AGCTAB_5GArrayLength Rtl8192DEAGCTAB_5GArrayLength
#define Rtl8192D_AGCTAB_2GArrayLength Rtl8192DEAGCTAB_2GArrayLength
#define Rtl8192D_AGCTAB_2TArrayLength Rtl8192DEAGCTAB_2TArrayLength
#define Rtl8192D_AGCTAB_1TArrayLength Rtl8192DEAGCTAB_1TArrayLength
#define Rtl8192D_AGCTAB_ArrayLength Rtl8192DEAGCTAB_ArrayLength
#define Rtl8192D_PHY_REG_2TArrayLength Rtl8192DEPHY_REG_2TArrayLength
#define Rtl8192D_PHY_REG_1TArrayLength Rtl8192DEPHY_REG_1TArrayLength
#define Rtl8192D_PHY_REG_Array_PGLength Rtl8192DEPHY_REG_Array_PGLength
#define Rtl8192D_PHY_REG_Array_MPLength Rtl8192DEPHY_REG_Array_MPLength
#define Rtl8192D_RadioA_2TArrayLength Rtl8192DERadioA_2TArrayLength
#define Rtl8192D_RadioB_2TArrayLength Rtl8192DERadioB_2TArrayLength
#define Rtl8192D_RadioA_2T_intPAArrayLength Rtl8192DERadioA_2T_intPAArrayLength
#define Rtl8192D_RadioB_2T_intPAArrayLength Rtl8192DERadioB_2T_intPAArrayLength
#elif defined(CONFIG_USB_HCI)
#define RTL819X_DEFAULT_RF_TYPE RF_1T2R
//---------------------------------------------------------------------
// RTL8192DU From file
//---------------------------------------------------------------------
#define RTL8192D_FW_IMG "rtl8192DU\\rtl8192dfw.bin"
#define RTL8192D_PHY_REG "rtl8192DU\\PHY_REG.txt"
#define RTL8192D_PHY_REG_PG "rtl8192DU\\PHY_REG_PG.txt"
#define RTL8192D_PHY_REG_MP "rtl8192DU\\PHY_REG_MP.txt"
#define RTL8192D_AGC_TAB "rtl8192DU\\AGC_TAB.txt"
#define RTL8192D_AGC_TAB_2G "rtl8192DU\\AGC_TAB_2G.txt"
#define RTL8192D_AGC_TAB_5G "rtl8192DU\\AGC_TAB_5G.txt"
#define RTL8192D_PHY_RADIO_A "rtl8192DU\\radio_a.txt"
#define RTL8192D_PHY_RADIO_B "rtl8192DU\\radio_b.txt"
#define RTL8192D_PHY_RADIO_A_intPA "rtl8192DU\\radio_a_intPA.txt"
#define RTL8192D_PHY_RADIO_B_intPA "rtl8192DU\\radio_b_intPA.txt"
#define RTL8192D_PHY_MACREG "rtl8192DU\\MAC_REG.txt"
//---------------------------------------------------------------------
// RTL8192DU From header
//---------------------------------------------------------------------
// Fw Array
#define Rtl8192D_FwImageArray Rtl8192DUFwImgArray
// MAC/BB/PHY Array
#define Rtl8192D_MAC_Array Rtl8192DUMAC_2T_Array
#define Rtl8192D_AGCTAB_Array Rtl8192DUAGCTAB_Array
#define Rtl8192D_AGCTAB_5GArray Rtl8192DUAGCTAB_5GArray
#define Rtl8192D_AGCTAB_2GArray Rtl8192DUAGCTAB_2GArray
#define Rtl8192D_AGCTAB_2TArray Rtl8192DUAGCTAB_2TArray
#define Rtl8192D_AGCTAB_1TArray Rtl8192DUAGCTAB_1TArray
#define Rtl8192D_PHY_REG_2TArray Rtl8192DUPHY_REG_2TArray
#define Rtl8192D_PHY_REG_1TArray Rtl8192DUPHY_REG_1TArray
#define Rtl8192D_PHY_REG_Array_PG Rtl8192DUPHY_REG_Array_PG
#define Rtl8192D_PHY_REG_Array_MP Rtl8192DUPHY_REG_Array_MP
#define Rtl8192D_RadioA_2TArray Rtl8192DURadioA_2TArray
#define Rtl8192D_RadioA_1TArray Rtl8192DURadioA_1TArray
#define Rtl8192D_RadioB_2TArray Rtl8192DURadioB_2TArray
#define Rtl8192D_RadioB_1TArray Rtl8192DURadioB_1TArray
#define Rtl8192D_RadioA_2T_intPAArray Rtl8192DURadioA_2T_intPAArray
#define Rtl8192D_RadioB_2T_intPAArray Rtl8192DURadioB_2T_intPAArray
// Array length
#define Rtl8192D_FwImageArrayLength Rtl8192DUImgArrayLength
#define Rtl8192D_MAC_ArrayLength Rtl8192DUMAC_2T_ArrayLength
#define Rtl8192D_AGCTAB_5GArrayLength Rtl8192DUAGCTAB_5GArrayLength
#define Rtl8192D_AGCTAB_2GArrayLength Rtl8192DUAGCTAB_2GArrayLength
#define Rtl8192D_AGCTAB_2TArrayLength Rtl8192DUAGCTAB_2TArrayLength
#define Rtl8192D_AGCTAB_1TArrayLength Rtl8192DUAGCTAB_1TArrayLength
#define Rtl8192D_AGCTAB_ArrayLength Rtl8192DUAGCTAB_ArrayLength
#define Rtl8192D_PHY_REG_2TArrayLength Rtl8192DUPHY_REG_2TArrayLength
#define Rtl8192D_PHY_REG_1TArrayLength Rtl8192DUPHY_REG_1TArrayLength
#define Rtl8192D_PHY_REG_Array_PGLength Rtl8192DUPHY_REG_Array_PGLength
#define Rtl8192D_PHY_REG_Array_MPLength Rtl8192DUPHY_REG_Array_MPLength
#define Rtl8192D_RadioA_2TArrayLength Rtl8192DURadioA_2TArrayLength
#define Rtl8192D_RadioB_2TArrayLength Rtl8192DURadioB_2TArrayLength
#define Rtl8192D_RadioA_2T_intPAArrayLength Rtl8192DURadioA_2T_intPAArrayLength
#define Rtl8192D_RadioB_2T_intPAArrayLength Rtl8192DURadioB_2T_intPAArrayLength
// The file name "_2T" is for 92CU, "_1T" is for 88CU. Modified by tynli. 2009.11.24.
/* #define Rtl819XFwImageArray Rtl8192DUFwImgArray
#define Rtl819XMAC_Array Rtl8192DUMAC_2TArray
#define Rtl819XAGCTAB_Array Rtl8192DUAGCTAB_Array
#define Rtl819XAGCTAB_5GArray Rtl8192DUAGCTAB_5GArray
#define Rtl819XAGCTAB_2GArray Rtl8192DUAGCTAB_2GArray
#define Rtl819XPHY_REG_2TArray Rtl8192DUPHY_REG_2TArray
#define Rtl819XPHY_REG_1TArray Rtl8192DUPHY_REG_1TArray
#define Rtl819XRadioA_2TArray Rtl8192DURadioA_2TArray
#define Rtl819XRadioA_1TArray Rtl8192DURadioA_1TArray
#define Rtl819XRadioA_2T_intPAArray Rtl8192DURadioA_2T_intPAArray
#define Rtl819XRadioB_2TArray Rtl8192DURadioB_2TArray
#define Rtl819XRadioB_1TArray Rtl8192DURadioB_1TArray
#define Rtl819XRadioB_2T_intPAArray Rtl8192DURadioB_2T_intPAArray
#define Rtl819XPHY_REG_Array_PG Rtl8192DUPHY_REG_Array_PG
#define Rtl819XPHY_REG_Array_MP Rtl8192DUPHY_REG_Array_MP
#define Rtl819XAGCTAB_2TArray Rtl8192DUAGCTAB_2TArray
#define Rtl819XAGCTAB_1TArray Rtl8192DUAGCTAB_1TArray*/
#endif
//
// Check if FW header exists. We do not consider the lower 4 bits in this case.
// By tynli. 2009.12.04.
//
#define IS_FW_HEADER_EXIST_92D(_pFwHdr) ((le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x92C0 ||\
(le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x88C0 ||\
(le16_to_cpu(_pFwHdr->Signature)&0xFFFF) == 0x92D0 ||\
(le16_to_cpu(_pFwHdr->Signature)&0xFFFF) == 0x92D1 ||\
(le16_to_cpu(_pFwHdr->Signature)&0xFFFF) == 0x92D2 ||\
(le16_to_cpu(_pFwHdr->Signature)&0xFFFF) == 0x92D3 )
#define FW_8192D_SIZE 0x8020 // Max FW len = 32k + 32(FW header length).
#define FW_8192D_START_ADDRESS 0x1000
#define FW_8192D_END_ADDRESS 0x1FFF
typedef struct _RT_FIRMWARE_8192D{
FIRMWARE_SOURCE eFWSource;
u8* szFwBuffer;
u32 ulFwLength;
} RT_FIRMWARE_8192D, *PRT_FIRMWARE_8192D;
//
// This structure must be cared byte-ordering
//
// Added by tynli. 2009.12.04.
typedef struct _RT_8192D_FIRMWARE_HDR {//8-byte alinment required
//--- LONG WORD 0 ----
u16 Signature; // 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut
u8 Category; // AP/NIC and USB/PCI
u8 Function; // Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions
u16 Version; // FW Version
u8 Subversion; // FW Subversion, default 0x00
u8 Rsvd1;
//--- LONG WORD 1 ----
u8 Month; // Release time Month field
u8 Date; // Release time Date field
u8 Hour; // Release time Hour field
u8 Minute; // Release time Minute field
u16 RamCodeSize; // The size of RAM code
u16 Rsvd2;
//--- LONG WORD 2 ----
u32 SvnIdx; // The SVN entry index
u32 Rsvd3;
//--- LONG WORD 3 ----
u32 Rsvd4;
u32 Rsvd5;
}RT_8192D_FIRMWARE_HDR, *PRT_8192D_FIRMWARE_HDR;
#define DRIVER_EARLY_INT_TIME_8192D 0x05
#define BCN_DMA_ATIME_INT_TIME_8192D 0x02
typedef enum _BT_CurState{
BT_OFF = 0,
BT_ON = 1,
} BT_CurState, *PBT_CurState;
typedef enum _BT_ServiceType{
BT_SCO = 0,
BT_A2DP = 1,
BT_HID = 2,
BT_HID_Idle = 3,
BT_Scan = 4,
BT_Idle = 5,
BT_OtherAction = 6,
BT_Busy = 7,
BT_OtherBusy = 8,
} BT_ServiceType, *PBT_ServiceType;
typedef struct _BT_COEXIST_STR{
u8 BluetoothCoexist;
u8 BT_Ant_Num;
u8 BT_CoexistType;
u8 BT_State;
u8 BT_CUR_State; //0:on, 1:off
u8 BT_Ant_isolation; //0:good, 1:bad
u8 BT_PapeCtrl; //0:SW, 1:SW/HW dynamic
u8 BT_Service;
u8 BT_RadioSharedType;
u8 Ratio_Tx;
u8 Ratio_PRI;
}BT_COEXIST_STR, *PBT_COEXIST_STR;
// Note: We will divide number of page equally for each queue other than public queue!
#define TX_TOTAL_PAGE_NUMBER_8192D 0xF8
#define TX_PAGE_BOUNDARY (TX_TOTAL_PAGE_NUMBER_8192D + 1)
// For Normal Chip Setting
// (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8192D
#define NORMAL_PAGE_NUM_PUBQ 0x56
// For Test Chip Setting
// (HPQ + LPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8192D
#define TEST_PAGE_NUM_PUBQ 0x89
#define TX_TOTAL_PAGE_NUMBER_92D_DUAL_MAC 0x7A
#define NORMAL_PAGE_NUM_PUBQ_92D_DUAL_MAC 0x5A
#define NORMAL_PAGE_NUM_HPQ_92D_DUAL_MAC 0x10
#define NORMAL_PAGE_NUM_LPQ_92D_DUAL_MAC 0x10
#define NORMAL_PAGE_NUM_NORMALQ_92D_DUAL_MAC 0
#define TX_PAGE_BOUNDARY_DUAL_MAC (TX_TOTAL_PAGE_NUMBER_92D_DUAL_MAC + 1)
// For Test Chip Setting
#define WMM_TEST_TX_TOTAL_PAGE_NUMBER 0xF5
#define WMM_TEST_TX_PAGE_BOUNDARY (WMM_TEST_TX_TOTAL_PAGE_NUMBER + 1) //F6
#define WMM_TEST_PAGE_NUM_PUBQ 0xA3
#define WMM_TEST_PAGE_NUM_HPQ 0x29
#define WMM_TEST_PAGE_NUM_LPQ 0x29
//Note: For Normal Chip Setting ,modify later
#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER 0xF5
#define WMM_NORMAL_TX_PAGE_BOUNDARY (WMM_TEST_TX_TOTAL_PAGE_NUMBER + 1) //F6
#define WMM_NORMAL_PAGE_NUM_PUBQ 0xB0
#define WMM_NORMAL_PAGE_NUM_HPQ 0x29
#define WMM_NORMAL_PAGE_NUM_LPQ 0x1C
#define WMM_NORMAL_PAGE_NUM_NPQ 0x1C
#define WMM_NORMAL_PAGE_NUM_PUBQ_92D 0X65//0x82
#define WMM_NORMAL_PAGE_NUM_HPQ_92D 0X30//0x29
#define WMM_NORMAL_PAGE_NUM_LPQ_92D 0X30
#define WMM_NORMAL_PAGE_NUM_NPQ_92D 0X30
//-------------------------------------------------------------------------
// Chip specific
//-------------------------------------------------------------------------
#define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3)
#define CHIP_BONDING_92C_1T2R 0x1
#define CHIP_BONDING_88C_USB_MCARD 0x2
#define CHIP_BONDING_88C_USB_HP 0x1
//-------------------------------------------------------------------------
// Channel Plan
//-------------------------------------------------------------------------
#define EFUSE_REAL_CONTENT_LEN 1024
#define EFUSE_MAP_LEN 256
#define EFUSE_MAX_SECTION 32
#define EFUSE_MAX_SECTION_BASE 16
// <Roger_Notes> To prevent out of boundary programming case, leave 1byte and program full section
// 9bytes + 1byt + 5bytes and pre 1byte.
// For worst case:
// | 2byte|----8bytes----|1byte|--7bytes--| //92D
#define EFUSE_OOB_PROTECT_BYTES 18 // PG data exclude header, dummy 7 bytes frome CP test and reserved 1byte.
typedef enum _PA_MODE {
PA_MODE_EXTERNAL = 0x00,
PA_MODE_INTERNAL_SP3T = 0x01,
PA_MODE_INTERNAL_SPDT = 0x02
} PA_MODE;
/* Copy from rtl8192c */
enum c2h_id_8192d {
C2H_DBG = 0,
C2H_TSF = 1,
C2H_AP_RPT_RSP = 2,
C2H_CCX_TX_RPT = 3,
C2H_BT_RSSI = 4,
C2H_BT_OP_MODE = 5,
C2H_EXT_RA_RPT = 6,
C2H_HW_INFO_EXCH = 10,
C2H_C2H_H2C_TEST = 11,
C2H_BT_INFO = 12,
C2H_BT_MP_INFO = 15,
MAX_C2HEVENT
};
#ifdef CONFIG_PCI_HCI
//
// Function disabled.
//
#define DF_TX_BIT BIT0
#define DF_RX_BIT BIT1
#define DF_IO_BIT BIT2
#define DF_IO_D3_BIT BIT3
#define RT_DF_TYPE u32
//#define RT_DISABLE_FUNC(__pAdapter, __FuncBits) ((__pAdapter)->DisabledFunctions |= ((RT_DF_TYPE)(__FuncBits)))
//#define RT_ENABLE_FUNC(__pAdapter, __FuncBits) ((__pAdapter)->DisabledFunctions &= (~((RT_DF_TYPE)(__FuncBits))))
//#define RT_IS_FUNC_DISABLED(__pAdapter, __FuncBits) ( (__pAdapter)->DisabledFunctions & (__FuncBits) )
void InterruptRecognized8192DE(PADAPTER Adapter, PRT_ISR_CONTENT pIsrContent);
VOID UpdateInterruptMask8192DE(PADAPTER Adapter, u32 AddMSR, u32 RemoveMSR);
#endif
int FirmwareDownload92D(IN PADAPTER Adapter);
VOID rtl8192d_FirmwareSelfReset(IN PADAPTER Adapter);
void rtl8192d_ReadChipVersion(IN PADAPTER Adapter);
VOID rtl8192d_EfuseParseChnlPlan(PADAPTER Adapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
VOID rtl8192d_ReadTxPowerInfo(PADAPTER Adapter, u8* PROMContent, BOOLEAN AutoLoadFail);
VOID rtl8192d_ResetDualMacSwitchVariables(IN PADAPTER Adapter);
u8 GetEEPROMSize8192D(PADAPTER Adapter);
BOOLEAN PHY_CheckPowerOffFor8192D(PADAPTER Adapter);
VOID PHY_SetPowerOnFor8192D(PADAPTER Adapter);
//void PHY_ConfigMacPhyMode92D(PADAPTER Adapter);
void rtl8192d_free_hal_data(_adapter * padapter);
void rtl8192d_init_default_value(_adapter *adapter);
void rtl8192d_set_hal_ops(struct hal_ops *pHalFunc);
void SetHwReg8192D(_adapter *adapter, u8 variable, u8 *val);
void GetHwReg8192D(_adapter *adapter, u8 variable, u8 *val);
#endif

105
include/rtl8192d_recv.h
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef _RTL8192D_RECV_H_
#define _RTL8192D_RECV_H_
#define RECV_BLK_SZ 512
#define RECV_BLK_CNT 16
#define RECV_BLK_TH RECV_BLK_CNT
#if defined(CONFIG_USB_HCI)
#ifndef MAX_RECVBUF_SZ
#ifdef PLATFORM_OS_CE
#define MAX_RECVBUF_SZ (8192+1024) // 8K+1k
#else
#ifndef CONFIG_MINIMAL_MEMORY_USAGE
//#define MAX_RECVBUF_SZ (32768) // 32k
//#define MAX_RECVBUF_SZ (16384) //16K
//#define MAX_RECVBUF_SZ (10240) //10K
#ifdef CONFIG_PLATFORM_MSTAR
#define MAX_RECVBUF_SZ (8192) // 8K
#else
#define MAX_RECVBUF_SZ (15360) // 15k < 16k
#endif
#else
#define MAX_RECVBUF_SZ (4000) // about 4K
#endif
#endif
#endif //!MAX_RECVBUF_SZ
#elif defined(CONFIG_PCI_HCI)
//#ifndef CONFIG_MINIMAL_MEMORY_USAGE
// #define MAX_RECVBUF_SZ (9100)
//#else
#define MAX_RECVBUF_SZ (4000) // about 4K
//#endif
#endif
struct phy_stat
{
unsigned int phydw0;
unsigned int phydw1;
unsigned int phydw2;
unsigned int phydw3;
unsigned int phydw4;
unsigned int phydw5;
unsigned int phydw6;
unsigned int phydw7;
};
// Rx smooth factor
#define Rx_Smooth_Factor (20)
#ifdef CONFIG_USB_HCI
typedef struct _INTERRUPT_MSG_FORMAT_EX{
unsigned int C2H_MSG0;
unsigned int C2H_MSG1;
unsigned int C2H_MSG2;
unsigned int C2H_MSG3;
unsigned int HISR; // from HISR Reg0x124, read to clear
unsigned int HISRE;// from HISRE Reg0x12c, read to clear
unsigned int MSG_EX;
}INTERRUPT_MSG_FORMAT_EX,*PINTERRUPT_MSG_FORMAT_EX;
void rtl8192du_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf);
int rtl8192du_init_recv_priv(_adapter * padapter);
void rtl8192du_free_recv_priv(_adapter * padapter);
#endif
#ifdef CONFIG_PCI_HCI
int rtl8192de_init_recv_priv(_adapter * padapter);
void rtl8192de_free_recv_priv(_adapter * padapter);
#endif
void rtl8192d_translate_rx_signal_stuff(union recv_frame *precvframe, struct phy_stat *pphy_status);
void rtl8192d_query_rx_desc_status(union recv_frame *precvframe, struct recv_stat *pdesc);
#endif

50
include/rtl8192d_rf.h
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@@ -1,50 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef _RTL8192D_RF_H_
#define _RTL8192D_RF_H_
//
// RF RL6052 Series API
//
void rtl8192d_RF_ChangeTxPath( IN PADAPTER Adapter,
IN u16 DataRate);
void rtl8192d_PHY_RF6052SetBandwidth(
IN PADAPTER Adapter,
IN CHANNEL_WIDTH Bandwidth);
VOID rtl8192d_PHY_RF6052SetCckTxPower(
IN PADAPTER Adapter,
IN u8* pPowerlevel);
VOID rtl8192d_PHY_RF6052SetOFDMTxPower(
IN PADAPTER Adapter,
IN u8* pPowerLevel,
IN u8 Channel);
int PHY_RF6052_Config8192D( IN PADAPTER Adapter );
BOOLEAN rtl8192d_PHY_EnableAnotherPHY(IN PADAPTER Adapter, IN BOOLEAN bMac0);
void rtl8192d_PHY_PowerDownAnotherPHY(IN PADAPTER Adapter, IN BOOLEAN bMac0);
/*--------------------------Exported Function prototype---------------------*/
#endif/* End of HalRf.h */

118
include/rtl8192d_spec.h
View File

@@ -1,118 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTL8192D_SPEC_H__
#define __RTL8192D_SPEC_H__
#include <drv_conf.h>
//============================================================
// 8192D Regsiter offset definition
//============================================================
//============================================================
//
//============================================================
//-----------------------------------------------------
//
// 0x0000h ~ 0x00FFh System Configuration
//
//-----------------------------------------------------
#define REG_HMEBOX_EXT_0 0x0088
#define REG_HMEBOX_EXT_1 0x008A
#define REG_HMEBOX_EXT_2 0x008C
#define REG_HMEBOX_EXT_3 0x008E
//#define REG_MAC_PHY_CTRL_NORMAL 0x00F8
#define REG_MAC0 0x0081
#define REG_MAC1 0x0053
#define FW_MAC0_ready 0x18
#define FW_MAC1_ready 0x1A
#define MAC0_ON BIT7
#define MAC1_ON BIT0
#define mac0_ready BIT0
#define mac1_ready BIT0
//-----------------------------------------------------
//
// 0x0100h ~ 0x01FFh MACTOP General Configuration
//
//-----------------------------------------------------
//-----------------------------------------------------
//
// 0x0200h ~ 0x027Fh TXDMA Configuration
//
//-----------------------------------------------------
//-----------------------------------------------------
//
// 0x0280h ~ 0x02FFh RXDMA Configuration
//
//-----------------------------------------------------
//-----------------------------------------------------
//
// 0x0300h ~ 0x03FFh PCIe
//
//-----------------------------------------------------
//-----------------------------------------------------
//
// 0x0400h ~ 0x047Fh Protocol Configuration
//
//-----------------------------------------------------
//-----------------------------------------------------
//
// 0x0500h ~ 0x05FFh EDCA Configuration
//
//-----------------------------------------------------
//-----------------------------------------------------
//
// 0x0600h ~ 0x07FFh WMAC Configuration
//
//-----------------------------------------------------
//-----------------------------------------------------
//
// 0xFE00h ~ 0xFE55h USB Configuration
//
//-----------------------------------------------------
#ifdef CONFIG_PCI_HCI
#define RT_BCN_INT_MASKS (IMR_BcnInt | IMR_TBDOK | IMR_TBDER)
#define RT_AC_INT_MASKS (IMR_VIDOK | IMR_VODOK | IMR_BEDOK|IMR_BKDOK)
#endif
//========================================================
// General definitions
//========================================================
#define MACID_NUM_92D 32
#define CAM_ENTRY_NUM_92D 32
#include "basic_types.h"
#endif /* __RTL8192D_SPEC_H__ */

174
include/rtl8192d_xmit.h
View File

@@ -1,174 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef _RTL8192D_XMIT_H_
#define _RTL8192D_XMIT_H_
//
//defined for TX DESC Operation
//
#define MAX_TID (15)
//OFFSET 0
#define OFFSET_SZ 0
#define OFFSET_SHT 16
#define BMC BIT(24)
#define LSG BIT(26)
#define FSG BIT(27)
#define OWN BIT(31)
//OFFSET 4
#define PKT_OFFSET_SZ 0
#define BK BIT(6)
#define QSEL_SHT 8
#define Rate_ID_SHT 16
#define NAVUSEHDR BIT(20)
#define PKT_OFFSET_SHT 26
#define HWPC BIT(31)
//OFFSET 8
#define AGG_EN BIT(29)
//OFFSET 12
#define SEQ_SHT 16
//OFFSET 16
#define QoS BIT(6)
#define HW_SEQ_EN BIT(7)
#define USERATE BIT(8)
#define DISDATAFB BIT(10)
#define DATA_SHORT BIT(24)
#define DATA_BW BIT(25)
//OFFSET 20
#define SGI BIT(6)
//Because we open EM for normal case, we just always insert 2*8 bytes.by wl
#ifdef USB_PACKET_OFFSET_SZ
#define USB_92D_DUMMY_OFFSET (PACKET_OFFSET_SZ/8)
#else
#define USB_92D_DUMMY_OFFSET 2
#endif
#define USB_92D_DUMMY_LENGTH (USB_92D_DUMMY_OFFSET * PACKET_OFFSET_SZ)
#define USB_HWDESC_HEADER_LEN (TXDESC_SIZE + USB_92D_DUMMY_LENGTH)
//For 92D early mode
#define SET_EARLYMODE_PKTNUM(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 3, __Value)
#define SET_EARLYMODE_LEN0(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 12, __Value)
#define SET_EARLYMODE_LEN1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 16, 12, __Value)
#define SET_EARLYMODE_LEN2_1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 28, 4, __Value)
#define SET_EARLYMODE_LEN2_2(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 8, __Value)
#define SET_EARLYMODE_LEN3(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 8, 12, __Value)
#define SET_EARLYMODE_LEN4(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 20, 12, __Value)
/* Copy from rtl8192c */
struct txrpt_ccx_8192d {
/* offset 0 */
u8 retry_cnt:6;
u8 rsvd_0:2;
/* offset 1 */
u8 rts_retry_cnt:6;
u8 rsvd_1:2;
/* offset 2 */
u8 ccx_qtime0;
u8 ccx_qtime1;
/* offset 4 */
u8 missed_pkt_num:5;
u8 rsvd_4:3;
/* offset 5 */
u8 mac_id:5;
u8 des1_fragssn:3;
/* offset 6 */
u8 rpt_pkt_num:5;
u8 pkt_drop:1;
u8 lifetime_over:1;
u8 retry_over:1;
/* offset 7*/
u8 edca_tx_queue:4;
u8 rsvd_7:1;
u8 bmc:1;
u8 pkt_ok:1;
u8 int_ccx:1;
};
#define txrpt_ccx_qtime_8192d(txrpt_ccx) ((txrpt_ccx)->ccx_qtime0+((txrpt_ccx)->ccx_qtime1<<8))
#ifdef CONFIG_XMIT_ACK
void dump_txrpt_ccx_8192d(void *buf);
void handle_txrpt_ccx_8192d(_adapter *adapter, void *buf);
#else
#define dump_txrpt_ccx_8192d(buf) do {} while(0)
#define handle_txrpt_ccx_8192d(adapter, buf) do {} while(0)
#endif
#ifdef CONFIG_USB_HCI
s32 rtl8192du_init_xmit_priv(_adapter * padapter);
void rtl8192du_free_xmit_priv(_adapter * padapter);
void rtl8192du_cal_txdesc_chksum(struct tx_desc *ptxdesc);
s32 rtl8192du_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
s32 rtl8192du_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe);
s32 rtl8192du_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe);
s32 rtl8192du_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
#ifdef CONFIG_HOSTAPD_MLME
s32 rtl8192du_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt);
#endif
#endif
#ifdef CONFIG_PCI_HCI
s32 rtl8192de_init_xmit_priv(_adapter * padapter);
void rtl8192de_free_xmit_priv(_adapter * padapter);
s32 rtl8192de_enqueue_xmitbuf(struct rtw_tx_ring *ring, struct xmit_buf *pxmitbuf);
struct xmit_buf *rtl8192de_dequeue_xmitbuf(struct rtw_tx_ring *ring);
void rtl8192de_xmitframe_resume(_adapter *padapter);
s32 rtl8192de_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe);
s32 rtl8192de_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe);
s32 rtl8192de_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
#ifdef CONFIG_HOSTAPD_MLME
s32 rtl8192de_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt);
#endif
#endif//end if CONFIG_PCI_HCI
#endif

72
include/rtl8192e_cmd.h
View File

@@ -42,6 +42,7 @@ typedef enum _RTL8192E_H2C_CMD
H2C_8192E_SAP_PS = 0x26,
H2C_8192E_RA_MASK = 0x40,
H2C_8192E_RSSI_REPORT = 0x42,
H2C_8192E_RA_PARA_ADJUST = 0x46,
H2C_8192E_WO_WLAN = 0x80,
H2C_8192E_REMOTE_WAKE_CTRL = 0x81,
@@ -55,21 +56,6 @@ typedef enum _RTL8192E_H2C_CMD
MAX_8192E_H2CCMD
}RTL8192E_H2C_CMD;
typedef enum _RTL8192E_C2H_EVT
{
C2H_8192E_DBG = 0,
C2H_8192E_LB = 1,
C2H_8192E_TXBF = 2,
C2H_8192E_TX_REPORT = 3,
C2H_8192E_BT_INFO = 9,
C2H_8192E_FW_SWCHNL = 0x10,
C2H_8192E_BT_MP = 11,
C2H_8192E_RA_RPT=12,
MAX_8192E_C2HEVENT
}RTL8192E_C2H_EVT;
struct cmd_msg_parm {
u8 eid; //element id
u8 sz; // sz
@@ -114,13 +100,14 @@ typedef struct _RSVDPAGE_LOC_92E {
//_SETPWRMODE_PARM
#define SET_8192E_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT(__pH2CCmd, 0, 8, __Value)
#define SET_8192E_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
#define SET_8192E_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value)
#define SET_8192E_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value)
#define SET_8192E_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+2, 0, 8, __Value)
#define SET_8192E_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+3, 0, 8, __Value)
#define SET_8192E_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+4, 0, 8, __Value)
#define SET_8192E_H2CCMD_PWRMODE_PARM_BYTE5(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+5, 0, 8, __Value)
#define SET_8192E_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
#define SET_8192E_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
#define SET_8192E_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value)
#define SET_8192E_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
#define SET_8192E_H2CCMD_PWRMODE_PARM_BYTE5(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)
#define GET_8192E_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd) LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)
//_P2P_PS_OFFLOAD
@@ -137,8 +124,9 @@ void rtl8192e_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode);
void rtl8192e_set_FwJoinBssReport_cmd(PADAPTER padapter, u8 mstatus);
u8 rtl8192e_set_rssi_cmd(PADAPTER padapter, u8 *param);
void rtl8192e_set_raid_cmd(PADAPTER padapter, u32 bitmap, u8* arg);
void rtl8192e_Add_RateATid(PADAPTER padapter, u32 bitmap, u8 *arg, u8 rssi_level);
void rtl8192e_Add_RateATid(PADAPTER padapter, u64 rate_bitmap, u8 *arg, u8 rssi_level);
s32 FillH2CCmd_8192E(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
u8 GetTxBufferRsvdPageNum8192E(_adapter *padapter, bool wowlan);
//u8 rtl8192c_set_FwSelectSuspend_cmd(PADAPTER padapter, u8 bfwpoll, u16 period);
s32 c2h_handler_8192e(PADAPTER padapter, u8 *buf);
#ifdef CONFIG_BT_COEXIST
@@ -146,48 +134,20 @@ void rtl8192e_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter);
#endif // CONFIG_BT_COEXIST
#ifdef CONFIG_P2P_PS
void rtl8192e_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);
//void rtl8723a_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);
#endif //CONFIG_P2P
void CheckFwRsvdPageContent(PADAPTER padapter);
void rtl8192e_set_FwMediaStatus_cmd(PADAPTER padapter, u16 mstatus_rpt );
#ifdef CONFIG_TDLS
#ifdef CONFIG_TDLS_CH_SW
void rtl8192e_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable);
#endif
#endif
#ifdef CONFIG_TSF_RESET_OFFLOAD
//u8 rtl8188e_reset_tsf(_adapter *padapter, u8 reset_port);
int reset_tsf(PADAPTER Adapter, u8 reset_port );
#endif // CONFIG_TSF_RESET_OFFLOAD
#ifdef CONFIG_WOWLAN
typedef struct _SETWOWLAN_PARM{
u8 mode;
u8 gpio_index;
u8 gpio_duration;
u8 second_mode;
u8 reserve;
}SETWOWLAN_PARM, *PSETWOWLAN_PARM;
#define FW_WOWLAN_FUN_EN BIT(0)
#define FW_WOWLAN_PATTERN_MATCH BIT(1)
#define FW_WOWLAN_MAGIC_PKT BIT(2)
#define FW_WOWLAN_UNICAST BIT(3)
#define FW_WOWLAN_ALL_PKT_DROP BIT(4)
#define FW_WOWLAN_GPIO_ACTIVE BIT(5)
#define FW_WOWLAN_REKEY_WAKEUP BIT(6)
#define FW_WOWLAN_DEAUTH_WAKEUP BIT(7)
#define FW_WOWLAN_GPIO_WAKEUP_EN BIT(0)
#define FW_FW_PARSE_MAGIC_PKT BIT(1)
#define FW_REMOTE_WAKE_CTRL_EN BIT(0)
#define FW_REALWOWLAN_EN BIT(5)
#endif//CONFIG_WOWLAN
#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
void rtl8192e_set_wowlan_cmd(_adapter* padapter, u8 enable);
void rtl8192e_set_ap_wowlan_cmd(_adapter* padapter, u8 enable);
void rtl8192e_set_ap_ps_wowlan_cmd(_adapter* padapter, u8 enable);
void SetFwRelatedForWoWLAN8192E(_adapter* padapter, u8 bHostIsGoingtoSleep);
#endif
/// TX Feedback Content
#define USEC_UNIT_FOR_8192E_C2H_TX_RPT_QUEUE_TIME 256
@@ -215,4 +175,4 @@ C2HPacketHandler_8192E(
IN u1Byte Length
);
#endif//__RTL8188E_CMD_H__
#endif//__RTL8192E_CMD_H__

4
include/rtl8192e_dm.h
View File

@@ -30,9 +30,5 @@ void rtl8192e_HalDmWatchDog(IN PADAPTER Adapter);
//void rtl8192c_dm_RF_Saving(IN PADAPTER pAdapter, IN u8 bForceInNormal);
#ifdef CONFIG_ANTENNA_DIVERSITY
void AntDivCompare8192e(PADAPTER Adapter, WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src);
u8 AntDivBeforeLink8192e(PADAPTER Adapter );
#endif
#endif

54
include/rtl8192e_hal.h
View File

@@ -22,11 +22,7 @@
//#include "hal_com.h"
#if 1
#include "hal_data.h"
#else
#include "../hal/OUTSRC/odm_precomp.h"
#endif
//include HAL Related header after HAL Related compiling flags
#include "rtl8192e_spec.h"
@@ -132,9 +128,20 @@ typedef struct _RT_FIRMWARE_8192E {
#define DRIVER_EARLY_INT_TIME_8192E 0x05
#define BCN_DMA_ATIME_INT_TIME_8192E 0x02
#define RX_DMA_SIZE_8192E 0x4000 /* 16K*/
#define MAX_RX_DMA_BUFFER_SIZE_8192E 0x3d00 //0x3E80 //0x3FFF // RX 16K reserved for WOW ?
#ifdef CONFIG_WOWLAN
#define RESV_FMWF WKFMCAM_SIZE*MAX_WKFM_NUM /* 16 entries, for each is 24 bytes*/
#else
#define RESV_FMWF 0
#endif
#ifdef CONFIG_FW_C2H_DEBUG
#define RX_DMA_RESERVED_SIZE_8192E 0x100 /* 256B, reserved for c2h debug message*/
#else
#define RX_DMA_RESERVED_SIZE_8192E 0x40 /* 64B, reserved for c2h event(16bytes) or ccx(8 Bytes )*/
#endif
#define MAX_RX_DMA_BUFFER_SIZE_8192E (RX_DMA_SIZE_8192E-RX_DMA_RESERVED_SIZE_8192E) /*RX 16K*/
//For General Reserved Page Number(Beacon Queue is reserved page)
//if (CONFIG_2BCN_EN) Beacon:4, PS-Poll:1, Null Data:1,Prob Rsp:1,Qos Null Data:1
@@ -153,11 +160,22 @@ typedef struct _RT_FIRMWARE_8192E {
#define WOWLAN_PAGE_NUM_8192E 0x0d
#endif
/* Note:
Tx FIFO Size : 64KB
Tx page Size : 256B
Total page numbers : 256(0x100)
*/
#define TOTAL_RSVD_PAGE_NUMBER_8192E (RSVD_PAGE_NUM_8192E+WOWLAN_PAGE_NUM_8192E)
#define TX_TOTAL_PAGE_NUMBER_8192E (0x100 - TOTAL_RSVD_PAGE_NUMBER_8192E)
#define TX_PAGE_BOUNDARY_8192E TX_TOTAL_PAGE_NUMBER_8192E
#define TOTAL_PAGE_NUMBER_8192E (0x100)
#define TX_TOTAL_PAGE_NUMBER_8192E (TOTAL_PAGE_NUMBER_8192E - TOTAL_RSVD_PAGE_NUMBER_8192E)
#define TX_PAGE_BOUNDARY_8192E ( TX_TOTAL_PAGE_NUMBER_8192E ) /* beacon header start address */
#define PAGE_SIZE_TX_92E PAGE_SIZE_256
#define RSVD_PKT_LEN_92E (TOTAL_RSVD_PAGE_NUMBER_8192E *PAGE_SIZE_TX_92E)
#define TX_PAGE_LOAD_FW_BOUNDARY_8192E 0x47 //0xA5
#define TX_PAGE_BOUNDARY_WOWLAN_8192E 0xE0
@@ -219,7 +237,7 @@ typedef struct _RT_FIRMWARE_8192E {
#define EFUSE_BT_MAX_SECTION_8192E 128 // 1024/8
#define EFUSE_PROTECT_BYTES_BANK_8192E 16
#define EFUSE_MAX_BANK_8192E 3
#define EFUSE_MAX_BANK_8192E 3
//===========================================================
#define INCLUDE_MULTI_FUNC_BT(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)
@@ -249,35 +267,41 @@ void Hal_ReadChannelPlan8192E(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFai
void Hal_EfuseParseXtal_8192E(PADAPTER pAdapter,u8* hwinfo,BOOLEAN AutoLoadFail);
void Hal_ReadAntennaDiversity8192E(PADAPTER pAdapter,u8* PROMContent,BOOLEAN AutoLoadFail);
void Hal_ReadPAType_8192E(PADAPTER Adapter,u8* PROMContent, BOOLEAN AutoloadFail);
void Hal_ReadAmplifierType_8192E(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
void Hal_ReadRFEType_8192E(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
void Hal_EfuseParseBTCoexistInfo8192E(PADAPTER Adapter, u8* hwinfo, BOOLEAN AutoLoadFail);
void Hal_EfuseParseKFreeData_8192E(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
u8 Hal_CrystalAFEAdjust(_adapter * Adapter);
BOOLEAN HalDetectPwrDownMode8192E(PADAPTER Adapter);
#ifdef CONFIG_WOWLAN
#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
void Hal_DetectWoWMode(PADAPTER pAdapter);
#endif //CONFIG_WOWLAN
/***********************************************************/
// RTL8192E-MAC Setting
VOID _InitQueueReservedPage_8192E(IN PADAPTER Adapter);
VOID _InitQueuePriority_8192E(IN PADAPTER Adapter);
VOID _InitTxBufferBoundary_8192E(IN PADAPTER Adapter,IN u8 txpktbuf_bndy);
VOID _InitPageBoundary_8192E(IN PADAPTER Adapter);
//VOID _InitTransferPageSize_8192E(IN PADAPTER Adapter);
VOID _InitDriverInfoSize_8192E(IN PADAPTER Adapter,IN u8 drvInfoSize);
VOID _InitRxSetting_8192E(PADAPTER Adapter);
VOID _InitRDGSetting_8192E(PADAPTER Adapter);
void _InitID_8192E(IN PADAPTER Adapter);
VOID _InitNetworkType_8192E(IN PADAPTER Adapter);
VOID _InitWMACSetting_8192E(IN PADAPTER Adapter);
VOID _InitAdaptiveCtrl_8192E(IN PADAPTER Adapter);
VOID _InitAdaptiveCtrl_8192E(IN PADAPTER Adapter);
VOID _InitRateFallback_8192E(IN PADAPTER Adapter);
VOID _InitEDCA_8192E( IN PADAPTER Adapter);
VOID _InitRetryFunction_8192E( IN PADAPTER Adapter);
VOID _BBTurnOnBlock_8192E(IN PADAPTER Adapter);
VOID _InitBeaconParameters_8192E(IN PADAPTER Adapter);
VOID _InitBeaconMaxError_8192E(
IN PADAPTER Adapter,
IN BOOLEAN InfraMode
void _BBTurnOnBlock_8192E(PADAPTER padapter);
);
void SetBeaconRelatedRegisters8192E(PADAPTER padapter);
VOID hal_ReadRFType_8192E(PADAPTER Adapter);
@@ -299,6 +323,7 @@ GetHalDefVar8192E(
IN PVOID pValue
);
void rtl8192e_set_hal_ops(struct hal_ops *pHalFunc);
void init_hal_spec_8192e(_adapter *adapter);
void rtl8192e_init_default_value(_adapter * padapter);
// register
@@ -311,6 +336,11 @@ BOOLEAN InterruptRecognized8192EE(PADAPTER Adapter);
BOOLEAN InterruptRecognized8192EE(PADAPTER Adapter);
u16 get_txdesc_buf_addr(u16 ff_hwaddr);
#endif
#ifdef CONFIG_SDIO_HCI
#ifdef CONFIG_SDIO_TX_ENABLE_AVAL_INT
void _init_available_page_threshold(PADAPTER padapter, u8 numHQ, u8 numNQ, u8 numLQ, u8 numPubQ);
#endif
#endif
#ifdef CONFIG_BT_COEXIST

20
include/rtl8192e_recv.h
View File

@@ -29,10 +29,12 @@
#ifdef CONFIG_MINIMAL_MEMORY_USAGE
#define MAX_RECVBUF_SZ (4000) // about 4K
#else
#ifdef CONFIG_PLATFORM_MSTAR
#define MAX_RECVBUF_SZ (8192) // 8K
#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER
#define MAX_RECVBUF_SZ (rtw_rtkm_get_buff_size()) /*depend rtkm*/
#elif defined(CONFIG_PLATFORM_HISILICON)
#define MAX_RECVBUF_SZ (16384) /* 16k */
#else
#define MAX_RECVBUF_SZ (32768) // 32k
#define MAX_RECVBUF_SZ (32768) /* 32k */
#endif
//#define MAX_RECVBUF_SZ (20480) //20K
//#define MAX_RECVBUF_SZ (10240) //10K
@@ -52,7 +54,7 @@
#elif defined(CONFIG_SDIO_HCI)
#define MAX_RECVBUF_SZ (10240)
#define MAX_RECVBUF_SZ (16384)
#endif
@@ -151,13 +153,12 @@
#ifdef CONFIG_SDIO_HCI
s32 rtl8812s_init_recv_priv(PADAPTER padapter);
void rtl8812s_free_recv_priv(PADAPTER padapter);
void rtl8812s_recv_hdl(PADAPTER padapter, struct recv_buf *precvbuf);
s32 rtl8192es_init_recv_priv(PADAPTER padapter);
void rtl8192es_free_recv_priv(PADAPTER padapter);
void rtl8192es_recv_hdl(PADAPTER padapter, struct recv_buf *precvbuf);
#endif
#ifdef CONFIG_USB_HCI
#define INTERRUPT_MSG_FORMAT_LEN 60
void rtl8192eu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf);
s32 rtl8192eu_init_recv_priv(PADAPTER padapter);
void rtl8192eu_free_recv_priv(PADAPTER padapter);
@@ -172,7 +173,6 @@ void rtl8192ee_free_recv_priv(PADAPTER padapter);
#endif
void rtl8192e_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc);
void rtl8192e_query_rx_phy_status(union recv_frame *prframe, u8 *pphy_stat);
#endif
#endif /* __RTL8192E_RECV_H__ */

12
include/rtl8192e_spec.h
View File

@@ -41,7 +41,7 @@
#define REG_AFE_CTRL2_8192E 0x0028
#define REG_AFE_CTRL3_8192E 0x002c
#define REG_PAD_CTRL1_8192E 0x0064
#define REG_SDIO_CTRL_8192E 0x0070
#define REG_OPT_CTRL_8192E 0x0074
#define REG_RF_B_CTRL_8192E 0x0076
@@ -175,6 +175,10 @@
#define REG_WMAC_LBK_BUF_HD_8192E 0x045D
#define REG_NDPA_OPT_CTRL_8192E 0x045F
#define REG_DATA_SC_8192E 0x0483
#ifdef CONFIG_WOWLAN
#define REG_TXPKTBUF_IV_LOW 0x0484
#define REG_TXPKTBUF_IV_HIGH 0x0488
#endif
#define REG_ARFR2_8192E 0x048C
#define REG_ARFR3_8192E 0x0494
#define REG_TXRPT_START_OFFSET 0x04AC
@@ -314,7 +318,11 @@
//========================================================
#define MACID_NUM_8192E 128
#define CAM_ENTRY_NUM_8192E 64
#define SEC_CAM_ENT_NUM_8192E 64
#define NSS_NUM_8192E 2
#define BAND_CAP_8192E (BAND_CAP_2G)
#define BW_CAP_8192E (BW_CAP_20M | BW_CAP_40M)
#define PROTO_CAP_8192E (PROTO_CAP_11B|PROTO_CAP_11G|PROTO_CAP_11N)
#endif //__RTL8192E_SPEC_H__

30
include/rtl8192e_xmit.h
View File

@@ -355,9 +355,7 @@ typedef struct txdescriptor_8192e
#define SET_EARLYMODE_LEN2_92E(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15, __Value)
#define SET_EARLYMODE_LEN3_92E(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value)
void rtl8192e_fill_fake_txdesc(PADAPTER padapter,u8*pDesc,u32 BufferLen,u8 IsPsPoll,u8 IsBTQosNull);
void rtl8192e_cal_txdesc_chksum(u8 *ptxdesc);
#ifdef CONFIG_USB_HCI
s32 rtl8192eu_init_xmit_priv(PADAPTER padapter);
@@ -382,6 +380,20 @@ s32 rtl8192ee_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
void rtl8192ee_xmit_tasklet(void *priv);
#endif
#if defined(CONFIG_SDIO_HCI)||defined (CONFIG_GSPI_HCI)
s32 rtl8192es_init_xmit_priv(PADAPTER padapter);
void rtl8192es_free_xmit_priv(PADAPTER padapter);
s32 rtl8192es_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
s32 rtl8192es_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
s32 rtl8192es_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
thread_return rtl8192es_xmit_thread(thread_context context);
s32 rtl8192es_xmit_buf_handler(PADAPTER padapter);
#ifdef CONFIG_SDIO_TX_TASKLET
void rtl8192es_xmit_tasklet(void *priv);
#endif
#endif
struct txrpt_ccx_92e {
/* offset 0 */
@@ -420,12 +432,20 @@ struct txrpt_ccx_92e {
#ifdef CONFIG_TX_EARLY_MODE
void UpdateEarlyModeInfo8192E(struct xmit_priv *pxmitpriv,struct xmit_buf *pxmitbuf );
#endif
s32 rtl8192e_init_xmit_priv(_adapter *padapter);
void _dbg_dump_tx_info(_adapter *padapter,int frame_tag,u8 *ptxdesc);
u8 BWMapping_92E(PADAPTER Adapter, struct pkt_attrib *pattrib);
void rtl8192e_fill_fake_txdesc(PADAPTER padapter,u8*pDesc,u32 BufferLen,
u8 IsPsPoll,u8 IsBTQosNull, u8 bDataFrame);
void rtl8192e_cal_txdesc_chksum(u8 *ptxdesc);
u8 BWMapping_92E(PADAPTER Adapter, struct pkt_attrib *pattrib);
u8 SCMapping_92E(PADAPTER Adapter, struct pkt_attrib *pattrib);
void fill_txdesc_phy(PADAPTER padapter, struct pkt_attrib *pattrib, u8 *ptxdesc);
void fill_txdesc_vcs(struct pkt_attrib *pattrib, u8 *ptxdesc);
void fill_txdesc_sectype(struct pkt_attrib *pattrib, u8 *ptxdesc);
void rtl8192e_fixed_rate(_adapter *padapter,u8 *ptxdesc);
#endif //__RTL8192E_XMIT_H__

220
include/rtl8703b_cmd.h Normal file
View File

@@ -0,0 +1,220 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTL8703B_CMD_H__
#define __RTL8703B_CMD_H__
//---------------------------------------------------------------------------------------------------------//
//---------------------------------- H2C CMD DEFINITION ------------------------------------------------//
//---------------------------------------------------------------------------------------------------------//
enum h2c_cmd_8703B{
//Common Class: 000
H2C_8703B_RSVD_PAGE = 0x00,
H2C_8703B_MEDIA_STATUS_RPT = 0x01,
H2C_8703B_SCAN_ENABLE = 0x02,
H2C_8703B_KEEP_ALIVE = 0x03,
H2C_8703B_DISCON_DECISION = 0x04,
H2C_8703B_PSD_OFFLOAD = 0x05,
H2C_8703B_AP_OFFLOAD = 0x08,
H2C_8703B_BCN_RSVDPAGE = 0x09,
H2C_8703B_PROBERSP_RSVDPAGE = 0x0A,
H2C_8703B_FCS_RSVDPAGE = 0x10,
H2C_8703B_FCS_INFO = 0x11,
H2C_8703B_AP_WOW_GPIO_CTRL = 0x13,
//PoweSave Class: 001
H2C_8703B_SET_PWR_MODE = 0x20,
H2C_8703B_PS_TUNING_PARA = 0x21,
H2C_8703B_PS_TUNING_PARA2 = 0x22,
H2C_8703B_P2P_LPS_PARAM = 0x23,
H2C_8703B_P2P_PS_OFFLOAD = 0x24,
H2C_8703B_PS_SCAN_ENABLE = 0x25,
H2C_8703B_SAP_PS_ = 0x26,
H2C_8703B_INACTIVE_PS_ = 0x27, //Inactive_PS
H2C_8703B_FWLPS_IN_IPS_ = 0x28,
//Dynamic Mechanism Class: 010
H2C_8703B_MACID_CFG = 0x40,
H2C_8703B_TXBF = 0x41,
H2C_8703B_RSSI_SETTING = 0x42,
H2C_8703B_AP_REQ_TXRPT = 0x43,
H2C_8703B_INIT_RATE_COLLECT = 0x44,
H2C_8703B_RA_PARA_ADJUST = 0x46,
//BT Class: 011
H2C_8703B_B_TYPE_TDMA = 0x60,
H2C_8703B_BT_INFO = 0x61,
H2C_8703B_FORCE_BT_TXPWR = 0x62,
H2C_8703B_BT_IGNORE_WLANACT = 0x63,
H2C_8703B_DAC_SWING_VALUE = 0x64,
H2C_8703B_ANT_SEL_RSV = 0x65,
H2C_8703B_WL_OPMODE = 0x66,
H2C_8703B_BT_MP_OPER = 0x67,
H2C_8703B_BT_CONTROL = 0x68,
H2C_8703B_BT_WIFI_CTRL = 0x69,
H2C_8703B_BT_FW_PATCH = 0x6A,
H2C_8703B_BT_WLAN_CALIBRATION = 0x6D,
//WOWLAN Class: 100
H2C_8703B_WOWLAN = 0x80,
H2C_8703B_REMOTE_WAKE_CTRL = 0x81,
H2C_8703B_AOAC_GLOBAL_INFO = 0x82,
H2C_8703B_AOAC_RSVD_PAGE = 0x83,
H2C_8703B_AOAC_RSVD_PAGE2 = 0x84,
H2C_8703B_D0_SCAN_OFFLOAD_CTRL = 0x85,
H2C_8703B_D0_SCAN_OFFLOAD_INFO = 0x86,
H2C_8703B_CHNL_SWITCH_OFFLOAD = 0x87,
H2C_8703B_P2P_OFFLOAD_RSVD_PAGE = 0x8A,
H2C_8703B_P2P_OFFLOAD = 0x8B,
H2C_8703B_RESET_TSF = 0xC0,
H2C_8703B_MAXID,
};
//---------------------------------------------------------------------------------------------------------//
//---------------------------------- H2C CMD CONTENT --------------------------------------------------//
//---------------------------------------------------------------------------------------------------------//
//_RSVDPAGE_LOC_CMD_0x00
#define SET_8703B_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
#define SET_8703B_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
#define SET_8703B_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
#define SET_8703B_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
#define SET_8703B_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
//_KEEP_ALIVE_CMD_0x03
#define SET_8703B_H2CCMD_KEEPALIVE_PARM_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
#define SET_8703B_H2CCMD_KEEPALIVE_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
#define SET_8703B_H2CCMD_KEEPALIVE_PARM_PKT_TYPE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
#define SET_8703B_H2CCMD_KEEPALIVE_PARM_CHECK_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
//_DISCONNECT_DECISION_CMD_0x04
#define SET_8703B_H2CCMD_DISCONDECISION_PARM_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
#define SET_8703B_H2CCMD_DISCONDECISION_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
#define SET_8703B_H2CCMD_DISCONDECISION_PARM_CHECK_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
#define SET_8703B_H2CCMD_DISCONDECISION_PARM_TRY_PKT_NUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
// _PWR_MOD_CMD_0x20
#define SET_8703B_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
#define SET_8703B_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value)
#define SET_8703B_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value)
#define SET_8703B_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
#define SET_8703B_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
#define SET_8703B_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value)
#define SET_8703B_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
#define SET_8703B_H2CCMD_PWRMODE_PARM_BYTE5(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)
#define GET_8703B_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd) LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)
// _PS_TUNE_PARAM_CMD_0x21
#define SET_8703B_H2CCMD_PSTUNE_PARM_BCN_TO_LIMIT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
#define SET_8703B_H2CCMD_PSTUNE_PARM_DTIM_TIMEOUT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
#define SET_8703B_H2CCMD_PSTUNE_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 1, __Value)
#define SET_8703B_H2CCMD_PSTUNE_PARM_PS_TIMEOUT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 1, 7, __Value)
#define SET_8703B_H2CCMD_PSTUNE_PARM_DTIM_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
//_MACID_CFG_CMD_0x40
#define SET_8703B_H2CCMD_MACID_CFG_MACID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
#define SET_8703B_H2CCMD_MACID_CFG_RAID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 5, __Value)
#define SET_8703B_H2CCMD_MACID_CFG_SGI_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 7, 1, __Value)
#define SET_8703B_H2CCMD_MACID_CFG_BW(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 2, __Value)
#define SET_8703B_H2CCMD_MACID_CFG_NO_UPDATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 3, 1, __Value)
#define SET_8703B_H2CCMD_MACID_CFG_VHT_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 4, 2, __Value)
#define SET_8703B_H2CCMD_MACID_CFG_DISPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 6, 1, __Value)
#define SET_8703B_H2CCMD_MACID_CFG_DISRA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 7, 1, __Value)
#define SET_8703B_H2CCMD_MACID_CFG_RATE_MASK0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
#define SET_8703B_H2CCMD_MACID_CFG_RATE_MASK1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
#define SET_8703B_H2CCMD_MACID_CFG_RATE_MASK2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+5, 0, 8, __Value)
#define SET_8703B_H2CCMD_MACID_CFG_RATE_MASK3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+6, 0, 8, __Value)
//_RSSI_SETTING_CMD_0x42
#define SET_8703B_H2CCMD_RSSI_SETTING_MACID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
#define SET_8703B_H2CCMD_RSSI_SETTING_RSSI(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 7, __Value)
#define SET_8703B_H2CCMD_RSSI_SETTING_ULDL_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
// _AP_REQ_TXRPT_CMD_0x43
#define SET_8703B_H2CCMD_APREQRPT_PARM_MACID1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
#define SET_8703B_H2CCMD_APREQRPT_PARM_MACID2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
// _FORCE_BT_TXPWR_CMD_0x62
#define SET_8703B_H2CCMD_BT_PWR_IDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
// _FORCE_BT_MP_OPER_CMD_0x67
#define SET_8703B_H2CCMD_BT_MPOPER_VER(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)
#define SET_8703B_H2CCMD_BT_MPOPER_REQNUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value)
#define SET_8703B_H2CCMD_BT_MPOPER_IDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
#define SET_8703B_H2CCMD_BT_MPOPER_PARAM1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
#define SET_8703B_H2CCMD_BT_MPOPER_PARAM2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
#define SET_8703B_H2CCMD_BT_MPOPER_PARAM3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
// _BT_FW_PATCH_0x6A
#define SET_8703B_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value) SET_BITS_TO_LE_2BYTE((pu1Byte)(__pH2CCmd), 0, 16, __Value)
#define SET_8703B_H2CCMD_BT_FW_PATCH_ADDR0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
#define SET_8703B_H2CCMD_BT_FW_PATCH_ADDR1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
#define SET_8703B_H2CCMD_BT_FW_PATCH_ADDR2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
#define SET_8703B_H2CCMD_BT_FW_PATCH_ADDR3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)
//---------------------------------------------------------------------------------------------------------//
//------------------------------------------- Structure --------------------------------------------------//
//---------------------------------------------------------------------------------------------------------//
//---------------------------------------------------------------------------------------------------------//
//---------------------------------- Function Statement --------------------------------------------------//
//---------------------------------------------------------------------------------------------------------//
// host message to firmware cmd
void rtl8703b_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode);
void rtl8703b_set_FwJoinBssRpt_cmd(PADAPTER padapter, u8 mstatus);
void rtl8703b_set_rssi_cmd(PADAPTER padapter, u8 *param);
void rtl8703b_Add_RateATid(PADAPTER pAdapter, u64 rate_bitmap, u8 *arg, u8 rssi_level);
void rtl8703b_fw_try_ap_cmd(PADAPTER padapter, u32 need_ack);
//s32 rtl8703b_set_lowpwr_lps_cmd(PADAPTER padapter, u8 enable);
void rtl8703b_set_FwPsTuneParam_cmd(PADAPTER padapter);
void rtl8703b_set_FwMacIdConfig_cmd(_adapter* padapter, u8 mac_id, u8 raid, u8 bw, u8 sgi, u32 mask);
void rtl8703b_set_FwBtMpOper_cmd(PADAPTER padapter, u8 idx, u8 ver, u8 reqnum, u8 *param);
void rtl8703b_download_rsvd_page(PADAPTER padapter, u8 mstatus);
#ifdef CONFIG_BT_COEXIST
void rtl8703b_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter);
#endif // CONFIG_BT_COEXIST
#ifdef CONFIG_P2P
void rtl8703b_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);
#endif //CONFIG_P2P
void CheckFwRsvdPageContent(PADAPTER padapter);
#ifdef CONFIG_TDLS
#ifdef CONFIG_TDLS_CH_SW
void rtl8703b_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable);
#endif
#endif
#ifdef CONFIG_P2P_WOWLAN
void rtl8703b_set_p2p_wowlan_offload_cmd(PADAPTER padapter);
#endif
void rtl8703b_set_FwPwrModeInIPS_cmd(PADAPTER padapter, u8 cmd_param);
#ifdef CONFIG_TSF_RESET_OFFLOAD
u8 rtl8703b_reset_tsf(_adapter *padapter, u8 reset_port);
#endif // CONFIG_TSF_RESET_OFFLOAD
s32 FillH2CCmd8703B(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
u8 GetTxBufferRsvdPageNum8703B(_adapter *padapter, bool wowlan);
#endif

28
include/rtl8192d_dm.h → include/rtl8703b_dm.h
View File

@@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@@ -17,34 +17,32 @@
*
*
******************************************************************************/
#ifndef __RTL8192D_DM_H__
#define __RTL8192D_DM_H__
#ifndef __RTL8703B_DM_H__
#define __RTL8703B_DM_H__
//============================================================
// Description:
//
// This file is for 92CE/92CU dynamic mechanism only
// This file is for 8703B dynamic mechanism only
//
//
//============================================================
/*------------------------Export global variable----------------------------*/
/*------------------------Export global variable----------------------------*/
/*------------------------Export Marco Definition---------------------------*/
//#define DM_MultiSTA_InitGainChangeNotify(Event) {DM_DigTable.CurMultiSTAConnectState = Event;}
//============================================================
// structure and define
//============================================================
#define Rx_index_mapping_NUM 15
#define index_mapping_NUM 13
//============================================================
// function prototype
//============================================================
void rtl8192d_init_dm_priv(IN PADAPTER Adapter);
void rtl8192d_deinit_dm_priv(IN PADAPTER Adapter);
void rtl8192d_InitHalDm(IN PADAPTER Adapter);
void rtl8192d_HalDmWatchDog(IN PADAPTER Adapter);
void rtl8703b_init_dm_priv(PADAPTER padapter);
void rtl8703b_deinit_dm_priv(PADAPTER padapter);
#endif //__HAL8190PCIDM_H__
void rtl8703b_InitHalDm(PADAPTER padapter);
void rtl8703b_HalDmWatchDog(PADAPTER padapter);
void rtl8703b_HalDmWatchDog_in_LPS(PADAPTER padapter);
void rtl8703b_hal_dm_in_lps(PADAPTER padapter);
#endif

325
include/rtl8703b_hal.h Normal file
View File

@@ -0,0 +1,325 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTL8703B_HAL_H__
#define __RTL8703B_HAL_H__
#include "hal_data.h"
#include "rtl8703b_spec.h"
#include "rtl8703b_rf.h"
#include "rtl8703b_dm.h"
#include "rtl8703b_recv.h"
#include "rtl8703b_xmit.h"
#include "rtl8703b_cmd.h"
#include "rtl8703b_led.h"
#include "Hal8703BPwrSeq.h"
#include "Hal8703BPhyReg.h"
#include "Hal8703BPhyCfg.h"
#ifdef DBG_CONFIG_ERROR_DETECT
#include "rtl8703b_sreset.h"
#endif
//---------------------------------------------------------------------
// RTL8703B From file
//---------------------------------------------------------------------
#define RTL8703B_FW_IMG "rtl8703b/FW_NIC.bin"
#define RTL8703B_FW_WW_IMG "rtl8703b/FW_WoWLAN.bin"
#define RTL8703B_PHY_REG "rtl8703b/PHY_REG.txt"
#define RTL8703B_PHY_RADIO_A "rtl8703b/RadioA.txt"
#define RTL8703B_PHY_RADIO_B "rtl8703b/RadioB.txt"
#define RTL8703B_TXPWR_TRACK "rtl8703b/TxPowerTrack.txt"
#define RTL8703B_AGC_TAB "rtl8703b/AGC_TAB.txt"
#define RTL8703B_PHY_MACREG "rtl8703b/MAC_REG.txt"
#define RTL8703B_PHY_REG_PG "rtl8703b/PHY_REG_PG.txt"
#define RTL8703B_PHY_REG_MP "rtl8703b/PHY_REG_MP.txt"
#define RTL8703B_TXPWR_LMT "rtl8703b/TXPWR_LMT.txt"
//---------------------------------------------------------------------
// RTL8703B From header
//---------------------------------------------------------------------
#if MP_DRIVER == 1
#define Rtl8703B_FwBTImgArray Rtl8703BFwBTImgArray
#define Rtl8703B_FwBTImgArrayLength Rtl8703BFwBTImgArrayLength
#define Rtl8703B_PHY_REG_Array_MP Rtl8703B_PHYREG_Array_MP
#define Rtl8703B_PHY_REG_Array_MPLength Rtl8703B_PHYREG_Array_MPLength
#endif
#define FW_8703B_SIZE 0x8000
#define FW_8703B_START_ADDRESS 0x1000
#define FW_8703B_END_ADDRESS 0x1FFF //0x5FFF
#define IS_FW_HEADER_EXIST_8703B(_pFwHdr) ((le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x03B0)
typedef struct _RT_FIRMWARE {
FIRMWARE_SOURCE eFWSource;
#ifdef CONFIG_EMBEDDED_FWIMG
u8* szFwBuffer;
#else
u8 szFwBuffer[FW_8703B_SIZE];
#endif
u32 ulFwLength;
} RT_FIRMWARE_8703B, *PRT_FIRMWARE_8703B;
//
// This structure must be cared byte-ordering
//
// Added by tynli. 2009.12.04.
typedef struct _RT_8703B_FIRMWARE_HDR
{
// 8-byte alinment required
//--- LONG WORD 0 ----
u16 Signature; // 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut
u8 Category; // AP/NIC and USB/PCI
u8 Function; // Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions
u16 Version; // FW Version
u16 Subversion; // FW Subversion, default 0x00
//--- LONG WORD 1 ----
u8 Month; // Release time Month field
u8 Date; // Release time Date field
u8 Hour; // Release time Hour field
u8 Minute; // Release time Minute field
u16 RamCodeSize; // The size of RAM code
u16 Rsvd2;
//--- LONG WORD 2 ----
u32 SvnIdx; // The SVN entry index
u32 Rsvd3;
//--- LONG WORD 3 ----
u32 Rsvd4;
u32 Rsvd5;
}RT_8703B_FIRMWARE_HDR, *PRT_8703B_FIRMWARE_HDR;
#define DRIVER_EARLY_INT_TIME_8703B 0x05
#define BCN_DMA_ATIME_INT_TIME_8703B 0x02
// for 8703B
// TX 32K, RX 16K, Page size 128B for TX, 8B for RX
#define PAGE_SIZE_TX_8703B 128
#define PAGE_SIZE_RX_8703B 8
#define TX_DMA_SIZE_8703B 0x8000 /* 32K(TX) */
#define RX_DMA_SIZE_8703B 0x4000 /* 16K(RX) */
#ifdef CONFIG_WOWLAN
#define RESV_FMWF WKFMCAM_SIZE*MAX_WKFM_NUM /* 16 entries, for each is 24 bytes*/
#else
#define RESV_FMWF 0
#endif
#ifdef CONFIG_FW_C2H_DEBUG
#define RX_DMA_RESERVED_SIZE_8703B 0x100 // 256B, reserved for c2h debug message
#else
#define RX_DMA_RESERVED_SIZE_8703B 0x80 // 128B, reserved for tx report
#endif
#define RX_DMA_BOUNDARY_8703B (RX_DMA_SIZE_8703B - RX_DMA_RESERVED_SIZE_8703B - 1)
// Note: We will divide number of page equally for each queue other than public queue!
//For General Reserved Page Number(Beacon Queue is reserved page)
//Beacon:2, PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1
#define BCNQ_PAGE_NUM_8703B 0x08
#ifdef CONFIG_CONCURRENT_MODE
#define BCNQ1_PAGE_NUM_8703B 0x08 // 0x04
#else
#define BCNQ1_PAGE_NUM_8703B 0x00
#endif
#ifdef CONFIG_PNO_SUPPORT
#undef BCNQ1_PAGE_NUM_8703B
#define BCNQ1_PAGE_NUM_8703B 0x00 // 0x04
#endif
//For WoWLan , more reserved page
//ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, PNO: 6
#ifdef CONFIG_WOWLAN
#define WOWLAN_PAGE_NUM_8703B 0x07
#else
#define WOWLAN_PAGE_NUM_8703B 0x00
#endif
#ifdef CONFIG_PNO_SUPPORT
#undef WOWLAN_PAGE_NUM_8703B
#define WOWLAN_PAGE_NUM_8703B 0x15
#endif
#ifdef CONFIG_AP_WOWLAN
#define AP_WOWLAN_PAGE_NUM_8703B 0x02
#endif
#define TX_TOTAL_PAGE_NUMBER_8703B (0xFF - BCNQ_PAGE_NUM_8703B - BCNQ1_PAGE_NUM_8703B - WOWLAN_PAGE_NUM_8703B)
#define TX_PAGE_BOUNDARY_8703B (TX_TOTAL_PAGE_NUMBER_8703B + 1)
#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8703B TX_TOTAL_PAGE_NUMBER_8703B
#define WMM_NORMAL_TX_PAGE_BOUNDARY_8703B (WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8703B + 1)
// For Normal Chip Setting
// (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8703B
#define NORMAL_PAGE_NUM_HPQ_8703B 0x0C
#define NORMAL_PAGE_NUM_LPQ_8703B 0x02
#define NORMAL_PAGE_NUM_NPQ_8703B 0x02
// Note: For Normal Chip Setting, modify later
#define WMM_NORMAL_PAGE_NUM_HPQ_8703B 0x30
#define WMM_NORMAL_PAGE_NUM_LPQ_8703B 0x20
#define WMM_NORMAL_PAGE_NUM_NPQ_8703B 0x20
#include "HalVerDef.h"
#include "hal_com.h"
#define EFUSE_OOB_PROTECT_BYTES 15
#define HAL_EFUSE_MEMORY
#define HWSET_MAX_SIZE_8703B 256
#define EFUSE_REAL_CONTENT_LEN_8703B 256
#define EFUSE_MAP_LEN_8703B 512
#define EFUSE_MAX_SECTION_8703B 64
#define EFUSE_IC_ID_OFFSET 506 //For some inferiority IC purpose. added by Roger, 2009.09.02.
#define AVAILABLE_EFUSE_ADDR(addr) (addr < EFUSE_REAL_CONTENT_LEN_8703B)
#define EFUSE_ACCESS_ON 0x69
#define EFUSE_ACCESS_OFF 0x00
//========================================================
// EFUSE for BT definition
//========================================================
#define BANK_NUM 1
#define EFUSE_BT_REAL_BANK_CONTENT_LEN 128
#define EFUSE_BT_REAL_CONTENT_LEN (EFUSE_BT_REAL_BANK_CONTENT_LEN * BANK_NUM)
#define EFUSE_BT_MAP_LEN 1024 // 1k bytes
#define EFUSE_BT_MAX_SECTION (EFUSE_BT_MAP_LEN / 8)
#define EFUSE_PROTECT_BYTES_BANK 16
typedef struct _C2H_EVT_HDR
{
u8 CmdID;
u8 CmdLen;
u8 CmdSeq;
} __attribute__((__packed__)) C2H_EVT_HDR, *PC2H_EVT_HDR;
typedef enum tag_Package_Definition
{
PACKAGE_DEFAULT,
PACKAGE_QFN68,
PACKAGE_TFBGA90,
PACKAGE_TFBGA80,
PACKAGE_TFBGA79
}PACKAGE_TYPE_E;
#define INCLUDE_MULTI_FUNC_BT(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)
#define INCLUDE_MULTI_FUNC_GPS(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)
// rtl8703b_hal_init.c
s32 rtl8703b_FirmwareDownload(PADAPTER padapter, BOOLEAN bUsedWoWLANFw);
void rtl8703b_FirmwareSelfReset(PADAPTER padapter);
void rtl8703b_InitializeFirmwareVars(PADAPTER padapter);
void rtl8703b_InitAntenna_Selection(PADAPTER padapter);
void rtl8703b_DeinitAntenna_Selection(PADAPTER padapter);
void rtl8703b_CheckAntenna_Selection(PADAPTER padapter);
void rtl8703b_init_default_value(PADAPTER padapter);
s32 rtl8703b_InitLLTTable(PADAPTER padapter);
s32 CardDisableHWSM(PADAPTER padapter, u8 resetMCU);
s32 CardDisableWithoutHWSM(PADAPTER padapter);
// EFuse
u8 GetEEPROMSize8703B(PADAPTER padapter);
void Hal_InitPGData(PADAPTER padapter, u8 *PROMContent);
void Hal_EfuseParseIDCode(PADAPTER padapter, u8 *hwinfo);
void Hal_EfuseParseTxPowerInfo_8703B(PADAPTER padapter, u8 *PROMContent, BOOLEAN AutoLoadFail);
void Hal_EfuseParseBTCoexistInfo_8703B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
void Hal_EfuseParseEEPROMVer_8703B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
void Hal_EfuseParseChnlPlan_8703B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
void Hal_EfuseParseCustomerID_8703B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
void Hal_EfuseParseAntennaDiversity_8703B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
void Hal_EfuseParseXtal_8703B(PADAPTER pAdapter, u8 *hwinfo, u8 AutoLoadFail);
void Hal_EfuseParseThermalMeter_8703B(PADAPTER padapter, u8 *hwinfo, u8 AutoLoadFail);
VOID Hal_EfuseParseVoltage_8703B(PADAPTER pAdapter,u8* hwinfo,BOOLEAN AutoLoadFail);
VOID Hal_EfuseParseBoardType_8703B(PADAPTER Adapter, u8* PROMContent,BOOLEAN AutoloadFail);
#ifdef CONFIG_C2H_PACKET_EN
void rtl8703b_c2h_packet_handler(PADAPTER padapter, u8 *pbuf, u16 length);
#endif
void rtl8703b_set_hal_ops(struct hal_ops *pHalFunc);
void init_hal_spec_8703b(_adapter *adapter);
void SetHwReg8703B(PADAPTER padapter, u8 variable, u8 *val);
void GetHwReg8703B(PADAPTER padapter, u8 variable, u8 *val);
#ifdef CONFIG_C2H_PACKET_EN
void SetHwRegWithBuf8703B(PADAPTER padapter, u8 variable, u8 *pbuf, int len);
#endif // CONFIG_C2H_PACKET_EN
u8 SetHalDefVar8703B(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
u8 GetHalDefVar8703B(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
// register
void rtl8703b_InitBeaconParameters(PADAPTER padapter);
void rtl8703b_InitBeaconMaxError(PADAPTER padapter, u8 InfraMode);
void _InitBurstPktLen_8703BS(PADAPTER Adapter);
void _InitLTECoex_8703BS(PADAPTER Adapter);
void _InitMacAPLLSetting_8703B(PADAPTER Adapter);
void _8051Reset8703(PADAPTER padapter);
#ifdef CONFIG_WOWLAN
void Hal_DetectWoWMode(PADAPTER pAdapter);
#endif //CONFIG_WOWLAN
void rtl8703b_start_thread(_adapter *padapter);
void rtl8703b_stop_thread(_adapter *padapter);
#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)
void rtl8703bs_init_checkbthang_workqueue(_adapter * adapter);
void rtl8703bs_free_checkbthang_workqueue(_adapter * adapter);
void rtl8703bs_cancle_checkbthang_workqueue(_adapter * adapter);
void rtl8703bs_hal_check_bt_hang(_adapter * adapter);
#endif
#ifdef CONFIG_GPIO_WAKEUP
void HalSetOutPutGPIO(PADAPTER padapter, u8 index, u8 OutPutValue);
#endif
int FirmwareDownloadBT(IN PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware);
void CCX_FwC2HTxRpt_8703b(PADAPTER padapter, u8 *pdata, u8 len);
s32 c2h_id_filter_ccx_8703b(u8 *buf);
s32 c2h_handler_8703b(PADAPTER padapter, u8 *pC2hEvent);
u8 MRateToHwRate8703B(u8 rate);
u8 HwRateToMRate8703B(u8 rate);
void Hal_ReadRFGainOffset(PADAPTER pAdapter,u8* hwinfo,BOOLEAN AutoLoadFail);
#ifdef CONFIG_PCI_HCI
BOOLEAN InterruptRecognized8703BE(PADAPTER Adapter);
VOID UpdateInterruptMask8703BE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
#endif
#endif

86
include/rtl8192c_led.h → include/rtl8703b_led.h
View File

@@ -1,37 +1,49 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTL8192C_LED_H_
#define __RTL8192C_LED_H_
//================================================================================
// Interface to manipulate LED objects.
//================================================================================
#ifdef CONFIG_USB_HCI
void rtl8192cu_InitSwLeds(_adapter *padapter);
void rtl8192cu_DeInitSwLeds(_adapter *padapter);
#endif
#ifdef CONFIG_PCI_HCI
void rtl8192ce_InitSwLeds(_adapter *padapter);
void rtl8192ce_DeInitSwLeds(_adapter *padapter);
#endif
#endif
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTL8703B_LED_H__
#define __RTL8703B_LED_H__
#include <drv_conf.h>
#include <osdep_service.h>
#include <drv_types.h>
//================================================================================
// Interface to manipulate LED objects.
//================================================================================
#ifdef CONFIG_USB_HCI
void rtl8703bu_InitSwLeds(PADAPTER padapter);
void rtl8703bu_DeInitSwLeds(PADAPTER padapter);
#endif
#ifdef CONFIG_SDIO_HCI
void rtl8703bs_InitSwLeds(PADAPTER padapter);
void rtl8703bs_DeInitSwLeds(PADAPTER padapter);
#endif
#ifdef CONFIG_GSPI_HCI
void rtl8703bs_InitSwLeds(PADAPTER padapter);
void rtl8703bs_DeInitSwLeds(PADAPTER padapter);
#endif
#ifdef CONFIG_PCI_HCI
void rtl8703be_InitSwLeds(PADAPTER padapter);
void rtl8703be_DeInitSwLeds(PADAPTER padapter);
#endif
#endif

205
include/rtl8192c_recv.h → include/rtl8703b_recv.h
View File

@@ -1,113 +1,92 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef _RTL8192C_RECV_H_
#define _RTL8192C_RECV_H_
#define RECV_BLK_SZ 512
#define RECV_BLK_CNT 16
#define RECV_BLK_TH RECV_BLK_CNT
#if defined(CONFIG_USB_HCI)
#ifndef MAX_RECVBUF_SZ
#ifdef PLATFORM_OS_CE
#define MAX_RECVBUF_SZ (8192+1024) // 8K+1k
#else
#ifndef CONFIG_MINIMAL_MEMORY_USAGE
//#define MAX_RECVBUF_SZ (32768) // 32k
//#define MAX_RECVBUF_SZ (16384) //16K
//#define MAX_RECVBUF_SZ (10240) //10K
#ifdef CONFIG_PLATFORM_MSTAR
#define MAX_RECVBUF_SZ (8192) // 8K
#else
#define MAX_RECVBUF_SZ (15360) // 15k < 16k
#endif
//#define MAX_RECVBUF_SZ (8192+1024) // 8K+1k
#else
#define MAX_RECVBUF_SZ (4000) // about 4K
#endif
#endif
#endif //!MAX_RECVBUF_SZ
#elif defined(CONFIG_PCI_HCI)
//#ifndef CONFIG_MINIMAL_MEMORY_USAGE
// #define MAX_RECVBUF_SZ (9100)
//#else
#define MAX_RECVBUF_SZ (4000) // about 4K
//#endif
#elif defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
#define MAX_RECVBUF_SZ (10240)
#endif
struct phy_stat
{
unsigned int phydw0;
unsigned int phydw1;
unsigned int phydw2;
unsigned int phydw3;
unsigned int phydw4;
unsigned int phydw5;
unsigned int phydw6;
unsigned int phydw7;
};
// Rx smooth factor
#define Rx_Smooth_Factor (20)
#ifdef CONFIG_USB_HCI
typedef struct _INTERRUPT_MSG_FORMAT_EX{
unsigned int C2H_MSG0;
unsigned int C2H_MSG1;
unsigned int C2H_MSG2;
unsigned int C2H_MSG3;
unsigned int HISR; // from HISR Reg0x124, read to clear
unsigned int HISRE;// from HISRE Reg0x12c, read to clear
unsigned int MSG_EX;
}INTERRUPT_MSG_FORMAT_EX,*PINTERRUPT_MSG_FORMAT_EX;
void rtl8192cu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf);
int rtl8192cu_init_recv_priv(_adapter * padapter);
void rtl8192cu_free_recv_priv(_adapter * padapter);
#endif
#ifdef CONFIG_PCI_HCI
int rtl8192ce_init_recv_priv(_adapter * padapter);
void rtl8192ce_free_recv_priv(_adapter * padapter);
#endif
void rtl8192c_translate_rx_signal_stuff(union recv_frame *precvframe, struct phy_stat *pphy_status);
void rtl8192c_query_rx_desc_status(union recv_frame *precvframe, struct recv_stat *pdesc);
#endif
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTL8703B_RECV_H__
#define __RTL8703B_RECV_H__
#define RECV_BLK_SZ 512
#define RECV_BLK_CNT 16
#define RECV_BLK_TH RECV_BLK_CNT
#if defined(CONFIG_USB_HCI)
#ifndef MAX_RECVBUF_SZ
#ifdef PLATFORM_OS_CE
#define MAX_RECVBUF_SZ (8192+1024) // 8K+1k
#else
#ifndef CONFIG_MINIMAL_MEMORY_USAGE
//#define MAX_RECVBUF_SZ (32768) // 32k
//#define MAX_RECVBUF_SZ (16384) //16K
//#define MAX_RECVBUF_SZ (10240) //10K
#ifdef CONFIG_PLATFORM_MSTAR
#define MAX_RECVBUF_SZ (8192) // 8K
#else
#define MAX_RECVBUF_SZ (15360) // 15k < 16k
#endif
//#define MAX_RECVBUF_SZ (8192+1024) // 8K+1k
#else
#define MAX_RECVBUF_SZ (4000) // about 4K
#endif
#endif
#endif //!MAX_RECVBUF_SZ
#elif defined(CONFIG_PCI_HCI)
//#ifndef CONFIG_MINIMAL_MEMORY_USAGE
// #define MAX_RECVBUF_SZ (9100)
//#else
#define MAX_RECVBUF_SZ (4000) // about 4K
//#endif
#elif defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
#define MAX_RECVBUF_SZ (10240)
#endif
// Rx smooth factor
#define Rx_Smooth_Factor (20)
#ifdef CONFIG_SDIO_HCI
#ifndef CONFIG_SDIO_RX_COPY
#undef MAX_RECVBUF_SZ
#define MAX_RECVBUF_SZ (RX_DMA_SIZE_8703B - RX_DMA_RESERVED_SIZE_8703B)
#endif // !CONFIG_SDIO_RX_COPY
#endif // CONFIG_SDIO_HCI
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
s32 rtl8703bs_init_recv_priv(PADAPTER padapter);
void rtl8703bs_free_recv_priv(PADAPTER padapter);
#endif
#ifdef CONFIG_USB_HCI
int rtl8703bu_init_recv_priv(_adapter *padapter);
void rtl8703bu_free_recv_priv (_adapter *padapter);
void rtl8703bu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf);
#endif
#ifdef CONFIG_PCI_HCI
s32 rtl8703be_init_recv_priv(PADAPTER padapter);
void rtl8703be_free_recv_priv(PADAPTER padapter);
#endif
void rtl8703b_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc);
#endif /* __RTL8703B_RECV_H__ */

11
include/rtl8723a_pg.h → include/rtl8703b_rf.h
View File

@@ -17,8 +17,15 @@
*
*
******************************************************************************/
#ifndef __RTL8723A_PG_H__
#define __RTL8723A_PG_H__
#ifndef __RTL8703B_RF_H__
#define __RTL8703B_RF_H__
int PHY_RF6052_Config8703B( IN PADAPTER Adapter );
VOID
PHY_RF6052SetBandwidth8703B(
IN PADAPTER Adapter,
IN CHANNEL_WIDTH Bandwidth);
#endif

480
include/rtl8703b_spec.h Normal file
View File

@@ -0,0 +1,480 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*******************************************************************************/
#ifndef __RTL8703B_SPEC_H__
#define __RTL8703B_SPEC_H__
#include <drv_conf.h>
#define HAL_NAV_UPPER_UNIT_8703B 128 // micro-second
//-----------------------------------------------------
//
// 0x0000h ~ 0x00FFh System Configuration
//
//-----------------------------------------------------
#define REG_SYS_ISO_CTRL_8703B 0x0000 // 2 Byte
#define REG_SYS_FUNC_EN_8703B 0x0002 // 2 Byte
#define REG_APS_FSMCO_8703B 0x0004 // 4 Byte
#define REG_SYS_CLKR_8703B 0x0008 // 2 Byte
#define REG_9346CR_8703B 0x000A // 2 Byte
#define REG_EE_VPD_8703B 0x000C // 2 Byte
#define REG_AFE_MISC_8703B 0x0010 // 1 Byte
#define REG_SPS0_CTRL_8703B 0x0011 // 7 Byte
#define REG_SPS_OCP_CFG_8703B 0x0018 // 4 Byte
#define REG_RSV_CTRL_8703B 0x001C // 3 Byte
#define REG_RF_CTRL_8703B 0x001F // 1 Byte
#define REG_LPLDO_CTRL_8703B 0x0023 // 1 Byte
#define REG_AFE_XTAL_CTRL_8703B 0x0024 // 4 Byte
#define REG_AFE_PLL_CTRL_8703B 0x0028 // 4 Byte
#define REG_MAC_PLL_CTRL_EXT_8703B 0x002c // 4 Byte
#define REG_EFUSE_CTRL_8703B 0x0030
#define REG_EFUSE_TEST_8703B 0x0034
#define REG_PWR_DATA_8703B 0x0038
#define REG_CAL_TIMER_8703B 0x003C
#define REG_ACLK_MON_8703B 0x003E
#define REG_GPIO_MUXCFG_8703B 0x0040
#define REG_GPIO_IO_SEL_8703B 0x0042
#define REG_MAC_PINMUX_CFG_8703B 0x0043
#define REG_GPIO_PIN_CTRL_8703B 0x0044
#define REG_GPIO_INTM_8703B 0x0048
#define REG_LEDCFG0_8703B 0x004C
#define REG_LEDCFG1_8703B 0x004D
#define REG_LEDCFG2_8703B 0x004E
#define REG_LEDCFG3_8703B 0x004F
#define REG_FSIMR_8703B 0x0050
#define REG_FSISR_8703B 0x0054
#define REG_HSIMR_8703B 0x0058
#define REG_HSISR_8703B 0x005c
#define REG_GPIO_EXT_CTRL 0x0060
#define REG_PAD_CTRL1_8703B 0x0064
#define REG_MULTI_FUNC_CTRL_8703B 0x0068
#define REG_GPIO_STATUS_8703B 0x006C
#define REG_SDIO_CTRL_8703B 0x0070
#define REG_OPT_CTRL_8703B 0x0074
#define REG_AFE_CTRL_4_8703B 0x0078
#define REG_MCUFWDL_8703B 0x0080
#define REG_HMEBOX_DBG_0_8703B 0x0088
#define REG_HMEBOX_DBG_1_8703B 0x008A
#define REG_HMEBOX_DBG_2_8703B 0x008C
#define REG_HMEBOX_DBG_3_8703B 0x008E
#define REG_HIMR0_8703B 0x00B0
#define REG_HISR0_8703B 0x00B4
#define REG_HIMR1_8703B 0x00B8
#define REG_HISR1_8703B 0x00BC
#define REG_PMC_DBG_CTRL2_8703B 0x00CC
#define REG_EFUSE_BURN_GNT_8703B 0x00CF
#define REG_HPON_FSM_8703B 0x00EC
#define REG_SYS_CFG_8703B 0x00F0
#define REG_SYS_CFG1_8703B 0x00FC
#define REG_ROM_VERSION 0x00FD
//-----------------------------------------------------
//
// 0x0100h ~ 0x01FFh MACTOP General Configuration
//
//-----------------------------------------------------
#define REG_C2HEVT_CMD_ID_8703B 0x01A0
#define REG_C2HEVT_CMD_SEQ_88XX 0x01A1
#define REG_C2hEVT_CMD_CONTENT_88XX 0x01A2
#define REG_C2HEVT_CMD_LEN_8703B 0x01AE
#define REG_C2HEVT_CMD_LEN_88XX REG_C2HEVT_CMD_LEN_8703B
#define REG_C2HEVT_CLEAR_8703B 0x01AF
#define REG_MCUTST_1_8703B 0x01C0
#define REG_WOWLAN_WAKE_REASON 0x01C7
#define REG_FMETHR_8703B 0x01C8
#define REG_HMETFR_8703B 0x01CC
#define REG_HMEBOX_0_8703B 0x01D0
#define REG_HMEBOX_1_8703B 0x01D4
#define REG_HMEBOX_2_8703B 0x01D8
#define REG_HMEBOX_3_8703B 0x01DC
#define REG_LLT_INIT_8703B 0x01E0
#define REG_HMEBOX_EXT0_8703B 0x01F0
#define REG_HMEBOX_EXT1_8703B 0x01F4
#define REG_HMEBOX_EXT2_8703B 0x01F8
#define REG_HMEBOX_EXT3_8703B 0x01FC
//-----------------------------------------------------
//
// 0x0200h ~ 0x027Fh TXDMA Configuration
//
//-----------------------------------------------------
#define REG_RQPN_8703B 0x0200
#define REG_FIFOPAGE_8703B 0x0204
#define REG_DWBCN0_CTRL_8703B REG_TDECTRL
#define REG_TXDMA_OFFSET_CHK_8703B 0x020C
#define REG_TXDMA_STATUS_8703B 0x0210
#define REG_RQPN_NPQ_8703B 0x0214
#define REG_DWBCN1_CTRL_8703B 0x0228
//-----------------------------------------------------
//
// 0x0280h ~ 0x02FFh RXDMA Configuration
//
//-----------------------------------------------------
#define REG_RXDMA_AGG_PG_TH_8703B 0x0280
#define REG_FW_UPD_RDPTR_8703B 0x0284 // FW shall update this register before FW write RXPKT_RELEASE_POLL to 1
#define REG_RXDMA_CONTROL_8703B 0x0286 // Control the RX DMA.
#define REG_RXPKT_NUM_8703B 0x0287 // The number of packets in RXPKTBUF.
#define REG_RXDMA_STATUS_8703B 0x0288
#define REG_RXDMA_MODE_CTRL_8703B 0x0290
#define REG_EARLY_MODE_CONTROL_8703B 0x02BC
#define REG_RSVD5_8703B 0x02F0
#define REG_RSVD6_8703B 0x02F4
//-----------------------------------------------------
//
// 0x0300h ~ 0x03FFh PCIe
//
//-----------------------------------------------------
#define REG_PCIE_CTRL_REG_8703B 0x0300
#define REG_INT_MIG_8703B 0x0304 // Interrupt Migration
#define REG_BCNQ_DESA_8703B 0x0308 // TX Beacon Descriptor Address
#define REG_HQ_DESA_8703B 0x0310 // TX High Queue Descriptor Address
#define REG_MGQ_DESA_8703B 0x0318 // TX Manage Queue Descriptor Address
#define REG_VOQ_DESA_8703B 0x0320 // TX VO Queue Descriptor Address
#define REG_VIQ_DESA_8703B 0x0328 // TX VI Queue Descriptor Address
#define REG_BEQ_DESA_8703B 0x0330 // TX BE Queue Descriptor Address
#define REG_BKQ_DESA_8703B 0x0338 // TX BK Queue Descriptor Address
#define REG_RX_DESA_8703B 0x0340 // RX Queue Descriptor Address
#define REG_DBI_WDATA_8703B 0x0348 // DBI Write Data
#define REG_DBI_RDATA_8703B 0x034C // DBI Read Data
#define REG_DBI_ADDR_8703B 0x0350 // DBI Address
#define REG_DBI_FLAG_8703B 0x0352 // DBI Read/Write Flag
#define REG_MDIO_WDATA_8703B 0x0354 // MDIO for Write PCIE PHY
#define REG_MDIO_RDATA_8703B 0x0356 // MDIO for Reads PCIE PHY
#define REG_MDIO_CTL_8703B 0x0358 // MDIO for Control
#define REG_DBG_SEL_8703B 0x0360 // Debug Selection Register
#define REG_PCIE_HRPWM_8703B 0x0361 //PCIe RPWM
#define REG_PCIE_HCPWM_8703B 0x0363 //PCIe CPWM
#define REG_PCIE_MULTIFET_CTRL_8703B 0x036A //PCIE Multi-Fethc Control
//-----------------------------------------------------
//
// 0x0400h ~ 0x047Fh Protocol Configuration
//
//-----------------------------------------------------
#define REG_VOQ_INFORMATION_8703B 0x0400
#define REG_VIQ_INFORMATION_8703B 0x0404
#define REG_BEQ_INFORMATION_8703B 0x0408
#define REG_BKQ_INFORMATION_8703B 0x040C
#define REG_MGQ_INFORMATION_8703B 0x0410
#define REG_HGQ_INFORMATION_8703B 0x0414
#define REG_BCNQ_INFORMATION_8703B 0x0418
#define REG_TXPKT_EMPTY_8703B 0x041A
#define REG_FWHW_TXQ_CTRL_8703B 0x0420
#define REG_HWSEQ_CTRL_8703B 0x0423
#define REG_TXPKTBUF_BCNQ_BDNY_8703B 0x0424
#define REG_TXPKTBUF_MGQ_BDNY_8703B 0x0425
#define REG_LIFECTRL_CTRL_8703B 0x0426
#define REG_MULTI_BCNQ_OFFSET_8703B 0x0427
#define REG_SPEC_SIFS_8703B 0x0428
#define REG_RL_8703B 0x042A
#define REG_TXBF_CTRL_8703B 0x042C
#define REG_DARFRC_8703B 0x0430
#define REG_RARFRC_8703B 0x0438
#define REG_RRSR_8703B 0x0440
#define REG_ARFR0_8703B 0x0444
#define REG_ARFR1_8703B 0x044C
#define REG_CCK_CHECK_8703B 0x0454
#define REG_AMPDU_MAX_TIME_8703B 0x0456
#define REG_TXPKTBUF_BCNQ_BDNY1_8703B 0x0457
#define REG_AMPDU_MAX_LENGTH_8703B 0x0458
#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8703B 0x045D
#define REG_NDPA_OPT_CTRL_8703B 0x045F
#define REG_FAST_EDCA_CTRL_8703B 0x0460
#define REG_RD_RESP_PKT_TH_8703B 0x0463
#define REG_DATA_SC_8703B 0x0483
#ifdef CONFIG_WOWLAN
#define REG_TXPKTBUF_IV_LOW 0x0484
#define REG_TXPKTBUF_IV_HIGH 0x0488
#endif
#define REG_TXRPT_START_OFFSET 0x04AC
#define REG_POWER_STAGE1_8703B 0x04B4
#define REG_POWER_STAGE2_8703B 0x04B8
#define REG_AMPDU_BURST_MODE_8703B 0x04BC
#define REG_PKT_VO_VI_LIFE_TIME_8703B 0x04C0
#define REG_PKT_BE_BK_LIFE_TIME_8703B 0x04C2
#define REG_STBC_SETTING_8703B 0x04C4
#define REG_HT_SINGLE_AMPDU_8703B 0x04C7
#define REG_PROT_MODE_CTRL_8703B 0x04C8
#define REG_MAX_AGGR_NUM_8703B 0x04CA
#define REG_RTS_MAX_AGGR_NUM_8703B 0x04CB
#define REG_BAR_MODE_CTRL_8703B 0x04CC
#define REG_RA_TRY_RATE_AGG_LMT_8703B 0x04CF
#define REG_MACID_PKT_DROP0_8703B 0x04D0
#define REG_MACID_PKT_SLEEP_8703B 0x04D4
//-----------------------------------------------------
//
// 0x0500h ~ 0x05FFh EDCA Configuration
//
//-----------------------------------------------------
#define REG_EDCA_VO_PARAM_8703B 0x0500
#define REG_EDCA_VI_PARAM_8703B 0x0504
#define REG_EDCA_BE_PARAM_8703B 0x0508
#define REG_EDCA_BK_PARAM_8703B 0x050C
#define REG_BCNTCFG_8703B 0x0510
#define REG_PIFS_8703B 0x0512
#define REG_RDG_PIFS_8703B 0x0513
#define REG_SIFS_CTX_8703B 0x0514
#define REG_SIFS_TRX_8703B 0x0516
#define REG_AGGR_BREAK_TIME_8703B 0x051A
#define REG_SLOT_8703B 0x051B
#define REG_TX_PTCL_CTRL_8703B 0x0520
#define REG_TXPAUSE_8703B 0x0522
#define REG_DIS_TXREQ_CLR_8703B 0x0523
#define REG_RD_CTRL_8703B 0x0524
//
// Format for offset 540h-542h:
// [3:0]: TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT.
// [7:4]: Reserved.
// [19:8]: TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet.
// [23:20]: Reserved
// Description:
// |
// |<--Setup--|--Hold------------>|
// --------------|----------------------
// |
// TBTT
// Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold.
// Described by Designer Tim and Bruce, 2011-01-14.
//
#define REG_TBTT_PROHIBIT_8703B 0x0540
#define REG_RD_NAV_NXT_8703B 0x0544
#define REG_NAV_PROT_LEN_8703B 0x0546
#define REG_BCN_CTRL_8703B 0x0550
#define REG_BCN_CTRL_1_8703B 0x0551
#define REG_MBID_NUM_8703B 0x0552
#define REG_DUAL_TSF_RST_8703B 0x0553
#define REG_BCN_INTERVAL_8703B 0x0554
#define REG_DRVERLYINT_8703B 0x0558
#define REG_BCNDMATIM_8703B 0x0559
#define REG_ATIMWND_8703B 0x055A
#define REG_USTIME_TSF_8703B 0x055C
#define REG_BCN_MAX_ERR_8703B 0x055D
#define REG_RXTSF_OFFSET_CCK_8703B 0x055E
#define REG_RXTSF_OFFSET_OFDM_8703B 0x055F
#define REG_TSFTR_8703B 0x0560
#define REG_CTWND_8703B 0x0572
#define REG_SECONDARY_CCA_CTRL_8703B 0x0577
#define REG_PSTIMER_8703B 0x0580
#define REG_TIMER0_8703B 0x0584
#define REG_TIMER1_8703B 0x0588
#define REG_ACMHWCTRL_8703B 0x05C0
#define REG_SCH_TXCMD_8703B 0x05F8
//-----------------------------------------------------
//
// 0x0600h ~ 0x07FFh WMAC Configuration
//
//-----------------------------------------------------
#define REG_MAC_CR_8703B 0x0600
#define REG_TCR_8703B 0x0604
#define REG_RCR_8703B 0x0608
#define REG_RX_PKT_LIMIT_8703B 0x060C
#define REG_RX_DLK_TIME_8703B 0x060D
#define REG_RX_DRVINFO_SZ_8703B 0x060F
#define REG_MACID_8703B 0x0610
#define REG_BSSID_8703B 0x0618
#define REG_MAR_8703B 0x0620
#define REG_MBIDCAMCFG_8703B 0x0628
#define REG_WOWLAN_GTK_DBG1 0x630
#define REG_WOWLAN_GTK_DBG2 0x634
#define REG_USTIME_EDCA_8703B 0x0638
#define REG_MAC_SPEC_SIFS_8703B 0x063A
#define REG_RESP_SIFP_CCK_8703B 0x063C
#define REG_RESP_SIFS_OFDM_8703B 0x063E
#define REG_ACKTO_8703B 0x0640
#define REG_CTS2TO_8703B 0x0641
#define REG_EIFS_8703B 0x0642
#define REG_NAV_UPPER_8703B 0x0652 // unit of 128
#define REG_TRXPTCL_CTL_8703B 0x0668
// Security
#define REG_CAMCMD_8703B 0x0670
#define REG_CAMWRITE_8703B 0x0674
#define REG_CAMREAD_8703B 0x0678
#define REG_CAMDBG_8703B 0x067C
#define REG_SECCFG_8703B 0x0680
// Power
#define REG_WOW_CTRL_8703B 0x0690
#define REG_PS_RX_INFO_8703B 0x0692
#define REG_UAPSD_TID_8703B 0x0693
#define REG_WKFMCAM_CMD_8703B 0x0698
#define REG_WKFMCAM_NUM_8703B 0x0698
#define REG_WKFMCAM_RWD_8703B 0x069C
#define REG_RXFLTMAP0_8703B 0x06A0
#define REG_RXFLTMAP1_8703B 0x06A2
#define REG_RXFLTMAP2_8703B 0x06A4
#define REG_BCN_PSR_RPT_8703B 0x06A8
#define REG_BT_COEX_TABLE_8703B 0x06C0
#define REG_BFMER0_INFO_8703B 0x06E4
#define REG_BFMER1_INFO_8703B 0x06EC
#define REG_CSI_RPT_PARAM_BW20_8703B 0x06F4
#define REG_CSI_RPT_PARAM_BW40_8703B 0x06F8
#define REG_CSI_RPT_PARAM_BW80_8703B 0x06FC
// Hardware Port 2
#define REG_MACID1_8703B 0x0700
#define REG_BSSID1_8703B 0x0708
#define REG_BFMEE_SEL_8703B 0x0714
#define REG_SND_PTCL_CTRL_8703B 0x0718
// LTE_COEX
#define REG_LTECOEX_CTRL 0x07C0
#define REG_LTECOEX_WRITE_DATA 0x07C4
#define REG_LTECOEX_READ_DATA 0x07C8
#define REG_LTECOEX_PATH_CONTROL 0x70
//============================================================
// SDIO Bus Specification
//============================================================
//-----------------------------------------------------
// SDIO CMD Address Mapping
//-----------------------------------------------------
//-----------------------------------------------------
// I/O bus domain (Host)
//-----------------------------------------------------
//-----------------------------------------------------
// SDIO register
//-----------------------------------------------------
#define SDIO_REG_HCPWM1_8703B 0x025 // HCI Current Power Mode 1
//============================================================================
// 8703 Regsiter Bit and Content definition
//============================================================================
#define BIT_USB_RXDMA_AGG_EN BIT(31)
#define RXDMA_AGG_MODE_EN BIT(1)
#ifdef CONFIG_WOWLAN
#define RXPKT_RELEASE_POLL BIT(16)
#define RXDMA_IDLE BIT(17)
#define RW_RELEASE_EN BIT(18)
#endif
//2 HSISR
// interrupt mask which needs to clear
#define MASK_HSISR_CLEAR (HSISR_GPIO12_0_INT |\
HSISR_SPS_OCP_INT |\
HSISR_RON_INT |\
HSISR_PDNINT |\
HSISR_GPIO9_INT)
//----------------------------------------------------------------------------
// 8703B REG_CCK_CHECK (offset 0x454)
//----------------------------------------------------------------------------
#define BIT_BCN_PORT_SEL BIT5
#ifdef CONFIG_RF_POWER_TRIM
#ifdef CONFIG_RTL8703B
#define EEPROM_RF_GAIN_OFFSET 0xC1
#endif
#define EEPROM_RF_GAIN_VAL 0x1F6
#endif /*CONFIG_RF_POWER_TRIM*/
//----------------------------------------------------------------------------
// 8195 IMR/ISR bits (offset 0xB0, 8bits)
//----------------------------------------------------------------------------
#define IMR_DISABLED_8703B 0
// IMR DW0(0x00B0-00B3) Bit 0-31
#define IMR_TIMER2_8703B BIT31 // Timeout interrupt 2
#define IMR_TIMER1_8703B BIT30 // Timeout interrupt 1
#define IMR_PSTIMEOUT_8703B BIT29 // Power Save Time Out Interrupt
#define IMR_GTINT4_8703B BIT28 // When GTIMER4 expires, this bit is set to 1
#define IMR_GTINT3_8703B BIT27 // When GTIMER3 expires, this bit is set to 1
#define IMR_TXBCN0ERR_8703B BIT26 // Transmit Beacon0 Error
#define IMR_TXBCN0OK_8703B BIT25 // Transmit Beacon0 OK
#define IMR_TSF_BIT32_TOGGLE_8703B BIT24 // TSF Timer BIT32 toggle indication interrupt
#define IMR_BCNDMAINT0_8703B BIT20 // Beacon DMA Interrupt 0
#define IMR_BCNDERR0_8703B BIT16 // Beacon Queue DMA OK0
#define IMR_HSISR_IND_ON_INT_8703B BIT15 // HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1)
#define IMR_BCNDMAINT_E_8703B BIT14 // Beacon DMA Interrupt Extension for Win7
#define IMR_ATIMEND_8703B BIT12 // CTWidnow End or ATIM Window End
#define IMR_C2HCMD_8703B BIT10 // CPU to Host Command INT Status, Write 1 clear
#define IMR_CPWM2_8703B BIT9 // CPU power Mode exchange INT Status, Write 1 clear
#define IMR_CPWM_8703B BIT8 // CPU power Mode exchange INT Status, Write 1 clear
#define IMR_HIGHDOK_8703B BIT7 // High Queue DMA OK
#define IMR_MGNTDOK_8703B BIT6 // Management Queue DMA OK
#define IMR_BKDOK_8703B BIT5 // AC_BK DMA OK
#define IMR_BEDOK_8703B BIT4 // AC_BE DMA OK
#define IMR_VIDOK_8703B BIT3 // AC_VI DMA OK
#define IMR_VODOK_8703B BIT2 // AC_VO DMA OK
#define IMR_RDU_8703B BIT1 // Rx Descriptor Unavailable
#define IMR_ROK_8703B BIT0 // Receive DMA OK
// IMR DW1(0x00B4-00B7) Bit 0-31
#define IMR_BCNDMAINT7_8703B BIT27 // Beacon DMA Interrupt 7
#define IMR_BCNDMAINT6_8703B BIT26 // Beacon DMA Interrupt 6
#define IMR_BCNDMAINT5_8703B BIT25 // Beacon DMA Interrupt 5
#define IMR_BCNDMAINT4_8703B BIT24 // Beacon DMA Interrupt 4
#define IMR_BCNDMAINT3_8703B BIT23 // Beacon DMA Interrupt 3
#define IMR_BCNDMAINT2_8703B BIT22 // Beacon DMA Interrupt 2
#define IMR_BCNDMAINT1_8703B BIT21 // Beacon DMA Interrupt 1
#define IMR_BCNDOK7_8703B BIT20 // Beacon Queue DMA OK Interrup 7
#define IMR_BCNDOK6_8703B BIT19 // Beacon Queue DMA OK Interrup 6
#define IMR_BCNDOK5_8703B BIT18 // Beacon Queue DMA OK Interrup 5
#define IMR_BCNDOK4_8703B BIT17 // Beacon Queue DMA OK Interrup 4
#define IMR_BCNDOK3_8703B BIT16 // Beacon Queue DMA OK Interrup 3
#define IMR_BCNDOK2_8703B BIT15 // Beacon Queue DMA OK Interrup 2
#define IMR_BCNDOK1_8703B BIT14 // Beacon Queue DMA OK Interrup 1
#define IMR_ATIMEND_E_8703B BIT13 // ATIM Window End Extension for Win7
#define IMR_TXERR_8703B BIT11 // Tx Error Flag Interrupt Status, write 1 clear.
#define IMR_RXERR_8703B BIT10 // Rx Error Flag INT Status, Write 1 clear
#define IMR_TXFOVW_8703B BIT9 // Transmit FIFO Overflow
#define IMR_RXFOVW_8703B BIT8 // Receive FIFO Overflow
#ifdef CONFIG_PCI_HCI
//#define IMR_RX_MASK (IMR_ROK_8703B|IMR_RDU_8703B|IMR_RXFOVW_8703B)
#define IMR_TX_MASK (IMR_VODOK_8703B|IMR_VIDOK_8703B|IMR_BEDOK_8703B|IMR_BKDOK_8703B|IMR_MGNTDOK_8703B|IMR_HIGHDOK_8703B)
#define RT_BCN_INT_MASKS (IMR_BCNDMAINT0_8703B | IMR_TXBCN0OK_8703B | IMR_TXBCN0ERR_8703B | IMR_BCNDERR0_8703B)
#define RT_AC_INT_MASKS (IMR_VIDOK_8703B | IMR_VODOK_8703B | IMR_BEDOK_8703B|IMR_BKDOK_8703B)
#endif
//========================================================
// General definitions
//========================================================
#define MACID_NUM_8703B 16
#define SEC_CAM_ENT_NUM_8703B 16
#define NSS_NUM_8703B 1
#define BAND_CAP_8703B (BAND_CAP_2G)
#define BW_CAP_8703B (BW_CAP_20M | BW_CAP_40M)
#define PROTO_CAP_8703B (PROTO_CAP_11B|PROTO_CAP_11G|PROTO_CAP_11N)
#endif /* __RTL8703B_SPEC_H__ */

30
include/rtl8703b_sreset.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef _RTL8703B_SRESET_H_
#define _RTL8703B_SRESET_H_
#include <rtw_sreset.h>
#ifdef DBG_CONFIG_ERROR_DETECT
extern void rtl8703b_sreset_xmit_status_check(_adapter *padapter);
extern void rtl8703b_sreset_linked_status_check(_adapter *padapter);
#endif
#endif

336
include/rtl8703b_xmit.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTL8703B_XMIT_H__
#define __RTL8703B_XMIT_H__
#define MAX_TID (15)
#ifndef __INC_HAL8703BDESC_H
#define __INC_HAL8703BDESC_H
#define RX_STATUS_DESC_SIZE_8703B 24
#define RX_DRV_INFO_SIZE_UNIT_8703B 8
//DWORD 0
#define SET_RX_STATUS_DESC_PKT_LEN_8703B(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE( __pRxStatusDesc, 0, 14, __Value)
#define SET_RX_STATUS_DESC_EOR_8703B(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE( __pRxStatusDesc, 30, 1, __Value)
#define SET_RX_STATUS_DESC_OWN_8703B(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE( __pRxStatusDesc, 31, 1, __Value)
#define GET_RX_STATUS_DESC_PKT_LEN_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 0, 14)
#define GET_RX_STATUS_DESC_CRC32_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 14, 1)
#define GET_RX_STATUS_DESC_ICV_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 15, 1)
#define GET_RX_STATUS_DESC_DRVINFO_SIZE_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 16, 4)
#define GET_RX_STATUS_DESC_SECURITY_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 20, 3)
#define GET_RX_STATUS_DESC_QOS_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 23, 1)
#define GET_RX_STATUS_DESC_SHIFT_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 24, 2)
#define GET_RX_STATUS_DESC_PHY_STATUS_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 26, 1)
#define GET_RX_STATUS_DESC_SWDEC_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 27, 1)
#define GET_RX_STATUS_DESC_LAST_SEG_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 28, 1)
#define GET_RX_STATUS_DESC_FIRST_SEG_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 29, 1)
#define GET_RX_STATUS_DESC_EOR_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 30, 1)
#define GET_RX_STATUS_DESC_OWN_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 31, 1)
//DWORD 1
#define GET_RX_STATUS_DESC_MACID_8703B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 0, 7)
#define GET_RX_STATUS_DESC_TID_8703B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 8, 4)
#define GET_RX_STATUS_DESC_AMSDU_8703B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 13, 1)
#define GET_RX_STATUS_DESC_RXID_MATCH_8703B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 14, 1)
#define GET_RX_STATUS_DESC_PAGGR_8703B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 15, 1)
#define GET_RX_STATUS_DESC_A1_FIT_8703B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 16, 4)
#define GET_RX_STATUS_DESC_CHKERR_8703B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 20, 1)
#define GET_RX_STATUS_DESC_IPVER_8703B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 21, 1)
#define GET_RX_STATUS_DESC_IS_TCPUDP__8703B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 22, 1)
#define GET_RX_STATUS_DESC_CHK_VLD_8703B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 23, 1)
#define GET_RX_STATUS_DESC_PAM_8703B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 24, 1)
#define GET_RX_STATUS_DESC_PWR_8703B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 25, 1)
#define GET_RX_STATUS_DESC_MORE_DATA_8703B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 26, 1)
#define GET_RX_STATUS_DESC_MORE_FRAG_8703B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 27, 1)
#define GET_RX_STATUS_DESC_TYPE_8703B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 28, 2)
#define GET_RX_STATUS_DESC_MC_8703B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 30, 1)
#define GET_RX_STATUS_DESC_BC_8703B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 31, 1)
//DWORD 2
#define GET_RX_STATUS_DESC_SEQ_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+8, 0, 12)
#define GET_RX_STATUS_DESC_FRAG_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+8, 12, 4)
#define GET_RX_STATUS_DESC_RX_IS_QOS_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+8, 16, 1)
#define GET_RX_STATUS_DESC_WLANHD_IV_LEN_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+8, 18, 6)
#define GET_RX_STATUS_DESC_RPT_SEL_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+8, 28, 1)
//DWORD 3
#define GET_RX_STATUS_DESC_RX_RATE_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+12, 0, 7)
#define GET_RX_STATUS_DESC_HTC_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+12, 10, 1)
#define GET_RX_STATUS_DESC_EOSP_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+12, 11, 1)
#define GET_RX_STATUS_DESC_BSSID_FIT_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+12, 12, 2)
#ifdef CONFIG_USB_RX_AGGREGATION
#define GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+12, 16, 8)
#endif
#define GET_RX_STATUS_DESC_PATTERN_MATCH_8703B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+12, 29, 1)
#define GET_RX_STATUS_DESC_UNICAST_MATCH_8703B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+12, 30, 1)
#define GET_RX_STATUS_DESC_MAGIC_MATCH_8703B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+12, 31, 1)
//DWORD 6
#define GET_RX_STATUS_DESC_SPLCP_8703B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+16, 0, 1)
#define GET_RX_STATUS_DESC_LDPC_8703B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+16, 1, 1)
#define GET_RX_STATUS_DESC_STBC_8703B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+16, 2, 1)
#define GET_RX_STATUS_DESC_BW_8703B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+16, 4, 2)
//DWORD 5
#define GET_RX_STATUS_DESC_TSFL_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+20, 0, 32)
#define GET_RX_STATUS_DESC_BUFF_ADDR_8703B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+24, 0, 32)
#define GET_RX_STATUS_DESC_BUFF_ADDR64_8703B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+28, 0, 32)
#define SET_RX_STATUS_DESC_BUFF_ADDR_8703B(__pRxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxDesc+24, 0, 32, __Value)
// Dword 0
#define GET_TX_DESC_OWN_8703B(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc, 31, 1)
#define SET_TX_DESC_PKT_SIZE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value)
#define SET_TX_DESC_OFFSET_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value)
#define SET_TX_DESC_BMC_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value)
#define SET_TX_DESC_HTC_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value)
#define SET_TX_DESC_LAST_SEG_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 26, 1, __Value)
#define SET_TX_DESC_FIRST_SEG_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value)
#define SET_TX_DESC_LINIP_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 28, 1, __Value)
#define SET_TX_DESC_NO_ACM_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value)
#define SET_TX_DESC_GF_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value)
#define SET_TX_DESC_OWN_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)
// Dword 1
#define SET_TX_DESC_MACID_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value)
#define SET_TX_DESC_QUEUE_SEL_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value)
#define SET_TX_DESC_RDG_NAV_EXT_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value)
#define SET_TX_DESC_LSIG_TXOP_EN_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value)
#define SET_TX_DESC_PIFS_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value)
#define SET_TX_DESC_RATE_ID_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value)
#define SET_TX_DESC_EN_DESC_ID_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value)
#define SET_TX_DESC_SEC_TYPE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value)
#define SET_TX_DESC_PKT_OFFSET_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value)
// Dword 2
#define SET_TX_DESC_PAID_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0, 9, __Value)
#define SET_TX_DESC_CCA_RTS_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value)
#define SET_TX_DESC_AGG_ENABLE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value)
#define SET_TX_DESC_RDG_ENABLE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value)
#define SET_TX_DESC_AGG_BREAK_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value)
#define SET_TX_DESC_MORE_FRAG_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value)
#define SET_TX_DESC_RAW_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value)
#define SET_TX_DESC_SPE_RPT_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value)
#define SET_TX_DESC_AMPDU_DENSITY_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value)
#define SET_TX_DESC_BT_INT_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value)
#define SET_TX_DESC_GID_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 6, __Value)
// Dword 3
#define SET_TX_DESC_WHEADER_LEN_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 0, 4, __Value)
#define SET_TX_DESC_CHK_EN_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 4, 1, __Value)
#define SET_TX_DESC_EARLY_MODE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 5, 1, __Value)
#define SET_TX_DESC_HWSEQ_SEL_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value)
#define SET_TX_DESC_USE_RATE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value)
#define SET_TX_DESC_DISABLE_RTS_FB_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value)
#define SET_TX_DESC_DISABLE_FB_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value)
#define SET_TX_DESC_CTS2SELF_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value)
#define SET_TX_DESC_RTS_ENABLE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value)
#define SET_TX_DESC_HW_RTS_ENABLE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value)
#define SET_TX_DESC_NAV_USE_HDR_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 15, 1, __Value)
#define SET_TX_DESC_USE_MAX_LEN_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value)
#define SET_TX_DESC_MAX_AGG_NUM_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value)
#define SET_TX_DESC_NDPA_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 22, 2, __Value)
#define SET_TX_DESC_AMPDU_MAX_TIME_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value)
// Dword 4
#define SET_TX_DESC_TX_RATE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value)
#define SET_TX_DESC_DATA_RATE_FB_LIMIT_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value)
#define SET_TX_DESC_RTS_RATE_FB_LIMIT_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value)
#define SET_TX_DESC_RETRY_LIMIT_ENABLE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value)
#define SET_TX_DESC_DATA_RETRY_LIMIT_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value)
#define SET_TX_DESC_RTS_RATE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value)
// Dword 5
#define SET_TX_DESC_DATA_SC_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value)
#define SET_TX_DESC_DATA_SHORT_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value)
#define SET_TX_DESC_DATA_BW_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value)
#define SET_TX_DESC_DATA_LDPC_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 7, 1, __Value)
#define SET_TX_DESC_DATA_STBC_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value)
#define SET_TX_DESC_CTROL_STBC_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value)
#define SET_TX_DESC_RTS_SHORT_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value)
#define SET_TX_DESC_RTS_SC_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value)
// Dword 6
#define SET_TX_DESC_SW_DEFINE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value)
#define SET_TX_DESC_MBSSID_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 12, 4, __Value)
#define SET_TX_DESC_ANTSEL_A_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value)
#define SET_TX_DESC_ANTSEL_B_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 19, 3, __Value)
#define SET_TX_DESC_ANTSEL_C_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 22, 3, __Value)
#define SET_TX_DESC_ANTSEL_D_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 25, 3, __Value)
// Dword 7
#if(DEV_BUS_TYPE == RT_PCI_INTERFACE)
#define SET_TX_DESC_TX_BUFFER_SIZE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
#else
#define SET_TX_DESC_TX_DESC_CHECKSUM_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
#endif
#define SET_TX_DESC_USB_TXAGG_NUM_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value)
#if(DEV_BUS_TYPE == RT_SDIO_INTERFACE)
#define SET_TX_DESC_SDIO_TXSEQ_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 16, 8, __Value)
#endif
// Dword 8
#define SET_TX_DESC_HWSEQ_EN_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value)
// Dword 9
#define SET_TX_DESC_SEQ_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value)
// Dword 10
#define SET_TX_DESC_TX_BUFFER_ADDRESS_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+40, 0, 32, __Value)
#define GET_TX_DESC_TX_BUFFER_ADDRESS_8703B(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+40, 0, 32)
// Dword 11
#define SET_TX_DESC_NEXT_DESC_ADDRESS_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+48, 0, 32, __Value)
#define SET_EARLYMODE_PKTNUM_8703B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value)
#define SET_EARLYMODE_LEN0_8703B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value)
#define SET_EARLYMODE_LEN1_1_8703B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value)
#define SET_EARLYMODE_LEN1_2_8703B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value)
#define SET_EARLYMODE_LEN2_8703B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15, __Value)
#define SET_EARLYMODE_LEN3_8703B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value)
#endif
//-----------------------------------------------------------
//
// Rate
//
//-----------------------------------------------------------
// CCK Rates, TxHT = 0
#define DESC8703B_RATE1M 0x00
#define DESC8703B_RATE2M 0x01
#define DESC8703B_RATE5_5M 0x02
#define DESC8703B_RATE11M 0x03
// OFDM Rates, TxHT = 0
#define DESC8703B_RATE6M 0x04
#define DESC8703B_RATE9M 0x05
#define DESC8703B_RATE12M 0x06
#define DESC8703B_RATE18M 0x07
#define DESC8703B_RATE24M 0x08
#define DESC8703B_RATE36M 0x09
#define DESC8703B_RATE48M 0x0a
#define DESC8703B_RATE54M 0x0b
// MCS Rates, TxHT = 1
#define DESC8703B_RATEMCS0 0x0c
#define DESC8703B_RATEMCS1 0x0d
#define DESC8703B_RATEMCS2 0x0e
#define DESC8703B_RATEMCS3 0x0f
#define DESC8703B_RATEMCS4 0x10
#define DESC8703B_RATEMCS5 0x11
#define DESC8703B_RATEMCS6 0x12
#define DESC8703B_RATEMCS7 0x13
#define DESC8703B_RATEMCS8 0x14
#define DESC8703B_RATEMCS9 0x15
#define DESC8703B_RATEMCS10 0x16
#define DESC8703B_RATEMCS11 0x17
#define DESC8703B_RATEMCS12 0x18
#define DESC8703B_RATEMCS13 0x19
#define DESC8703B_RATEMCS14 0x1a
#define DESC8703B_RATEMCS15 0x1b
#define DESC8703B_RATEVHTSS1MCS0 0x2c
#define DESC8703B_RATEVHTSS1MCS1 0x2d
#define DESC8703B_RATEVHTSS1MCS2 0x2e
#define DESC8703B_RATEVHTSS1MCS3 0x2f
#define DESC8703B_RATEVHTSS1MCS4 0x30
#define DESC8703B_RATEVHTSS1MCS5 0x31
#define DESC8703B_RATEVHTSS1MCS6 0x32
#define DESC8703B_RATEVHTSS1MCS7 0x33
#define DESC8703B_RATEVHTSS1MCS8 0x34
#define DESC8703B_RATEVHTSS1MCS9 0x35
#define DESC8703B_RATEVHTSS2MCS0 0x36
#define DESC8703B_RATEVHTSS2MCS1 0x37
#define DESC8703B_RATEVHTSS2MCS2 0x38
#define DESC8703B_RATEVHTSS2MCS3 0x39
#define DESC8703B_RATEVHTSS2MCS4 0x3a
#define DESC8703B_RATEVHTSS2MCS5 0x3b
#define DESC8703B_RATEVHTSS2MCS6 0x3c
#define DESC8703B_RATEVHTSS2MCS7 0x3d
#define DESC8703B_RATEVHTSS2MCS8 0x3e
#define DESC8703B_RATEVHTSS2MCS9 0x3f
#define RX_HAL_IS_CCK_RATE_8703B(pDesc)\
(GET_RX_STATUS_DESC_RX_RATE_8703B(pDesc) == DESC8703B_RATE1M ||\
GET_RX_STATUS_DESC_RX_RATE_8703B(pDesc) == DESC8703B_RATE2M ||\
GET_RX_STATUS_DESC_RX_RATE_8703B(pDesc) == DESC8703B_RATE5_5M ||\
GET_RX_STATUS_DESC_RX_RATE_8703B(pDesc) == DESC8703B_RATE11M)
void rtl8703b_update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem);
void rtl8703b_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame);
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
s32 rtl8703bs_init_xmit_priv(PADAPTER padapter);
void rtl8703bs_free_xmit_priv(PADAPTER padapter);
s32 rtl8703bs_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
s32 rtl8703bs_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
s32 rtl8703bs_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
s32 rtl8703bs_xmit_buf_handler(PADAPTER padapter);
thread_return rtl8703bs_xmit_thread(thread_context context);
#define hal_xmit_handler rtl8703bs_xmit_buf_handler
#endif
#ifdef CONFIG_USB_HCI
s32 rtl8703bu_xmit_buf_handler(PADAPTER padapter);
#define hal_xmit_handler rtl8703bu_xmit_buf_handler
s32 rtl8703bu_init_xmit_priv(PADAPTER padapter);
void rtl8703bu_free_xmit_priv(PADAPTER padapter);
s32 rtl8703bu_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
s32 rtl8703bu_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
s32 rtl8703bu_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
//s32 rtl8812au_xmit_buf_handler(PADAPTER padapter);
void rtl8703bu_xmit_tasklet(void *priv);
s32 rtl8703bu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
void _dbg_dump_tx_info(_adapter *padapter,int frame_tag,struct tx_desc *ptxdesc);
#endif
#ifdef CONFIG_PCI_HCI
s32 rtl8703be_init_xmit_priv(PADAPTER padapter);
void rtl8703be_free_xmit_priv(PADAPTER padapter);
struct xmit_buf *rtl8703be_dequeue_xmitbuf(struct rtw_tx_ring *ring);
void rtl8703be_xmitframe_resume(_adapter *padapter);
s32 rtl8703be_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
s32 rtl8703be_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
s32 rtl8703be_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
void rtl8703be_xmit_tasklet(void *priv);
#endif
u8 BWMapping_8703B(PADAPTER Adapter, struct pkt_attrib *pattrib);
u8 SCMapping_8703B(PADAPTER Adapter, struct pkt_attrib *pattrib);
#endif

215
include/rtl8723a_cmd.h
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@@ -1,215 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTL8723A_CMD_H__
#define __RTL8723A_CMD_H__
#define H2C_8723A_BT_FW_PATCH_LEN 3
#define H2C_BT_PWR_FORCE_LEN 3
enum cmd_msg_element_id
{
NONE_CMDMSG_EID,
AP_OFFLOAD_EID = 0,
SET_PWRMODE_EID = 1,
JOINBSS_RPT_EID = 2,
RSVD_PAGE_EID = 3,
RSSI_4_EID = 4,
RSSI_SETTING_EID = 5,
MACID_CONFIG_EID = 6,
MACID_PS_MODE_EID = 7,
P2P_PS_OFFLOAD_EID = 8,
SELECTIVE_SUSPEND_ROF_CMD = 9,
BT_QUEUE_PKT_EID = 17,
BT_ANT_TDMA_EID = 20,
BT_2ANT_HID_EID = 21,
P2P_PS_CTW_CMD_EID = 32,
FORCE_BT_TX_PWR_EID = 33,
SET_TDMA_WLAN_ACT_TIME_EID = 34,
SET_BT_TX_RETRY_INDEX_EID = 35,
HID_PROFILE_ENABLE_EID = 36,
BT_IGNORE_WLAN_ACT_EID = 37,
BT_PTA_MANAGER_UPDATE_ENABLE_EID = 38,
DAC_SWING_VALUE_EID = 41,
TRADITIONAL_TDMA_EN_EID = 51,
H2C_8723A_BT_FW_PATCH = 54,
B_TYPE_TDMA_EID = 58,
SCAN_EN_EID = 59,
LOWPWR_LPS_EID = 71,
H2C_8723A_RESET_TSF = 75,
MAX_CMDMSG_EID
};
struct cmd_msg_parm {
u8 eid; //element id
u8 sz; // sz
u8 buf[6];
};
typedef struct _SETPWRMODE_PARM
{
u8 Mode;
u8 SmartPS;
u8 AwakeInterval; // unit: beacon interval
u8 bAllQueueUAPSD;
#if 0
u8 LowRxBCN:1;
u8 AutoAntSwitch:1;
u8 PSAllowBTHighPriority:1;
u8 rsvd43:5;
#else
#define SETPM_LOWRXBCN BIT(0)
#define SETPM_AUTOANTSWITCH BIT(1)
#define SETPM_PSALLOWBTHIGHPRI BIT(2)
u8 BcnAntMode;
#endif
}__attribute__((__packed__)) SETPWRMODE_PARM, *PSETPWRMODE_PARM;
struct H2C_SS_RFOFF_PARAM{
u8 ROFOn; // 1: on, 0:off
u16 gpio_period; // unit: 1024 us
}__attribute__ ((packed));
typedef struct JOINBSSRPT_PARM_8723A{
u8 OpMode; // RT_MEDIA_STATUS
}JOINBSSRPT_PARM_8723A, *PJOINBSSRPT_PARM_8723A;
typedef struct _RSVDPAGE_LOC_8723A {
u8 LocProbeRsp;
u8 LocPsPoll;
u8 LocNullData;
u8 LocQosNull;
u8 LocBTQosNull;
} RSVDPAGE_LOC_8723A, *PRSVDPAGE_LOC_8723A;
typedef struct _B_TYPE_TDMA_PARM
{
#if 0
u8 En:1;
u8 FixAntennaInBTSide:1;
u8 TxPspoll:1;
u8 val870:1; // value of 870, when disable
u8 AutoWakeUp:1;
u8 NoPS:1;
u8 WlanHighPriority:1;
u8 rsvd07:1;
#else
#define B_TDMA_EN BIT(0)
#define B_TDMA_FIXANTINBT BIT(1)
#define B_TDMA_TXPSPOLL BIT(2)
#define B_TDMA_VAL870 BIT(3)
#define B_TDMA_AUTOWAKEUP BIT(4)
#define B_TDMA_NOPS BIT(5)
#define B_TDMA_WLANHIGHPRI BIT(6)
u8 option;
#endif
u8 TBTTOnPeriod;
u8 MedPeriod;
u8 rsvd30;
}__attribute__((__packed__)) B_TYPE_TDMA_PARM, *PB_TYPE_TDMA_PARM;
typedef struct _SCAN_EN_PARM {
#if 0
u8 En:1;
u8 rsvd01:7;
#else
u8 En;
#endif
}__attribute__((__packed__)) SCAN_EN_PARM, *PSCAN_EN_PARM;
// BT_PWR
#define SET_H2CCMD_BT_PWR_IDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT(__pH2CCmd, 0, 8, __Value)
// BT_FW_PATCH
#if 0
#define SET_H2CCMD_BT_FW_PATCH_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
#define SET_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value) SET_BITS_TO_LE_2BYTE((__pH2CCmd)+1, 0, 16, __Value)
#else
#define SET_H2CCMD_BT_FW_PATCH_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_4BYTE(__pH2CCmd, 0, 8, __Value) // SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
#define SET_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value) SET_BITS_TO_LE_4BYTE(__pH2CCmd, 8, 16, __Value) // SET_BITS_TO_LE_2BYTE((__pH2CCmd)+1, 0, 16, __Value)
#endif
#if 0
/*
* H2C_LOWPWR_LPS
* h2c cmd = 71
* byte1[6:0]= bcn count : how many bcn not recevied should return to old mechanism
* byte1[7] = enable : enable mechanism
* byte2=bcn period : bcn recv time of this AP, unit 32 us
* byte3= drop threshold : how many pkts be droped, rx dma should be release
* byte4 = max early period
* byte5 = max bcn timeout period
*/
#define SET_H2CCMD_LOWPWR_LPS_BCN_COUNT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)
#define SET_H2CCMD_LOWPWR_LPS_TB_BCN_THRESH(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 3, __Value)
#define SET_H2CCMD_LOWPWR_LPS_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 7, 1, __Value)
#define SET_H2CCMD_LOWPWR_LPS_BCN_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+1, 0, 8, __Value)
#define SET_H2CCMD_LOWPWR_LPS_BCN_DROP_THRESH(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+2, 0, 8, __Value)
#define SET_H2CCMD_LOWPWR_LPS_MAX_EARLY_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+3, 0, 8, __Value)
#define SET_H2CCMD_LOWPWR_LPS_MAX_BCN_TO_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+4, 0, 8, __Value)
#else
typedef struct _LOWPWR_LPS_PARM
{
u8 bcn_count:4;
u8 tb_bcn_threshold:3;
u8 enable:1;
u8 bcn_interval;
u8 drop_threshold;
u8 max_early_period;
u8 max_bcn_timeout_period;
}__attribute__((__packed__)) LOWPWR_LPS_PARM, *PLOWPWR_LPS_PARM;
#endif
// host message to firmware cmd
void rtl8723a_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode);
void rtl8723a_set_FwJoinBssReport_cmd(PADAPTER padapter, u8 mstatus);
#ifdef CONFIG_BT_COEXIST
void rtl8723a_set_BTCoex_AP_mode_FwRsvdPkt_cmd(PADAPTER padapter);
#endif
u8 rtl8192c_set_rssi_cmd(PADAPTER padapter, u8 *param);
//u8 rtl8723a_set_rssi_cmd(PADAPTER padapter, u8 *param);
void rtl8192c_set_raid_cmd(PADAPTER padapter, u32 mask, u8* arg);
//u8 rtl8723a_set_raid_cmd(PADAPTER padapter, u32 mask, u8 arg);
void rtl8192c_Add_RateATid(PADAPTER padapter, u32 bitmap, u8* arg, u8 rssi_level);
//void rtl8723a_Add_RateATid(PADAPTER padapter, u32 bitmap, u8 arg);
u8 rtl8192c_set_FwSelectSuspend_cmd(PADAPTER padapter, u8 bfwpoll, u16 period);
//u8 rtl8723a_set_FwSelectSuspend_cmd(PADAPTER padapter, u8 bfwpoll, u16 period);
#ifdef CONFIG_P2P
void rtl8192c_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);
//void rtl8723a_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);
#endif //CONFIG_P2P
void CheckFwRsvdPageContent(PADAPTER padapter);
#endif
#ifdef CONFIG_TSF_RESET_OFFLOAD
u8 rtl8723c_reset_tsf(_adapter *padapter, u8 reset_port);
#endif // CONFIG_TSF_RESET_OFFLOAD
s32 FillH2CCmd(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);

461
include/rtl8723a_hal.h
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@@ -1,461 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTL8723A_HAL_H__
#define __RTL8723A_HAL_H__
//#include "hal_com.h"
#if 1
#include "hal_data.h"
#else
#include "../hal/OUTSRC/odm_precomp.h"
#endif
#include "rtl8723a_spec.h"
#include "rtl8723a_pg.h"
#include "Hal8723APhyReg.h"
#include "Hal8723APhyCfg.h"
#include "rtl8723a_rf.h"
#include "rtl8723a_dm.h"
#include "rtl8723a_recv.h"
#include "rtl8723a_xmit.h"
#include "rtl8723a_cmd.h"
#include "rtl8723a_led.h"
#include "Hal8723PwrSeq.h"
#ifdef DBG_CONFIG_ERROR_DETECT
#include "rtl8723a_sreset.h"
#endif
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
//2TODO: We should define 8192S firmware related macro settings here!!
#define RTL819X_DEFAULT_RF_TYPE RF_1T2R
#define RTL819X_TOTAL_RF_PATH 2
//---------------------------------------------------------------------
// RTL8723S From file
//---------------------------------------------------------------------
#define RTL8723_FW_UMC_IMG "rtl8723S\\rtl8723fw.bin"
#define RTL8723_FW_UMC_B_IMG "rtl8723S\\rtl8723fw_B.bin"
#define RTL8723_PHY_REG "rtl8723S\\PHY_REG_1T.txt"
#define RTL8723_PHY_RADIO_A "rtl8723S\\radio_a_1T.txt"
#define RTL8723_PHY_RADIO_B "rtl8723S\\radio_b_1T.txt"
#define RTL8723_AGC_TAB "rtl8723S\\AGC_TAB_1T.txt"
#define RTL8723_PHY_MACREG "rtl8723S\\MAC_REG.txt"
#define RTL8723_PHY_REG_PG "rtl8723S\\PHY_REG_PG.txt"
#define RTL8723_PHY_REG_MP "rtl8723S\\PHY_REG_MP.txt"
//---------------------------------------------------------------------
// RTL8723S From header
//---------------------------------------------------------------------
// Fw Array
#define Rtl8723_FwImageArray Rtl8723SFwImgArray
#define Rtl8723_FwUMCBCutImageArrayWithBT Rtl8723SFwUMCBCutImgArrayWithBT
#define Rtl8723_FwUMCBCutImageArrayWithoutBT Rtl8723SFwUMCBCutImgArrayWithoutBT
#define Rtl8723_ImgArrayLength Rtl8723SImgArrayLength
#define Rtl8723_UMCBCutImgArrayWithBTLength Rtl8723SUMCBCutImgArrayWithBTLength
#define Rtl8723_UMCBCutImgArrayWithoutBTLength Rtl8723SUMCBCutImgArrayWithoutBTLength
#define Rtl8723_PHY_REG_Array_PG Rtl8723SPHY_REG_Array_PG
#define Rtl8723_PHY_REG_Array_PGLength Rtl8723SPHY_REG_Array_PGLength
#if MP_DRIVER == 1
#define Rtl8723E_FwBTImgArray Rtl8723EFwBTImgArray
#define Rtl8723E_FwBTImgArrayLength Rtl8723EBTImgArrayLength
#define Rtl8723_FwUMCBCutMPImageArray Rtl8723SFwUMCBCutMPImgArray
#define Rtl8723_UMCBCutMPImgArrayLength Rtl8723SUMCBCutMPImgArrayLength
#define Rtl8723_PHY_REG_Array_MP Rtl8723SPHY_REG_Array_MP
#define Rtl8723_PHY_REG_Array_MPLength Rtl8723SPHY_REG_Array_MPLength
#endif
#endif // CONFIG_SDIO_HCI
#ifdef CONFIG_USB_HCI
//2TODO: We should define 8192S firmware related macro settings here!!
#define RTL819X_DEFAULT_RF_TYPE RF_1T2R
#define RTL819X_TOTAL_RF_PATH 2
//TODO: The following need to check!!
#define RTL8723_FW_UMC_IMG "rtl8192CU\\rtl8723fw.bin"
#define RTL8723_FW_UMC_B_IMG "rtl8192CU\\rtl8723fw_B.bin"
#define RTL8723_PHY_REG "rtl8723S\\PHY_REG_1T.txt"
#define RTL8723_PHY_RADIO_A "rtl8723S\\radio_a_1T.txt"
#define RTL8723_PHY_RADIO_B "rtl8723S\\radio_b_1T.txt"
#define RTL8723_AGC_TAB "rtl8723S\\AGC_TAB_1T.txt"
#define RTL8723_PHY_MACREG "rtl8723S\\MAC_REG.txt"
#define RTL8723_PHY_REG_PG "rtl8723S\\PHY_REG_PG.txt"
#define RTL8723_PHY_REG_MP "rtl8723S\\PHY_REG_MP.txt"
//---------------------------------------------------------------------
// RTL8723S From header
//---------------------------------------------------------------------
// Fw Array
#define Rtl8723_FwImageArray Rtl8723UFwImgArray
#define Rtl8723_FwUMCBCutImageArrayWithBT Rtl8723UFwUMCBCutImgArrayWithBT
#define Rtl8723_FwUMCBCutImageArrayWithoutBT Rtl8723UFwUMCBCutImgArrayWithoutBT
#define Rtl8723_ImgArrayLength Rtl8723UImgArrayLength
#define Rtl8723_UMCBCutImgArrayWithBTLength Rtl8723UUMCBCutImgArrayWithBTLength
#define Rtl8723_UMCBCutImgArrayWithoutBTLength Rtl8723UUMCBCutImgArrayWithoutBTLength
#define Rtl8723_PHY_REG_Array_PG Rtl8723UPHY_REG_Array_PG
#define Rtl8723_PHY_REG_Array_PGLength Rtl8723UPHY_REG_Array_PGLength
#if MP_DRIVER == 1
#define Rtl8723E_FwBTImgArray Rtl8723EFwBTImgArray
#define Rtl8723E_FwBTImgArrayLength Rtl8723EBTImgArrayLength
#define Rtl8723_FwUMCBCutMPImageArray Rtl8723SFwUMCBCutMPImgArray
#define Rtl8723_UMCBCutMPImgArrayLength Rtl8723SUMCBCutMPImgArrayLength
#define Rtl8723_PHY_REG_Array_MP Rtl8723UPHY_REG_Array_MP
#define Rtl8723_PHY_REG_Array_MPLength Rtl8723UPHY_REG_Array_MPLength
#endif
#endif
#define FW_8723A_SIZE 0x8000
#define FW_8723A_START_ADDRESS 0x1000
#define FW_8723A_END_ADDRESS 0x1FFF //0x5FFF
#define IS_FW_HEADER_EXIST_8723A(_pFwHdr) ((le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x92C0 ||\
(le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x88C0 ||\
(le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x2300)
typedef struct _RT_FIRMWARE_8723A {
FIRMWARE_SOURCE eFWSource;
#ifdef CONFIG_EMBEDDED_FWIMG
u8* szFwBuffer;
#else
u8 szFwBuffer[FW_8723A_SIZE];
#endif
u32 ulFwLength;
} RT_FIRMWARE_8723A, *PRT_FIRMWARE_8723A;
//
// This structure must be cared byte-ordering
//
// Added by tynli. 2009.12.04.
typedef struct _RT_8723A_FIRMWARE_HDR
{
// 8-byte alinment required
//--- LONG WORD 0 ----
u16 Signature; // 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut
u8 Category; // AP/NIC and USB/PCI
u8 Function; // Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions
u16 Version; // FW Version
u8 Subversion; // FW Subversion, default 0x00
u16 Rsvd1;
//--- LONG WORD 1 ----
u8 Month; // Release time Month field
u8 Date; // Release time Date field
u8 Hour; // Release time Hour field
u8 Minute; // Release time Minute field
u16 RamCodeSize; // The size of RAM code
u16 Rsvd2;
//--- LONG WORD 2 ----
u32 SvnIdx; // The SVN entry index
u32 Rsvd3;
//--- LONG WORD 3 ----
u32 Rsvd4;
u32 Rsvd5;
}RT_8723A_FIRMWARE_HDR, *PRT_8723A_FIRMWARE_HDR;
#define DRIVER_EARLY_INT_TIME_8723A 0x05
#define BCN_DMA_ATIME_INT_TIME_8723A 0x02
//For General Reserved Page Number(Beacon Queue is reserved page)
//Beacon:2, PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1
#define BCNQ_PAGE_NUM_8723A 0x08
#define TX_TOTAL_PAGE_NUMBER_8723A (0xFF - BCNQ_PAGE_NUM_8723A)
#define TX_PAGE_BOUNDARY_8723A (TX_TOTAL_PAGE_NUMBER_8723A + 1)
#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8723A TX_TOTAL_PAGE_NUMBER_8723A
#define WMM_NORMAL_TX_PAGE_BOUNDARY_8723A (WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8723A + 1)
// For Normal Chip Setting
// (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8723A
#define NORMAL_PAGE_NUM_HPQ_8723A 0x0C
#define NORMAL_PAGE_NUM_LPQ_8723A 0x02
#define NORMAL_PAGE_NUM_NPQ_8723A 0x02
// Note: For Normal Chip Setting, modify later
#define WMM_NORMAL_PAGE_NUM_HPQ_8723A 0x29
#define WMM_NORMAL_PAGE_NUM_LPQ_8723A 0x1C
#define WMM_NORMAL_PAGE_NUM_NPQ_8723A 0x1C
//-------------------------------------------------------------------------
// Chip specific
//-------------------------------------------------------------------------
#define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3)
#define CHIP_BONDING_92C_1T2R 0x1
#define CHIP_BONDING_88C_USB_MCARD 0x2
#define CHIP_BONDING_88C_USB_HP 0x1
//-------------------------------------------------------------------------
// Channel Plan
//-------------------------------------------------------------------------
#define HAL_EFUSE_MEMORY
#define EFUSE_REAL_CONTENT_LEN 512
#define EFUSE_MAP_LEN 128
#define EFUSE_MAX_SECTION 16
#define EFUSE_IC_ID_OFFSET 506 //For some inferiority IC purpose. added by Roger, 2009.09.02.
#define AVAILABLE_EFUSE_ADDR(addr) (addr < EFUSE_REAL_CONTENT_LEN)
//
// <Roger_Notes>
// To prevent out of boundary programming case,
// leave 1byte and program full section
// 9bytes + 1byt + 5bytes and pre 1byte.
// For worst case:
// | 1byte|----8bytes----|1byte|--5bytes--|
// | | Reserved(14bytes) |
//
// PG data exclude header, dummy 6 bytes frome CP test and reserved 1byte.
#define EFUSE_OOB_PROTECT_BYTES 15
#define EFUSE_REAL_CONTENT_LEN_8723A 512
#define EFUSE_MAP_LEN_8723A 256
#define EFUSE_MAX_SECTION_8723A 32
//========================================================
// EFUSE for BT definition
//========================================================
#define EFUSE_BT_REAL_BANK_CONTENT_LEN 512
#define EFUSE_BT_REAL_CONTENT_LEN 1536 // 512*3
#define EFUSE_BT_MAP_LEN 1024 // 1k bytes
#define EFUSE_BT_MAX_SECTION 128 // 1024/8
#define EFUSE_PROTECT_BYTES_BANK 16
// Description: Determine the types of C2H events that are the same in driver and Fw.
// Fisrt constructed by tynli. 2009.10.09.
typedef enum _RTL8192C_C2H_EVT
{
C2H_DBG = 0,
C2H_TSF = 1,
C2H_AP_RPT_RSP = 2,
C2H_CCX_TX_RPT = 3, // The FW notify the report of the specific tx packet.
C2H_BT_RSSI = 4,
C2H_BT_OP_MODE = 5,
C2H_EXT_RA_RPT = 6,
C2H_HW_INFO_EXCH = 10,
C2H_C2H_H2C_TEST = 11,
C2H_BT_INFO = 12,
C2H_BT_MP_INFO = 15,
MAX_C2HEVENT
} RTL8192C_C2H_EVT;
#define INCLUDE_MULTI_FUNC_BT(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)
#define INCLUDE_MULTI_FUNC_GPS(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)
typedef struct rxreport_8723a
{
u32 pktlen:14;
u32 crc32:1;
u32 icverr:1;
u32 drvinfosize:4;
u32 security:3;
u32 qos:1;
u32 shift:2;
u32 physt:1;
u32 swdec:1;
u32 ls:1;
u32 fs:1;
u32 eor:1;
u32 own:1;
u32 macid:5;
u32 tid:4;
u32 hwrsvd:4;
u32 amsdu:1;
u32 paggr:1;
u32 faggr:1;
u32 a1fit:4;
u32 a2fit:4;
u32 pam:1;
u32 pwr:1;
u32 md:1;
u32 mf:1;
u32 type:2;
u32 mc:1;
u32 bc:1;
u32 seq:12;
u32 frag:4;
u32 nextpktlen:14;
u32 nextind:1;
u32 rsvd0831:1;
u32 rxmcs:6;
u32 rxht:1;
u32 gf:1;
u32 splcp:1;
u32 bw:1;
u32 htc:1;
u32 eosp:1;
u32 bssidfit:2;
u32 rsvd1214:16;
u32 unicastwake:1;
u32 magicwake:1;
u32 pattern0match:1;
u32 pattern1match:1;
u32 pattern2match:1;
u32 pattern3match:1;
u32 pattern4match:1;
u32 pattern5match:1;
u32 pattern6match:1;
u32 pattern7match:1;
u32 pattern8match:1;
u32 pattern9match:1;
u32 patternamatch:1;
u32 patternbmatch:1;
u32 patterncmatch:1;
u32 rsvd1613:19;
u32 tsfl;
u32 bassn:12;
u32 bavld:1;
u32 rsvd2413:19;
} RXREPORT, *PRXREPORT;
typedef struct phystatus_8723a
{
u32 rxgain_a:7;
u32 trsw_a:1;
u32 rxgain_b:7;
u32 trsw_b:1;
u32 chcorr_l:16;
u32 sigqualcck:8;
u32 cfo_a:8;
u32 cfo_b:8;
u32 chcorr_h:8;
u32 noisepwrdb_h:8;
u32 cfo_tail_a:8;
u32 cfo_tail_b:8;
u32 rsvd0824:8;
u32 rsvd1200:8;
u32 rxevm_a:8;
u32 rxevm_b:8;
u32 rxsnr_a:8;
u32 rxsnr_b:8;
u32 noisepwrdb_l:8;
u32 rsvd1616:8;
u32 postsnr_a:8;
u32 postsnr_b:8;
u32 csi_a:8;
u32 csi_b:8;
u32 targetcsi_a:8;
u32 targetcsi_b:8;
u32 sigevm:8;
u32 maxexpwr:8;
u32 exintflag:1;
u32 sgien:1;
u32 rxsc:2;
u32 idlelong:1;
u32 anttrainen:1;
u32 antselb:1;
u32 antsel:1;
} PHYSTATUS, *PPHYSTATUS;
// rtl8723a_hal_init.c
s32 rtl8723a_FirmwareDownload(PADAPTER padapter);
void rtl8723a_FirmwareSelfReset(PADAPTER padapter);
void rtl8723a_InitializeFirmwareVars(PADAPTER padapter);
void rtl8723a_InitAntenna_Selection(PADAPTER padapter);
void rtl8723a_DeinitAntenna_Selection(PADAPTER padapter);
void rtl8723a_CheckAntenna_Selection(PADAPTER padapter);
void rtl8723a_init_default_value(PADAPTER padapter);
s32 InitLLTTable(PADAPTER padapter, u32 boundary);
s32 CardDisableHWSM(PADAPTER padapter, u8 resetMCU);
s32 CardDisableWithoutHWSM(PADAPTER padapter);
// EFuse
u8 GetEEPROMSize8723A(PADAPTER padapter);
void Hal_InitPGData(PADAPTER padapter, u8 *PROMContent);
void Hal_EfuseParseIDCode(PADAPTER padapter, u8 *hwinfo);
void Hal_EfuseParseTxPowerInfo_8723A(PADAPTER padapter, u8 *PROMContent, BOOLEAN AutoLoadFail);
void Hal_EfuseParseBTCoexistInfo_8723A(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
void Hal_EfuseParseEEPROMVer(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
void rtl8723a_EfuseParseChnlPlan(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
void Hal_EfuseParseCustomerID(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
void Hal_EfuseParseAntennaDiversity(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
void Hal_EfuseParseRateIndicationOption(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
void Hal_EfuseParseXtal_8723A(PADAPTER pAdapter, u8 *hwinfo, u8 AutoLoadFail);
void Hal_EfuseParseThermalMeter_8723A(PADAPTER padapter, u8 *hwinfo, u8 AutoLoadFail);
//RT_CHANNEL_DOMAIN rtl8723a_HalMapChannelPlan(PADAPTER padapter, u8 HalChannelPlan);
//VERSION_8192C rtl8723a_ReadChipVersion(PADAPTER padapter);
//void rtl8723a_ReadBluetoothCoexistInfo(PADAPTER padapter, u8 *PROMContent, BOOLEAN AutoloadFail);
void Hal_InitChannelPlan(PADAPTER padapter);
void rtl8723a_set_hal_ops(struct hal_ops *pHalFunc);
void SetHwReg8723A(PADAPTER padapter, u8 variable, u8 *val);
void GetHwReg8723A(PADAPTER padapter, u8 variable, u8 *val);
u8 GetHalDefVar8723A(PADAPTER Adapter, HAL_DEF_VARIABLE eVariable, PVOID pValue);
#ifdef CONFIG_BT_COEXIST
void rtl8723a_SingleDualAntennaDetection(PADAPTER padapter);
#endif
int FirmwareDownloadBT(PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware);
// register
void SetBcnCtrlReg(PADAPTER padapter, u8 SetBits, u8 ClearBits);
void rtl8723a_InitBeaconParameters(PADAPTER padapter);
void rtl8723a_InitBeaconMaxError(PADAPTER padapter, u8 InfraMode);
void rtl8723a_start_thread(_adapter *padapter);
void rtl8723a_stop_thread(_adapter *padapter);
s32 c2h_id_filter_ccx_8723a(u8 *buf);
void _InitTransferPageSize(PADAPTER padapter);
#endif// __RTL8723A_HAL_H__

41
include/rtl8723a_recv.h
View File

@@ -1,41 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTL8723A_RECV_H__
#define __RTL8723A_RECV_H__
#include <rtl8192c_recv.h>
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
#ifdef CONFIG_DIRECT_RECV
void rtl8723as_recv(PADAPTER padapter, struct recv_buf *precvbuf);
#endif
s32 rtl8723as_init_recv_priv(PADAPTER padapter);
void rtl8723as_free_recv_priv(PADAPTER padapter);
#endif
void rtl8192c_query_rx_phy_status(union recv_frame *prframe, struct phy_stat *pphy_stat);
void rtl8192c_process_phy_info(PADAPTER padapter, void *prframe);
#ifdef CONFIG_USB_HCI
void update_recvframe_attrib(union recv_frame *precvframe, struct recv_stat *prxstat);
void update_recvframe_phyinfo(union recv_frame *precvframe, struct phy_stat *pphy_info);
#endif
#endif

105
include/rtl8723a_spec.h
View File

@@ -1,105 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*******************************************************************************/
#ifndef __RTL8723A_SPEC_H__
#define __RTL8723A_SPEC_H__
#include <rtl8192c_spec.h>
//============================================================================
// 8723A Regsiter offset definition
//============================================================================
//-----------------------------------------------------
//
// 0x0000h ~ 0x00FFh System Configuration
//
//-----------------------------------------------------
//-----------------------------------------------------
//
// 0x0100h ~ 0x01FFh MACTOP General Configuration
//
//-----------------------------------------------------
//-----------------------------------------------------
//
// 0x0200h ~ 0x027Fh TXDMA Configuration
//
//-----------------------------------------------------
//-----------------------------------------------------
//
// 0x0280h ~ 0x02FFh RXDMA Configuration
//
//-----------------------------------------------------
//-----------------------------------------------------
//
// 0x0300h ~ 0x03FFh PCIe
//
//-----------------------------------------------------
//-----------------------------------------------------
//
// 0x0400h ~ 0x047Fh Protocol Configuration
//
//-----------------------------------------------------
//-----------------------------------------------------
//
// 0x0500h ~ 0x05FFh EDCA Configuration
//
//-----------------------------------------------------
//-----------------------------------------------------
//
// 0x0600h ~ 0x07FFh WMAC Configuration
//
//-----------------------------------------------------
#define REG_BT_COEX_TABLE_1 0x06C0
#define REG_BT_COEX_TABLE_2 0x06C4
//============================================================================
// 8723 Regsiter Bit and Content definition
//============================================================================
//2 HSISR
// interrupt mask which needs to clear
#define MASK_HSISR_CLEAR (HSISR_GPIO12_0_INT |\
HSISR_SPS_OCP_INT |\
HSISR_RON_INT |\
HSISR_PDNINT |\
HSISR_GPIO9_INT)
//----------------------------------------------------------------------------
// 8723 EFUSE
//----------------------------------------------------------------------------
//============================================================================
// General definitions
//============================================================================
#define MACID_NUM_8723A 32
#define CAM_ENTRY_NUM_8723A 32
#endif /* __RTL8723A_SPEC_H__ */

237
include/rtl8723a_xmit.h
View File

@@ -1,237 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTL8723A_XMIT_H__
#define __RTL8723A_XMIT_H__
#include <rtl8192c_xmit.h>
//
//defined for TX DESC Operation
//
#define MAX_TID (15)
//OFFSET 0
#define OFFSET_SZ 0
#define OFFSET_SHT 16
#define BMC BIT(24)
#define LSG BIT(26)
#define FSG BIT(27)
#define OWN BIT(31)
//OFFSET 4
#define PKT_OFFSET_SZ 0
#define BK BIT(6)
#define QSEL_SHT 8
#define Rate_ID_SHT 16
#define NAVUSEHDR BIT(20)
#define PKT_OFFSET_SHT 26
#define HWPC BIT(31)
//OFFSET 8
#define AGG_EN BIT(29)
#define AMPDU_DENSITY_SHT 20
//OFFSET 12
#define SEQ_SHT 16
//OFFSET 16
#define QoS BIT(6)
#define HW_SEQ_EN BIT(7)
#define USERATE BIT(8)
#define DISDATAFB BIT(10)
#define DATA_SHORT BIT(24)
#define DATA_BW BIT(25)
//OFFSET 20
#define SGI BIT(6)
typedef struct txdesc_8723a
{
u32 pktlen:16;
u32 offset:8;
u32 bmc:1;
u32 htc:1;
u32 ls:1;
u32 fs:1;
u32 linip:1;
u32 noacm:1;
u32 gf:1;
u32 own:1;
u32 macid:5;
u32 agg_en:1;
u32 bk:1;
u32 rd_en:1;
u32 qsel:5;
u32 rd_nav_ext:1;
u32 lsig_txop_en:1;
u32 pifs:1;
u32 rate_id:4;
u32 navusehdr:1;
u32 en_desc_id:1;
u32 sectype:2;
u32 rsvd0424:2;
u32 pkt_offset:5; // unit: 8 bytes
u32 rsvd0431:1;
u32 rts_rc:6;
u32 data_rc:6;
u32 rsvd0812:2;
u32 bar_rty_th:2;
u32 rsvd0816:1;
u32 morefrag:1;
u32 raw:1;
u32 ccx:1;
u32 ampdu_density:3;
u32 bt_null:1;
u32 ant_sel_a:1;
u32 ant_sel_b:1;
u32 tx_ant_cck:2;
u32 tx_antl:2;
u32 tx_ant_ht:2;
u32 nextheadpage:8;
u32 tailpage:8;
u32 seq:12;
u32 cpu_handle:1;
u32 tag1:1;
u32 trigger_int:1;
u32 hwseq_en:1;
u32 rtsrate:5;
u32 ap_dcfe:1;
u32 hwseq_sel:2;
u32 userate:1;
u32 disrtsfb:1;
u32 disdatafb:1;
u32 cts2self:1;
u32 rtsen:1;
u32 hw_rts_en:1;
u32 port_id:1;
u32 rsvd1615:3;
u32 wait_dcts:1;
u32 cts2ap_en:1;
u32 data_sc:2;
u32 data_stbc:2;
u32 data_short:1;
u32 data_bw:1;
u32 rts_short:1;
u32 rts_bw:1;
u32 rts_sc:2;
u32 vcs_stbc:2;
u32 datarate:6;
u32 sgi:1;
u32 try_rate:1;
u32 data_ratefb_lmt:5;
u32 rts_ratefb_lmt:4;
u32 rty_lmt_en:1;
u32 data_rt_lmt:6;
u32 usb_txagg_num:8;
u32 txagg_a:5;
u32 txagg_b:5;
u32 use_max_len:1;
u32 max_agg_num:5;
u32 mcsg1_max_len:4;
u32 mcsg2_max_len:4;
u32 mcsg3_max_len:4;
u32 mcs7_sgi_max_len:4;
u32 checksum:16; // TxBuffSize(PCIe)/CheckSum(USB)
u32 mcsg4_max_len:4;
u32 mcsg5_max_len:4;
u32 mcsg6_max_len:4;
u32 mcs15_sgi_max_len:4;
}TXDESC_8723A, *PTXDESC_8723A;
#define txdesc_set_ccx_sw_8723a(txdesc, value) \
do { \
((struct txdesc_8723a *)(txdesc))->mcsg4_max_len = (((value)>>8) & 0x0f); \
((struct txdesc_8723a *)(txdesc))->mcs15_sgi_max_len= (((value)>>4) & 0x0f); \
((struct txdesc_8723a *)(txdesc))->mcsg6_max_len = ((value) & 0x0f); \
} while (0)
struct txrpt_ccx_8723a {
/* offset 0 */
u8 tag1:1;
u8 rsvd:4;
u8 int_bt:1;
u8 int_tri:1;
u8 int_ccx:1;
/* offset 1 */
u8 mac_id:5;
u8 pkt_drop:1;
u8 pkt_ok:1;
u8 bmc:1;
/* offset 2 */
u8 retry_cnt:6;
u8 lifetime_over:1;
u8 retry_over:1;
/* offset 3 */
u8 ccx_qtime0;
u8 ccx_qtime1;
/* offset 5 */
u8 final_data_rate;
/* offset 6 */
u8 sw1:4;
u8 qsel:4;
/* offset 7 */
u8 sw0;
};
#define txrpt_ccx_sw_8723a(txrpt_ccx) ((txrpt_ccx)->sw0 + ((txrpt_ccx)->sw1<<8))
#define txrpt_ccx_qtime_8723a(txrpt_ccx) ((txrpt_ccx)->ccx_qtime0+((txrpt_ccx)->ccx_qtime1<<8))
#ifdef CONFIG_XMIT_ACK
void dump_txrpt_ccx_8723a(void *buf);
void handle_txrpt_ccx_8723a(_adapter *adapter, void *buf);
#else
#define dump_txrpt_ccx_8723a(buf) do {} while(0)
#define handle_txrpt_ccx_8723a(adapter, buf) do {} while(0)
#endif //CONFIG_XMIT_ACK
void rtl8723a_update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem);
void rtl8723a_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull);
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
s32 rtl8723as_init_xmit_priv(PADAPTER padapter);
void rtl8723as_free_xmit_priv(PADAPTER padapter);
s32 rtl8723as_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
s32 rtl8723as_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
s32 rtl8723as_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
s32 rtl8723as_xmit_buf_handler(PADAPTER padapter);
thread_return rtl8723as_xmit_thread(thread_context context);
#endif
#ifdef CONFIG_USB_HCI
s32 rtl8723au_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
s32 rtl8723au_xmit_buf_handler(PADAPTER padapter);
#endif
#endif

205
include/rtl8723b_cmd.h
View File

@@ -56,6 +56,7 @@ enum h2c_cmd_8723B{
H2C_8723B_RSSI_SETTING = 0x42,
H2C_8723B_AP_REQ_TXRPT = 0x43,
H2C_8723B_INIT_RATE_COLLECT = 0x44,
H2C_8723B_RA_PARA_ADJUST = 0x46,
//BT Class: 011
H2C_8723B_B_TYPE_TDMA = 0x60,
@@ -80,114 +81,44 @@ enum h2c_cmd_8723B{
H2C_8723B_D0_SCAN_OFFLOAD_CTRL = 0x85,
H2C_8723B_D0_SCAN_OFFLOAD_INFO = 0x86,
H2C_8723B_CHNL_SWITCH_OFFLOAD = 0x87,
H2C_8723B_P2P_OFFLOAD_RSVD_PAGE = 0x8A,
H2C_8723B_P2P_OFFLOAD = 0x8B,
H2C_8723B_RESET_TSF = 0xC0,
H2C_8723B_MAXID,
};
/* move to hal_com_h2c.h
#define H2C_8723B_RSVDPAGE_LOC_LEN 5
#define H2C_8723B_MEDIA_STATUS_RPT_LEN 3
#define H2C_8723B_KEEP_ALIVE_CTRL_LEN 2
#define H2C_8723B_DISCON_DECISION_LEN 3
#define H2C_8723B_BCN_RSVDPAGE_LEN 5
#define H2C_8723B_PROBERSP_RSVDPAGE_LEN 5
#define H2C_8723B_AP_OFFLOAD_LEN 3
#define H2C_8723B_AP_WOW_GPIO_CTRL_LEN 3
#define H2C_8723B_PWRMODE_LEN 7
#define H2C_8723B_PSTUNEPARAM_LEN 4
#define H2C_8723B_MACID_CFG_LEN 7
#define H2C_8723B_BTMP_OPER_LEN 4
#define H2C_8723B_WOWLAN_LEN 4
#define H2C_8723B_REMOTE_WAKE_CTRL_LEN 3
#define H2C_8723B_AOAC_GLOBAL_INFO_LEN 2
#define H2C_8723B_AOAC_RSVDPAGE_LOC_LEN 7
#define H2C_8723B_SCAN_OFFLOAD_CTRL_LEN 4
#define H2C_8723B_BT_FW_PATCH_LEN 6
#define H2C_8723B_RSSI_SETTING_LEN 4
#define H2C_8723B_AP_REQ_TXRPT_LEN 2
#define H2C_8723B_FORCE_BT_TXPWR_LEN 3
#ifdef CONFIG_WOWLAN
#define eqMacAddr(a,b) ( ((a)[0]==(b)[0] && (a)[1]==(b)[1] && (a)[2]==(b)[2] && (a)[3]==(b)[3] && (a)[4]==(b)[4] && (a)[5]==(b)[5]) ? 1:0 )
#define cpMacAddr(des,src) ((des)[0]=(src)[0],(des)[1]=(src)[1],(des)[2]=(src)[2],(des)[3]=(src)[3],(des)[4]=(src)[4],(des)[5]=(src)[5])
#define cpIpAddr(des,src) ((des)[0]=(src)[0],(des)[1]=(src)[1],(des)[2]=(src)[2],(des)[3]=(src)[3])
//
// ARP packet
//
// LLC Header
#define GET_ARP_PKT_LLC_TYPE(__pHeader) ReadEF2Byte( ((u8*)(__pHeader)) + 6)
//ARP element
#define GET_ARP_PKT_OPERATION(__pHeader) ReadEF2Byte( ((u8*)(__pHeader)) + 6)
#define GET_ARP_PKT_SENDER_MAC_ADDR(__pHeader, _val) cpMacAddr((u8*)(_val), ((u8*)(__pHeader))+8)
#define GET_ARP_PKT_SENDER_IP_ADDR(__pHeader, _val) cpIpAddr((u8*)(_val), ((u8*)(__pHeader))+14)
#define GET_ARP_PKT_TARGET_MAC_ADDR(__pHeader, _val) cpMacAddr((u8*)(_val), ((u8*)(__pHeader))+18)
#define GET_ARP_PKT_TARGET_IP_ADDR(__pHeader, _val) cpIpAddr((u8*)(_val), ((u8*)(__pHeader))+24)
#define SET_ARP_PKT_HW(__pHeader, __Value) WriteEF2Byte( ((u8*)(__pHeader)) + 0, __Value)
#define SET_ARP_PKT_PROTOCOL(__pHeader, __Value) WriteEF2Byte( ((u8*)(__pHeader)) + 2, __Value)
#define SET_ARP_PKT_HW_ADDR_LEN(__pHeader, __Value) WriteEF1Byte( ((u8*)(__pHeader)) + 4, __Value)
#define SET_ARP_PKT_PROTOCOL_ADDR_LEN(__pHeader, __Value) WriteEF1Byte( ((u8*)(__pHeader)) + 5, __Value)
#define SET_ARP_PKT_OPERATION(__pHeader, __Value) WriteEF2Byte( ((u8*)(__pHeader)) + 6, __Value)
#define SET_ARP_PKT_SENDER_MAC_ADDR(__pHeader, _val) cpMacAddr(((u8*)(__pHeader))+8, (u8*)(_val))
#define SET_ARP_PKT_SENDER_IP_ADDR(__pHeader, _val) cpIpAddr(((u8*)(__pHeader))+14, (u8*)(_val))
#define SET_ARP_PKT_TARGET_MAC_ADDR(__pHeader, _val) cpMacAddr(((u8*)(__pHeader))+18, (u8*)(_val))
#define SET_ARP_PKT_TARGET_IP_ADDR(__pHeader, _val) cpIpAddr(((u8*)(__pHeader))+24, (u8*)(_val))
#define FW_WOWLAN_FUN_EN BIT(0)
#define FW_WOWLAN_PATTERN_MATCH BIT(1)
#define FW_WOWLAN_MAGIC_PKT BIT(2)
#define FW_WOWLAN_UNICAST BIT(3)
#define FW_WOWLAN_ALL_PKT_DROP BIT(4)
#define FW_WOWLAN_GPIO_ACTIVE BIT(5)
#define FW_WOWLAN_REKEY_WAKEUP BIT(6)
#define FW_WOWLAN_DEAUTH_WAKEUP BIT(7)
#define FW_WOWLAN_GPIO_WAKEUP_EN BIT(0)
#define FW_FW_PARSE_MAGIC_PKT BIT(1)
#define FW_REMOTE_WAKE_CTRL_EN BIT(0)
#define FW_REALWOWLAN_EN BIT(5)
#endif //CONFIG_WOWLAN
*/
//---------------------------------------------------------------------------------------------------------//
//---------------------------------- H2C CMD CONTENT --------------------------------------------------//
//---------------------------------------------------------------------------------------------------------//
//_RSVDPAGE_LOC_CMD_0x00
#define SET_8723B_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT(__pH2CCmd, 0, 8, __Value)
#define SET_8723B_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+1, 0, 8, __Value)
#define SET_8723B_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+2, 0, 8, __Value)
#define SET_8723B_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+3, 0, 8, __Value)
#define SET_8723B_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+4, 0, 8, __Value)
//_MEDIA_STATUS_RPT_PARM_CMD_0x01
#define SET_8723B_H2CCMD_MSRRPT_PARM_OPMODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
#define SET_8723B_H2CCMD_MSRRPT_PARM_MACID_IND(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
#define SET_8723B_H2CCMD_MSRRPT_PARM_MACID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT(__pH2CCmd+1, 0, 8, __Value)
#define SET_8723B_H2CCMD_MSRRPT_PARM_MACID_END(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT(__pH2CCmd+2, 0, 8, __Value)
#define SET_8723B_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
#define SET_8723B_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
#define SET_8723B_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
#define SET_8723B_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
#define SET_8723B_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
//_KEEP_ALIVE_CMD_0x03
#define SET_8723B_H2CCMD_KEEPALIVE_PARM_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
#define SET_8723B_H2CCMD_KEEPALIVE_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
#define SET_8723B_H2CCMD_KEEPALIVE_PARM_PKT_TYPE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
#define SET_8723B_H2CCMD_KEEPALIVE_PARM_CHECK_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT(__pH2CCmd+1, 0, 8, __Value)
#define SET_8723B_H2CCMD_KEEPALIVE_PARM_CHECK_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
//_DISCONNECT_DECISION_CMD_0x04
#define SET_8723B_H2CCMD_DISCONDECISION_PARM_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
#define SET_8723B_H2CCMD_DISCONDECISION_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
#define SET_8723B_H2CCMD_DISCONDECISION_PARM_CHECK_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT(__pH2CCmd+1, 0, 8, __Value)
#define SET_8723B_H2CCMD_DISCONDECISION_PARM_TRY_PKT_NUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT(__pH2CCmd+2, 0, 8, __Value)
#define SET_8723B_H2CCMD_DISCONDECISION_PARM_CHECK_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
#define SET_8723B_H2CCMD_DISCONDECISION_PARM_TRY_PKT_NUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
// _PWR_MOD_CMD_0x20
#define SET_8723B_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT(__pH2CCmd, 0, 8, __Value)
#define SET_8723B_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
#define SET_8723B_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value)
#define SET_8723B_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value)
#define SET_8723B_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+2, 0, 8, __Value)
#define SET_8723B_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+3, 0, 8, __Value)
#define SET_8723B_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+4, 0, 8, __Value)
#define SET_8723B_H2CCMD_PWRMODE_PARM_BYTE5(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+5, 0, 8, __Value)
#define SET_8723B_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
#define SET_8723B_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
#define SET_8723B_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value)
#define SET_8723B_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
#define SET_8723B_H2CCMD_PWRMODE_PARM_BYTE5(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)
#define GET_8723B_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd) LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)
@@ -222,7 +153,7 @@ enum h2c_cmd_8723B{
#define SET_8723B_H2CCMD_APREQRPT_PARM_MACID2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
// _FORCE_BT_TXPWR_CMD_0x62
#define SET_8723B_H2CCMD_BT_PWR_IDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT(__pH2CCmd, 0, 8, __Value)
#define SET_8723B_H2CCMD_BT_PWR_IDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
// _FORCE_BT_MP_OPER_CMD_0x67
#define SET_8723B_H2CCMD_BT_MPOPER_VER(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)
@@ -238,90 +169,11 @@ enum h2c_cmd_8723B{
#define SET_8723B_H2CCMD_BT_FW_PATCH_ADDR1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
#define SET_8723B_H2CCMD_BT_FW_PATCH_ADDR2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
#define SET_8723B_H2CCMD_BT_FW_PATCH_ADDR3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)
/* move to hal_com_h2c.h
// _WoWLAN PARAM_CMD_0x80
#define SET_8723B_H2CCMD_WOWLAN_FUNC_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
#define SET_8723B_H2CCMD_WOWLAN_PATTERN_MATCH_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
#define SET_8723B_H2CCMD_WOWLAN_MAGIC_PKT_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
#define SET_8723B_H2CCMD_WOWLAN_UNICAST_PKT_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)
#define SET_8723B_H2CCMD_WOWLAN_ALL_PKT_DROP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value)
#define SET_8723B_H2CCMD_WOWLAN_GPIO_ACTIVE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value)
#define SET_8723B_H2CCMD_WOWLAN_REKEY_WAKE_UP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 6, 1, __Value)
#define SET_8723B_H2CCMD_WOWLAN_DISCONNECT_WAKE_UP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 7, 1, __Value)
#define SET_8723B_H2CCMD_WOWLAN_GPIONUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 7, __Value)
#define SET_8723B_H2CCMD_WOWLAN_DATAPIN_WAKE_UP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 7, 1, __Value)
#define SET_8723B_H2CCMD_WOWLAN_GPIO_DURATION(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
//#define SET_8723B_H2CCMD_WOWLAN_GPIO_PULSE_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 1, __Value)
#define SET_8723B_H2CCMD_WOWLAN_GPIO_PULSE_COUNT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
// _REMOTE_WAKEUP_CMD_0x81
#define SET_8723B_H2CCMD_REMOTE_WAKECTRL_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
#define SET_8723B_H2CCMD_REMOTE_WAKE_CTRL_ARP_OFFLOAD_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
#define SET_8723B_H2CCMD_REMOTE_WAKE_CTRL_NDP_OFFLOAD_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
#define SET_8723B_H2CCMD_REMOTE_WAKE_CTRL_GTK_OFFLOAD_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)
#define SET_8723B_H2CCMD_REMOTE_WAKE_CTRL_NLO_OFFLOAD_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value)
#define SET_8723B_H2CCMD_REMOTE_WAKE_CTRL_FW_UNICAST_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 7, 1, __Value)
#define SET_8723B_H2CCMD_REMOTE_WAKE_CTRL_ARP_ACTION(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 1, __Value)
// AOAC_GLOBAL_INFO_0x82
#define SET_8723B_H2CCMD_AOAC_GLOBAL_INFO_PAIRWISE_ENC_ALG(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
#define SET_8723B_H2CCMD_AOAC_GLOBAL_INFO_GROUP_ENC_ALG(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
// AOAC_RSVDPAGE_LOC_0x83
#define SET_8723B_H2CCMD_AOAC_RSVDPAGE_LOC_REMOTE_WAKE_CTRL_INFO(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 0, 8, __Value)
#define SET_8723B_H2CCMD_AOAC_RSVDPAGE_LOC_ARP_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
#define SET_8723B_H2CCMD_AOAC_RSVDPAGE_LOC_NEIGHBOR_ADV(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
#define SET_8723B_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
#define SET_8723B_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_INFO(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
#ifdef CONFIG_GTK_OL
#define SET_8723B_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_EXT_MEM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)
#endif //CONFIG_GTK_OL
#ifdef CONFIG_PNO_SUPPORT
#define SET_8723B_H2CCMD_AOAC_RSVDPAGE_LOC_NLO_INFO(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 0, 8, __Value)
#endif
#ifdef CONFIG_PNO_SUPPORT
// D0_Scan_Offload_Info_0x86
#define SET_8723B_H2CCMD_AOAC_NLO_FUN_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 3, 1, __Value)
#define SET_8723B_H2CCMD_AOAC_RSVDPAGE_LOC_PROBE_PACKET(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
#define SET_8723B_H2CCMD_AOAC_RSVDPAGE_LOC_SCAN_INFO(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
#define SET_8723B_H2CCMD_AOAC_RSVDPAGE_LOC_SSID_INFO(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
#endif //CONFIG_PNO_SUPPORT
*/
//---------------------------------------------------------------------------------------------------------//
//------------------------------------------- Structure --------------------------------------------------//
//---------------------------------------------------------------------------------------------------------//
/* move to hal_com_h2c.h
typedef struct _RSVDPAGE_LOC {
u8 LocProbeRsp;
u8 LocPsPoll;
u8 LocNullData;
u8 LocQosNull;
u8 LocBTQosNull;
#ifdef CONFIG_WOWLAN
u8 LocRemoteCtrlInfo;
u8 LocArpRsp;
u8 LocNbrAdv;
u8 LocGTKRsp;
u8 LocGTKInfo;
u8 LocProbeReq;
u8 LocNetList;
#ifdef CONFIG_GTK_OL
u8 LocGTKEXTMEM;
#endif //CONFIG_GTK_OL
#ifdef CONFIG_PNO_SUPPORT
u8 LocPNOInfo;
u8 LocScanInfo;
u8 LocSSIDInfo;
u8 LocProbePacket;
#endif //CONFIG_PNO_SUPPORT
#endif //CONFIG_WOWLAN
#ifdef CONFIG_AP_WOWLAN
u8 LocApOffloadBCN;
#endif //CONFIG_AP_WOWLAN
} RSVDPAGE_LOC_8723B, *PRSVDPAGE_LOC_8723B;
*/
//---------------------------------------------------------------------------------------------------------//
//---------------------------------- Function Statement --------------------------------------------------//
@@ -331,12 +183,11 @@ typedef struct _RSVDPAGE_LOC {
void rtl8723b_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode);
void rtl8723b_set_FwJoinBssRpt_cmd(PADAPTER padapter, u8 mstatus);
void rtl8723b_set_rssi_cmd(PADAPTER padapter, u8 *param);
void rtl8723b_Add_RateATid(PADAPTER pAdapter, u32 bitmap, u8* arg, u8 rssi_level);
void rtl8723b_Add_RateATid(PADAPTER pAdapter, u64 rate_bitmap, u8 *arg, u8 rssi_level);
void rtl8723b_fw_try_ap_cmd(PADAPTER padapter, u32 need_ack);
//s32 rtl8723b_set_lowpwr_lps_cmd(PADAPTER padapter, u8 enable);
void rtl8723b_set_FwPsTuneParam_cmd(PADAPTER padapter);
void rtl8723b_set_FwMacIdConfig_cmd(_adapter* padapter, u8 mac_id, u8 raid, u8 bw, u8 sgi, u32 mask);
void rtl8723b_set_FwMediaStatusRpt_cmd(PADAPTER padapter, u8 mstatus, u8 macid);
void rtl8723b_set_FwBtMpOper_cmd(PADAPTER padapter, u8 idx, u8 ver, u8 reqnum, u8 *param);
void rtl8723b_download_rsvd_page(PADAPTER padapter, u8 mstatus);
#ifdef CONFIG_BT_COEXIST
@@ -348,11 +199,15 @@ void rtl8723b_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);
void CheckFwRsvdPageContent(PADAPTER padapter);
#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
void rtl8723b_set_wowlan_cmd(_adapter* padapter, u8 enable);
void rtl8723b_set_ap_wowlan_cmd(_adapter* padapter, u8 enable);
void SetFwRelatedForWoWLAN8723b(_adapter* padapter, u8 bHostIsGoingtoSleep);
#endif//CONFIG_WOWLAN
#ifdef CONFIG_TDLS
#ifdef CONFIG_TDLS_CH_SW
void rtl8723b_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable);
#endif
#endif
#ifdef CONFIG_P2P_WOWLAN
void rtl8723b_set_p2p_wowlan_offload_cmd(PADAPTER padapter);
#endif
void rtl8723b_set_FwPwrModeInIPS_cmd(PADAPTER padapter, u8 cmd_param);
@@ -360,6 +215,6 @@ void rtl8723b_set_FwPwrModeInIPS_cmd(PADAPTER padapter, u8 cmd_param);
u8 rtl8723b_reset_tsf(_adapter *padapter, u8 reset_port);
#endif // CONFIG_TSF_RESET_OFFLOAD
s32 FillH2CCmd8723B(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
u8 GetTxBufferRsvdPageNum8723B(_adapter *padapter, bool wowlan);
#endif

50
include/rtl8723b_hal.h
View File

@@ -60,9 +60,6 @@
#define Rtl8723B_FwBTImgArray Rtl8723BFwBTImgArray
#define Rtl8723B_FwBTImgArrayLength Rtl8723BFwBTImgArrayLength
#define Rtl8723B_FwMPImageArray Rtl8723BFwMPImgArray
#define Rtl8723B_FwMPImgArrayLength Rtl8723BMPImgArrayLength
#define Rtl8723B_PHY_REG_Array_MP Rtl8723B_PHYREG_Array_MP
#define Rtl8723B_PHY_REG_Array_MPLength Rtl8723B_PHYREG_Array_MPLength
#endif
@@ -124,7 +121,15 @@ typedef struct _RT_8723B_FIRMWARE_HDR
#define PAGE_SIZE_TX_8723B 128
#define PAGE_SIZE_RX_8723B 8
#define RX_DMA_SIZE_8723B 0x4000 // 16K
#define TX_DMA_SIZE_8723B 0x8000 /* 32K(TX) */
#define RX_DMA_SIZE_8723B 0x4000 /* 16K(RX) */
#ifdef CONFIG_WOWLAN
#define RESV_FMWF WKFMCAM_SIZE*MAX_WKFM_NUM /* 16 entries, for each is 24 bytes*/
#else
#define RESV_FMWF 0
#endif
#ifdef CONFIG_FW_C2H_DEBUG
#define RX_DMA_RESERVED_SIZE_8723B 0x100 // 256B, reserved for c2h debug message
#else
@@ -148,7 +153,6 @@ typedef struct _RT_8723B_FIRMWARE_HDR
#undef BCNQ1_PAGE_NUM_8723B
#define BCNQ1_PAGE_NUM_8723B 0x00 // 0x04
#endif
#define MAX_RX_DMA_BUFFER_SIZE_8723B 0x2800 // RX 10K
//For WoWLan , more reserved page
//ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, PNO: 6
@@ -213,26 +217,6 @@ typedef struct _RT_8723B_FIRMWARE_HDR
#define EFUSE_PROTECT_BYTES_BANK 16
// Description: Determine the types of C2H events that are the same in driver and Fw.
// Fisrt constructed by tynli. 2009.10.09.
typedef enum _C2H_EVT
{
C2H_DBG = 0,
C2H_TSF = 1,
C2H_AP_RPT_RSP = 2,
C2H_CCX_TX_RPT = 3, // The FW notify the report of the specific tx packet.
C2H_BT_RSSI = 4,
C2H_BT_OP_MODE = 5,
C2H_EXT_RA_RPT = 6,
C2H_8723B_BT_INFO = 9,
C2H_HW_INFO_EXCH = 10,
C2H_8723B_BT_MP_INFO = 11,
#ifdef CONFIG_FW_C2H_DEBUG
C2H_8723B_FW_DEBUG = 0xff,
#endif //CONFIG_FW_C2H_DEBUG
MAX_C2HEVENT
} C2H_EVT;
typedef struct _C2H_EVT_HDR
{
u8 CmdID;
@@ -281,15 +265,20 @@ void Hal_EfuseParseXtal_8723B(PADAPTER pAdapter, u8 *hwinfo, u8 AutoLoadFail);
void Hal_EfuseParseThermalMeter_8723B(PADAPTER padapter, u8 *hwinfo, u8 AutoLoadFail);
VOID Hal_EfuseParsePackageType_8723B(PADAPTER pAdapter,u8* hwinfo,BOOLEAN AutoLoadFail);
VOID Hal_EfuseParseVoltage_8723B(PADAPTER pAdapter,u8* hwinfo,BOOLEAN AutoLoadFail);
VOID Hal_EfuseParseBoardType_8723B(PADAPTER Adapter, u8* PROMContent,BOOLEAN AutoloadFail);
#ifdef CONFIG_C2H_PACKET_EN
void C2HPacketHandler_8723B(PADAPTER padapter, u8 *pbuffer, u16 length);
void rtl8723b_c2h_packet_handler(PADAPTER padapter, u8 *pbuf, u16 length);
#endif
void rtl8723b_set_hal_ops(struct hal_ops *pHalFunc);
void init_hal_spec_8723b(_adapter *adapter);
void SetHwReg8723B(PADAPTER padapter, u8 variable, u8 *val);
void GetHwReg8723B(PADAPTER padapter, u8 variable, u8 *val);
#ifdef CONFIG_C2H_PACKET_EN
void SetHwRegWithBuf8723B(PADAPTER padapter, u8 variable, u8 *pbuf, int len);
#endif // CONFIG_C2H_PACKET_EN
u8 SetHalDefVar8723B(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
u8 GetHalDefVar8723B(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
@@ -298,7 +287,7 @@ void rtl8723b_InitBeaconParameters(PADAPTER padapter);
void rtl8723b_InitBeaconMaxError(PADAPTER padapter, u8 InfraMode);
void _InitBurstPktLen_8723BS(PADAPTER Adapter);
void _8051Reset8723(PADAPTER padapter);
#ifdef CONFIG_WOWLAN
#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
void Hal_DetectWoWMode(PADAPTER pAdapter);
#endif //CONFIG_WOWLAN
@@ -319,17 +308,14 @@ void HalSetOutPutGPIO(PADAPTER padapter, u8 index, u8 OutPutValue);
int FirmwareDownloadBT(IN PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware);
void CCX_FwC2HTxRpt_8723b(PADAPTER padapter, u8 *pdata, u8 len);
#ifdef CONFIG_FW_C2H_DEBUG
void Debug_FwC2H_8723b(PADAPTER padapter, u8 *pdata, u8 len);
#endif //CONFIG_FW_C2H_DEBUG
s32 c2h_id_filter_ccx_8723b(u8 *buf);
s32 c2h_handler_8723b(PADAPTER padapter, u8 *pC2hEvent);
u8 MRateToHwRate8723B(u8 rate);
u8 HwRateToMRate8723B(u8 rate);
#ifdef CONFIG_RF_GAIN_OFFSET
#ifdef CONFIG_RF_POWER_TRIM
void Hal_ReadRFGainOffset(PADAPTER pAdapter,u8* hwinfo,BOOLEAN AutoLoadFail);
#endif //CONFIG_RF_GAIN_OFFSET
#endif /*CONFIG_RF_POWER_TRIM*/
#ifdef CONFIG_PCI_HCI
BOOLEAN InterruptRecognized8723BE(PADAPTER Adapter);

171
include/rtl8723b_recv.h
View File

@@ -20,7 +20,48 @@
#ifndef __RTL8723B_RECV_H__
#define __RTL8723B_RECV_H__
#include <rtl8192c_recv.h>
#define RECV_BLK_SZ 512
#define RECV_BLK_CNT 16
#define RECV_BLK_TH RECV_BLK_CNT
#if defined(CONFIG_USB_HCI)
#ifndef MAX_RECVBUF_SZ
#ifdef PLATFORM_OS_CE
#define MAX_RECVBUF_SZ (8192+1024) // 8K+1k
#else
#ifndef CONFIG_MINIMAL_MEMORY_USAGE
//#define MAX_RECVBUF_SZ (32768) // 32k
//#define MAX_RECVBUF_SZ (16384) //16K
//#define MAX_RECVBUF_SZ (10240) //10K
#ifdef CONFIG_PLATFORM_MSTAR
#define MAX_RECVBUF_SZ (8192) // 8K
#else
#define MAX_RECVBUF_SZ (15360) // 15k < 16k
#endif
//#define MAX_RECVBUF_SZ (8192+1024) // 8K+1k
#else
#define MAX_RECVBUF_SZ (4000) // about 4K
#endif
#endif
#endif //!MAX_RECVBUF_SZ
#elif defined(CONFIG_PCI_HCI)
//#ifndef CONFIG_MINIMAL_MEMORY_USAGE
// #define MAX_RECVBUF_SZ (9100)
//#else
#define MAX_RECVBUF_SZ (4000) // about 4K
//#endif
#elif defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
#define MAX_RECVBUF_SZ (10240)
#endif
// Rx smooth factor
#define Rx_Smooth_Factor (20)
#ifdef CONFIG_SDIO_HCI
#ifndef CONFIG_SDIO_RX_COPY
@@ -29,135 +70,13 @@
#endif // !CONFIG_SDIO_RX_COPY
#endif // CONFIG_SDIO_HCI
typedef struct rxreport_8723b
{
//DWORD 0
u32 pktlen:14;
u32 crc32:1;
u32 icverr:1;
u32 drvinfosize:4;
u32 security:3;
u32 qos:1;
u32 shift:2;
u32 physt:1;
u32 swdec:1;
u32 rsvd0028:2;
u32 eor:1;
u32 rsvd0031:1;
//DWORD 1
u32 macid:7;
u32 rsvd0407:1;
u32 tid:4;
u32 macid_vld:1;
u32 amsdu:1;
u32 rxid_match:1;
u32 paggr:1;
u32 a1fit:4;
u32 chkerr:1; //20
u32 rx_ipv:1;
u32 rx_is_tcp_udp:1;
u32 chk_vld:1; //23
u32 pam:1;
u32 pwr:1;
u32 md:1;
u32 mf:1;
u32 type:2;
u32 mc:1;
u32 bc:1;
//DWORD 2
u32 seq:12;
u32 frag:4;
u32 rx_is_qos:1;
u32 rsvd0817:1;
u32 wlanhd_iv_len:6;
u32 hwrsvd0824:4;
u32 c2h_ind:1;
u32 rsvd0829:2;
u32 fcs_ok:1;
//DWORD 3
u32 rx_rate:7;
u32 rsvd1207:3;
u32 htc:1;
u32 esop:1;
u32 bssid_fit:2;
u32 rsvd1214:2;
u32 dma_agg_num:8;
u32 rsvd1224:5;
u32 patternmatch:1;
u32 unicastwake:1;
u32 magicwake:1;
//DWORD 4
u32 splcp:1; //Ofdm sgi or cck_splcp
u32 ldpc:1;
u32 stbc:1;
u32 not_sounding:1;
u32 bw:2;
u32 rsvd1606:26;
//DWORD 5
u32 tsfl;
} RXREPORT, *PRXREPORT;
typedef struct phystatus_8723b
{
u32 rxgain_a:7;
u32 trsw_a:1;
u32 rxgain_b:7;
u32 trsw_b:1;
u32 chcorr_l:16;
u32 sigqualcck:8;
u32 cfo_a:8;
u32 cfo_b:8;
u32 chcorr_h:8;
u32 noisepwrdb_h:8;
u32 cfo_tail_a:8;
u32 cfo_tail_b:8;
u32 rsvd0824:8;
u32 rsvd1200:8;
u32 rxevm_a:8;
u32 rxevm_b:8;
u32 rxsnr_a:8;
u32 rxsnr_b:8;
u32 noisepwrdb_l:8;
u32 rsvd1616:8;
u32 postsnr_a:8;
u32 postsnr_b:8;
u32 csi_a:8;
u32 csi_b:8;
u32 targetcsi_a:8;
u32 targetcsi_b:8;
u32 sigevm:8;
u32 maxexpwr:8;
u32 exintflag:1;
u32 sgien:1;
u32 rxsc:2;
u32 idlelong:1;
u32 anttrainen:1;
u32 antselb:1;
u32 antsel:1;
} PHYSTATUS, *PPHYSTATUS;
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
s32 rtl8723bs_init_recv_priv(PADAPTER padapter);
void rtl8723bs_free_recv_priv(PADAPTER padapter);
#endif
void rtl8723b_query_rx_phy_status(union recv_frame *prframe, struct phy_stat *pphy_stat);
void rtl8723b_process_phy_info(PADAPTER padapter, void *prframe);
#ifdef CONFIG_USB_HCI
void update_recvframe_attrib(PADAPTER padapter, union recv_frame *precvframe, struct recv_stat *prxstat);
void update_recvframe_phyinfo(union recv_frame *precvframe, struct phy_stat *pphy_info);
int rtl8723bu_init_recv_priv(_adapter *padapter);
int rtl8723bu_init_recv_priv(_adapter *padapter);
void rtl8723bu_free_recv_priv (_adapter *padapter);
void rtl8723bu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf);
#endif
@@ -167,7 +86,7 @@ s32 rtl8723be_init_recv_priv(PADAPTER padapter);
void rtl8723be_free_recv_priv(PADAPTER padapter);
#endif
void rtl8723b_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc);
void rtl8723b_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc);
#endif
#endif /* __RTL8723B_RECV_H__ */

2
include/rtl8723b_rf.h
View File

@@ -20,8 +20,6 @@
#ifndef __RTL8723B_RF_H__
#define __RTL8723B_RF_H__
#include "rtl8192c_rf.h"
int PHY_RF6052_Config8723B( IN PADAPTER Adapter );
VOID

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