2015-08-18 19:03:09 +00:00
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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*
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******************************************************************************/
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#ifndef __INC_HAL8812PHYREG_H__
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#define __INC_HAL8812PHYREG_H__
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/*--------------------------Define Parameters-------------------------------*/
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//
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// BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
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// 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
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// 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
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// 3. RF register 0x00-2E
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// 4. Bit Mask for BB/RF register
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// 5. Other defintion for BB/RF R/W
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//
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// BB Register Definition
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#define rCCAonSec_Jaguar 0x838
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#define rPwed_TH_Jaguar 0x830
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// BW and sideband setting
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#define rBWIndication_Jaguar 0x834
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#define rL1PeakTH_Jaguar 0x848
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#define rRFMOD_Jaguar 0x8ac //RF mode
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#define rADC_Buf_Clk_Jaguar 0x8c4
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#define rRFECTRL_Jaguar 0x900
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#define bRFMOD_Jaguar 0xc3
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#define rCCK_System_Jaguar 0xa00 // for cck sideband
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#define bCCK_System_Jaguar 0x10
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// Block & Path enable
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#define rOFDMCCKEN_Jaguar 0x808 // OFDM/CCK block enable
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#define bOFDMEN_Jaguar 0x20000000
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#define bCCKEN_Jaguar 0x10000000
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#define rRxPath_Jaguar 0x808 // Rx antenna
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#define bRxPath_Jaguar 0xff
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#define rTxPath_Jaguar 0x80c // Tx antenna
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#define bTxPath_Jaguar 0x0fffffff
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#define rCCK_RX_Jaguar 0xa04 // for cck rx path selection
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#define bCCK_RX_Jaguar 0x0c000000
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#define rVhtlen_Use_Lsig_Jaguar 0x8c3 // Use LSIG for VHT length
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// RF read/write-related
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#define rHSSIRead_Jaguar 0x8b0 // RF read addr
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#define bHSSIRead_addr_Jaguar 0xff
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#define bHSSIRead_trigger_Jaguar 0x100
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#define rA_PIRead_Jaguar 0xd04 // RF readback with PI
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#define rB_PIRead_Jaguar 0xd44 // RF readback with PI
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#define rA_SIRead_Jaguar 0xd08 // RF readback with SI
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#define rB_SIRead_Jaguar 0xd48 // RF readback with SI
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#define rRead_data_Jaguar 0xfffff
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#define rA_LSSIWrite_Jaguar 0xc90 // RF write addr
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#define rB_LSSIWrite_Jaguar 0xe90 // RF write addr
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#define bLSSIWrite_data_Jaguar 0x000fffff
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#define bLSSIWrite_addr_Jaguar 0x0ff00000
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// YN: mask the following register definition temporarily
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#define rFPGA0_XA_RFInterfaceOE 0x860 // RF Channel switch
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#define rFPGA0_XB_RFInterfaceOE 0x864
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#define rFPGA0_XAB_RFInterfaceSW 0x870 // RF Interface Software Control
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#define rFPGA0_XCD_RFInterfaceSW 0x874
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//#define rFPGA0_XAB_RFParameter 0x878 // RF Parameter
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//#define rFPGA0_XCD_RFParameter 0x87c
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//#define rFPGA0_AnalogParameter1 0x880 // Crystal cap setting RF-R/W protection for parameter4??
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//#define rFPGA0_AnalogParameter2 0x884
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//#define rFPGA0_AnalogParameter3 0x888
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//#define rFPGA0_AdDaClockEn 0x888 // enable ad/da clock1 for dual-phy
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//#define rFPGA0_AnalogParameter4 0x88c
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// CCK TX scaling
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#define rCCK_TxFilter1_Jaguar 0xa20
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#define bCCK_TxFilter1_C0_Jaguar 0x00ff0000
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#define bCCK_TxFilter1_C1_Jaguar 0xff000000
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#define rCCK_TxFilter2_Jaguar 0xa24
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#define bCCK_TxFilter2_C2_Jaguar 0x000000ff
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#define bCCK_TxFilter2_C3_Jaguar 0x0000ff00
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#define bCCK_TxFilter2_C4_Jaguar 0x00ff0000
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#define bCCK_TxFilter2_C5_Jaguar 0xff000000
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#define rCCK_TxFilter3_Jaguar 0xa28
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#define bCCK_TxFilter3_C6_Jaguar 0x000000ff
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#define bCCK_TxFilter3_C7_Jaguar 0x0000ff00
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// YN: mask the following register definition temporarily
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//#define rPdp_AntA 0xb00
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//#define rPdp_AntA_4 0xb04
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//#define rConfig_Pmpd_AntA 0xb28
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//#define rConfig_AntA 0xb68
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//#define rConfig_AntB 0xb6c
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//#define rPdp_AntB 0xb70
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//#define rPdp_AntB_4 0xb74
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//#define rConfig_Pmpd_AntB 0xb98
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//#define rAPK 0xbd8
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// RXIQC
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#define rA_RxIQC_AB_Jaguar 0xc10 //RxIQ imblance matrix coeff. A & B
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#define rA_RxIQC_CD_Jaguar 0xc14 //RxIQ imblance matrix coeff. C & D
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#define rA_TxScale_Jaguar 0xc1c // Pah_A TX scaling factor
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#define rB_TxScale_Jaguar 0xe1c // Path_B TX scaling factor
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#define rB_RxIQC_AB_Jaguar 0xe10 //RxIQ imblance matrix coeff. A & B
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#define rB_RxIQC_CD_Jaguar 0xe14 //RxIQ imblance matrix coeff. C & D
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#define b_RxIQC_AC_Jaguar 0x02ff // bit mask for IQC matrix element A & C
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#define b_RxIQC_BD_Jaguar 0x02ff0000 // bit mask for IQC matrix element A & C
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// DIG-related
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#define rA_IGI_Jaguar 0xc50 // Initial Gain for path-A
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#define rB_IGI_Jaguar 0xe50 // Initial Gain for path-B
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#define rOFDM_FalseAlarm1_Jaguar 0xf48 // counter for break
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#define rOFDM_FalseAlarm2_Jaguar 0xf4c // counter for spoofing
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#define rCCK_FalseAlarm_Jaguar 0xa5c // counter for cck false alarm
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#define b_FalseAlarm_Jaguar 0xffff
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#define rCCK_CCA_Jaguar 0xa08 // cca threshold
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#define bCCK_CCA_Jaguar 0x00ff0000
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// Tx Power Ttraining-related
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#define rA_TxPwrTraing_Jaguar 0xc54
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#define rB_TxPwrTraing_Jaguar 0xe54
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// Report-related
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#define rOFDM_ShortCFOAB_Jaguar 0xf60
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#define rOFDM_LongCFOAB_Jaguar 0xf64
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#define rOFDM_EndCFOAB_Jaguar 0xf70
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#define rOFDM_AGCReport_Jaguar 0xf84
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#define rOFDM_RxSNR_Jaguar 0xf88
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#define rOFDM_RxEVMCSI_Jaguar 0xf8c
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#define rOFDM_SIGReport_Jaguar 0xf90
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// Misc functions
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#define rEDCCA_Jaguar 0x8a4 // EDCCA
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#define bEDCCA_Jaguar 0xffff
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#define rAGC_table_Jaguar 0x82c // AGC tabel select
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#define bAGC_table_Jaguar 0x3
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#define b_sel5g_Jaguar 0x1000 // sel5g
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#define b_LNA_sw_Jaguar 0x8000 // HW/WS control for LNA
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#define rFc_area_Jaguar 0x860 // fc_area
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#define bFc_area_Jaguar 0x1ffe000
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#define rSingleTone_ContTx_Jaguar 0x914
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// RFE
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#define rA_RFE_Pinmux_Jaguar 0xcb0 // Path_A RFE cotrol pinmux
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#define rB_RFE_Pinmux_Jaguar 0xeb0 // Path_B RFE control pinmux
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#define rA_RFE_Inv_Jaguar 0xcb4 // Path_A RFE cotrol
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#define rB_RFE_Inv_Jaguar 0xeb4 // Path_B RFE control
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#define rA_RFE_Jaguar 0xcb8 // Path_A RFE cotrol
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#define rB_RFE_Jaguar 0xeb8 // Path_B RFE control
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#define r_ANTSEL_SW_Jaguar 0x900 // ANTSEL SW Control
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#define bMask_RFEInv_Jaguar 0x3ff00000
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#define bMask_AntselPathFollow_Jaguar 0x00030000
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// TX AGC
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#define rTxAGC_A_CCK11_CCK1_JAguar 0xc20
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#define rTxAGC_A_Ofdm18_Ofdm6_JAguar 0xc24
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#define rTxAGC_A_Ofdm54_Ofdm24_JAguar 0xc28
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#define rTxAGC_A_MCS3_MCS0_JAguar 0xc2c
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#define rTxAGC_A_MCS7_MCS4_JAguar 0xc30
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#define rTxAGC_A_MCS11_MCS8_JAguar 0xc34
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#define rTxAGC_A_MCS15_MCS12_JAguar 0xc38
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#define rTxAGC_A_Nss1Index3_Nss1Index0_JAguar 0xc3c
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#define rTxAGC_A_Nss1Index7_Nss1Index4_JAguar 0xc40
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#define rTxAGC_A_Nss2Index1_Nss1Index8_JAguar 0xc44
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#define rTxAGC_A_Nss2Index5_Nss2Index2_JAguar 0xc48
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#define rTxAGC_A_Nss2Index9_Nss2Index6_JAguar 0xc4c
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#define rTxAGC_B_CCK11_CCK1_JAguar 0xe20
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#define rTxAGC_B_Ofdm18_Ofdm6_JAguar 0xe24
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#define rTxAGC_B_Ofdm54_Ofdm24_JAguar 0xe28
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#define rTxAGC_B_MCS3_MCS0_JAguar 0xe2c
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#define rTxAGC_B_MCS7_MCS4_JAguar 0xe30
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#define rTxAGC_B_MCS11_MCS8_JAguar 0xe34
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#define rTxAGC_B_MCS15_MCS12_JAguar 0xe38
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#define rTxAGC_B_Nss1Index3_Nss1Index0_JAguar 0xe3c
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#define rTxAGC_B_Nss1Index7_Nss1Index4_JAguar 0xe40
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#define rTxAGC_B_Nss2Index1_Nss1Index8_JAguar 0xe44
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#define rTxAGC_B_Nss2Index5_Nss2Index2_JAguar 0xe48
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#define rTxAGC_B_Nss2Index9_Nss2Index6_JAguar 0xe4c
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#define bTxAGC_byte0_Jaguar 0xff
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#define bTxAGC_byte1_Jaguar 0xff00
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#define bTxAGC_byte2_Jaguar 0xff0000
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#define bTxAGC_byte3_Jaguar 0xff000000
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// IQK YN: temporaily mask this part
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//#define rFPGA0_IQK 0xe28
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//#define rTx_IQK_Tone_A 0xe30
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//#define rRx_IQK_Tone_A 0xe34
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//#define rTx_IQK_PI_A 0xe38
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//#define rRx_IQK_PI_A 0xe3c
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//#define rTx_IQK 0xe40
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//#define rRx_IQK 0xe44
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//#define rIQK_AGC_Pts 0xe48
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//#define rIQK_AGC_Rsp 0xe4c
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//#define rTx_IQK_Tone_B 0xe50
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//#define rRx_IQK_Tone_B 0xe54
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//#define rTx_IQK_PI_B 0xe58
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//#define rRx_IQK_PI_B 0xe5c
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//#define rIQK_AGC_Cont 0xe60
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// AFE-related
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#define rA_AFEPwr1_Jaguar 0xc60 // dynamic AFE power control
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#define rA_AFEPwr2_Jaguar 0xc64 // dynamic AFE power control
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#define rA_Rx_WaitCCA_Tx_CCKRFON_Jaguar 0xc68
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#define rA_Tx_CCKBBON_OFDMRFON_Jaguar 0xc6c
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#define rA_Tx_OFDMBBON_Tx2Rx_Jaguar 0xc70
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#define rA_Tx2Tx_RXCCK_Jaguar 0xc74
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#define rA_Rx_OFDM_WaitRIFS_Jaguar 0xc78
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#define rA_Rx2Rx_BT_Jaguar 0xc7c
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#define rA_sleep_nav_Jaguar 0xc80
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#define rA_pmpd_Jaguar 0xc84
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#define rB_AFEPwr1_Jaguar 0xe60 // dynamic AFE power control
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#define rB_AFEPwr2_Jaguar 0xe64 // dynamic AFE power control
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#define rB_Rx_WaitCCA_Tx_CCKRFON_Jaguar 0xe68
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#define rB_Tx_CCKBBON_OFDMRFON_Jaguar 0xe6c
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#define rB_Tx_OFDMBBON_Tx2Rx_Jaguar 0xe70
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#define rB_Tx2Tx_RXCCK_Jaguar 0xe74
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#define rB_Rx_OFDM_WaitRIFS_Jaguar 0xe78
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#define rB_Rx2Rx_BT_Jaguar 0xe7c
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#define rB_sleep_nav_Jaguar 0xe80
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#define rB_pmpd_Jaguar 0xe84
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// YN: mask these registers temporaily
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//#define rTx_Power_Before_IQK_A 0xe94
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//#define rTx_Power_After_IQK_A 0xe9c
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//#define rRx_Power_Before_IQK_A 0xea0
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//#define rRx_Power_Before_IQK_A_2 0xea4
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//#define rRx_Power_After_IQK_A 0xea8
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//#define rRx_Power_After_IQK_A_2 0xeac
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//#define rTx_Power_Before_IQK_B 0xeb4
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//#define rTx_Power_After_IQK_B 0xebc
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//#define rRx_Power_Before_IQK_B 0xec0
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//#define rRx_Power_Before_IQK_B_2 0xec4
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//#define rRx_Power_After_IQK_B 0xec8
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//#define rRx_Power_After_IQK_B_2 0xecc
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// RSSI Dump
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#define rA_RSSIDump_Jaguar 0xBF0
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#define rB_RSSIDump_Jaguar 0xBF1
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#define rS1_RXevmDump_Jaguar 0xBF4
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#define rS2_RXevmDump_Jaguar 0xBF5
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#define rA_RXsnrDump_Jaguar 0xBF6
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#define rB_RXsnrDump_Jaguar 0xBF7
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#define rA_CfoShortDump_Jaguar 0xBF8
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#define rB_CfoShortDump_Jaguar 0xBFA
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#define rA_CfoLongDump_Jaguar 0xBEC
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#define rB_CfoLongDump_Jaguar 0xBEE
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// RF Register
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//
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#define RF_AC_Jaguar 0x00 //
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#define RF_RF_Top_Jaguar 0x07 //
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#define RF_TXLOK_Jaguar 0x08 //
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#define RF_TXAPK_Jaguar 0x0B
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#define RF_CHNLBW_Jaguar 0x18 // RF channel and BW switch
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#define RF_RCK1_Jaguar 0x1c //
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#define RF_RCK2_Jaguar 0x1d
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#define RF_RCK3_Jaguar 0x1e
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#define RF_ModeTableAddr 0x30
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#define RF_ModeTableData0 0x31
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#define RF_ModeTableData1 0x32
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#define RF_TxLCTank_Jaguar 0x54
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#define RF_APK_Jaguar 0x63
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#define RF_LCK 0xB4
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#define RF_WeLut_Jaguar 0xEF
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#define bRF_CHNLBW_MOD_AG_Jaguar 0x70300
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#define bRF_CHNLBW_BW 0xc00
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//
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// RL6052 Register definition
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//
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#define RF_AC 0x00 //
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#define RF_IPA_A 0x0C //
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#define RF_TXBIAS_A 0x0D
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#define RF_BS_PA_APSET_G9_G11 0x0E
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#define RF_MODE1 0x10 //
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#define RF_MODE2 0x11 //
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#define RF_CHNLBW 0x18 // RF channel and BW switch
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#define RF_RCK_OS 0x30 // RF TX PA control
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#define RF_TXPA_G1 0x31 // RF TX PA control
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#define RF_TXPA_G2 0x32 // RF TX PA control
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#define RF_TXPA_G3 0x33 // RF TX PA control
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#define RF_0x52 0x52
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#define RF_WE_LUT 0xEF
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//
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//Bit Mask
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//
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// 1. Page1(0x100)
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#define bBBResetB 0x100 // Useless now?
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#define bGlobalResetB 0x200
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#define bOFDMTxStart 0x4
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#define bCCKTxStart 0x8
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#define bCRC32Debug 0x100
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#define bPMACLoopback 0x10
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#define bTxLSIG 0xffffff
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#define bOFDMTxRate 0xf
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#define bOFDMTxReserved 0x10
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#define bOFDMTxLength 0x1ffe0
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#define bOFDMTxParity 0x20000
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#define bTxHTSIG1 0xffffff
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#define bTxHTMCSRate 0x7f
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#define bTxHTBW 0x80
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#define bTxHTLength 0xffff00
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#define bTxHTSIG2 0xffffff
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#define bTxHTSmoothing 0x1
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#define bTxHTSounding 0x2
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#define bTxHTReserved 0x4
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#define bTxHTAggreation 0x8
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#define bTxHTSTBC 0x30
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#define bTxHTAdvanceCoding 0x40
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#define bTxHTShortGI 0x80
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#define bTxHTNumberHT_LTF 0x300
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#define bTxHTCRC8 0x3fc00
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#define bCounterReset 0x10000
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#define bNumOfOFDMTx 0xffff
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#define bNumOfCCKTx 0xffff0000
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#define bTxIdleInterval 0xffff
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#define bOFDMService 0xffff0000
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#define bTxMACHeader 0xffffffff
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#define bTxDataInit 0xff
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#define bTxHTMode 0x100
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#define bTxDataType 0x30000
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#define bTxRandomSeed 0xffffffff
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#define bCCKTxPreamble 0x1
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#define bCCKTxSFD 0xffff0000
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#define bCCKTxSIG 0xff
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#define bCCKTxService 0xff00
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#define bCCKLengthExt 0x8000
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#define bCCKTxLength 0xffff0000
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#define bCCKTxCRC16 0xffff
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#define bCCKTxStatus 0x1
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#define bOFDMTxStatus 0x2
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//
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// 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
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// 1. Page1(0x100)
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//
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#define rPMAC_Reset 0x100
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#define rPMAC_TxStart 0x104
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#define rPMAC_TxLegacySIG 0x108
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#define rPMAC_TxHTSIG1 0x10c
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#define rPMAC_TxHTSIG2 0x110
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#define rPMAC_PHYDebug 0x114
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#define rPMAC_TxPacketNum 0x118
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#define rPMAC_TxIdle 0x11c
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#define rPMAC_TxMACHeader0 0x120
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#define rPMAC_TxMACHeader1 0x124
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#define rPMAC_TxMACHeader2 0x128
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#define rPMAC_TxMACHeader3 0x12c
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#define rPMAC_TxMACHeader4 0x130
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#define rPMAC_TxMACHeader5 0x134
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#define rPMAC_TxDataType 0x138
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#define rPMAC_TxRandomSeed 0x13c
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#define rPMAC_CCKPLCPPreamble 0x140
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#define rPMAC_CCKPLCPHeader 0x144
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#define rPMAC_CCKCRC16 0x148
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#define rPMAC_OFDMRxCRC32OK 0x170
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#define rPMAC_OFDMRxCRC32Er 0x174
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|
#define rPMAC_OFDMRxParityEr 0x178
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#define rPMAC_OFDMRxCRC8Er 0x17c
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|
#define rPMAC_CCKCRxRC16Er 0x180
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#define rPMAC_CCKCRxRC32Er 0x184
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#define rPMAC_CCKCRxRC32OK 0x188
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#define rPMAC_TxStatus 0x18c
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//
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// 3. Page8(0x800)
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|
//
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|
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#define rFPGA0_RFMOD 0x800 //RF mode & CCK TxSC // RF BW Setting??
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#define rFPGA0_TxInfo 0x804 // Status report??
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|
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#define rFPGA0_PSDFunction 0x808
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#define rFPGA0_TxGainStage 0x80c // Set TX PWR init gain?
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#define rFPGA0_XA_HSSIParameter1 0x820 // RF 3 wire register
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#define rFPGA0_XA_HSSIParameter2 0x824
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#define rFPGA0_XB_HSSIParameter1 0x828
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#define rFPGA0_XB_HSSIParameter2 0x82c
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|
#define rFPGA0_XAB_SwitchControl 0x858 // RF Channel switch
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#define rFPGA0_XCD_SwitchControl 0x85c
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|
#define rFPGA0_XAB_RFParameter 0x878 // RF Parameter
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|
|
#define rFPGA0_XCD_RFParameter 0x87c
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|
|
#define rFPGA0_AnalogParameter1 0x880 // Crystal cap setting RF-R/W protection for parameter4??
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|
#define rFPGA0_AnalogParameter2 0x884
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|
|
#define rFPGA0_AnalogParameter3 0x888
|
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|
|
#define rFPGA0_AdDaClockEn 0x888 // enable ad/da clock1 for dual-phy
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|
|
#define rFPGA0_AnalogParameter4 0x88c
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|
|
#define rFPGA0_XB_LSSIReadBack 0x8a4
|
2017-05-11 18:35:20 +00:00
|
|
|
#define rFPGA0_XCD_RFPara 0x8b4
|
|
|
|
|
|
2015-08-18 19:03:09 +00:00
|
|
|
//
|
|
|
|
|
// 4. Page9(0x900)
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|
|
|
|
//
|
|
|
|
|
#define rFPGA1_RFMOD 0x900 //RF mode & OFDM TxSC // RF BW Setting??
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|
#define rFPGA1_TxBlock 0x904 // Useless now
|
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|
|
#define rFPGA1_DebugSelect 0x908 // Useless now
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|
|
#define rFPGA1_TxInfo 0x90c // Useless now // Status report??
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|
|
//
|
|
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|
|
// PageA(0xA00)
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|
|
//
|
|
|
|
|
#define rCCK0_System 0xa00
|
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|
|
#define rCCK0_AFESetting 0xa04 // Disable init gain now // Select RX path by RSSI
|
2017-05-11 18:35:20 +00:00
|
|
|
#define rCCK0_DSPParameter2 0xa1c //SQ threshold
|
2015-08-18 19:03:09 +00:00
|
|
|
#define rCCK0_TxFilter1 0xa20
|
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|
|
#define rCCK0_TxFilter2 0xa24
|
|
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|
|
#define rCCK0_DebugPort 0xa28 //debug port and Tx filter3
|
2017-05-11 18:35:20 +00:00
|
|
|
#define rCCK0_FalseAlarmReport 0xa2c //0xa2d useless now 0xa30-a4f channel report
|
2015-08-18 19:03:09 +00:00
|
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|
|
//
|
|
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|
|
// PageB(0xB00)
|
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|
|
|
//
|
|
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|
|
#define rPdp_AntA 0xb00
|
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|
|
#define rPdp_AntA_4 0xb04
|
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|
|
#define rConfig_Pmpd_AntA 0xb28
|
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|
|
#define rConfig_AntA 0xb68
|
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|
|
#define rConfig_AntB 0xb6c
|
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|
|
#define rPdp_AntB 0xb70
|
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|
|
#define rPdp_AntB_4 0xb74
|
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|
|
#define rConfig_Pmpd_AntB 0xb98
|
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|
|
|
#define rAPK 0xbd8
|
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|
|
|
|
|
|
|
|
//
|
|
|
|
|
// 6. PageC(0xC00)
|
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|
|
|
//
|
|
|
|
|
#define rOFDM0_LSTF 0xc00
|
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|
|
#define rOFDM0_TRxPathEnable 0xc04
|
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|
|
#define rOFDM0_TRMuxPar 0xc08
|
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|
|
#define rOFDM0_TRSWIsolation 0xc0c
|
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|
|
#define rOFDM0_XARxAFE 0xc10 //RxIQ DC offset, Rx digital filter, DC notch filter
|
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|
|
#define rOFDM0_XARxIQImbalance 0xc14 //RxIQ imblance matrix
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|
|
#define rOFDM0_XBRxAFE 0xc18
|
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|
|
#define rOFDM0_XBRxIQImbalance 0xc1c
|
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|
|
#define rOFDM0_XCRxAFE 0xc20
|
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|
|
#define rOFDM0_XCRxIQImbalance 0xc24
|
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|
|
#define rOFDM0_XDRxAFE 0xc28
|
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|
|
#define rOFDM0_XDRxIQImbalance 0xc2c
|
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|
|
#define rOFDM0_RxDetector1 0xc30 //PD,BW & SBD // DM tune init gain
|
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|
|
#define rOFDM0_RxDetector2 0xc34 //SBD & Fame Sync.
|
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|
|
#define rOFDM0_RxDetector3 0xc38 //Frame Sync.
|
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|
|
#define rOFDM0_RxDetector4 0xc3c //PD, SBD, Frame Sync & Short-GI
|
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|
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|
|
|
#define rOFDM0_RxDSP 0xc40 //Rx Sync Path
|
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|
|
#define rOFDM0_CFOandDAGC 0xc44 //CFO & DAGC
|
|
|
|
|
#define rOFDM0_CCADropThreshold 0xc48 //CCA Drop threshold
|
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|
|
#define rOFDM0_ECCAThreshold 0xc4c // energy CCA
|
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|
|
#define rOFDM0_XAAGCCore1 0xc50 // DIG
|
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|
|
#define rOFDM0_XAAGCCore2 0xc54
|
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|
|
#define rOFDM0_XBAGCCore1 0xc58
|
|
|
|
|
#define rOFDM0_XBAGCCore2 0xc5c
|
|
|
|
|
#define rOFDM0_XCAGCCore1 0xc60
|
|
|
|
|
#define rOFDM0_XCAGCCore2 0xc64
|
|
|
|
|
#define rOFDM0_XDAGCCore1 0xc68
|
|
|
|
|
#define rOFDM0_XDAGCCore2 0xc6c
|
|
|
|
|
|
|
|
|
|
#define rOFDM0_AGCParameter1 0xc70
|
|
|
|
|
#define rOFDM0_AGCParameter2 0xc74
|
|
|
|
|
#define rOFDM0_AGCRSSITable 0xc78
|
|
|
|
|
#define rOFDM0_HTSTFAGC 0xc7c
|
|
|
|
|
|
|
|
|
|
#define rOFDM0_XATxIQImbalance 0xc80 // TX PWR TRACK and DIG
|
|
|
|
|
#define rOFDM0_XATxAFE 0xc84
|
|
|
|
|
#define rOFDM0_XBTxIQImbalance 0xc88
|
|
|
|
|
#define rOFDM0_XBTxAFE 0xc8c
|
|
|
|
|
#define rOFDM0_XCTxIQImbalance 0xc90
|
|
|
|
|
#define rOFDM0_XCTxAFE 0xc94
|
|
|
|
|
#define rOFDM0_XDTxIQImbalance 0xc98
|
|
|
|
|
#define rOFDM0_XDTxAFE 0xc9c
|
|
|
|
|
|
|
|
|
|
#define rOFDM0_RxIQExtAnta 0xca0
|
|
|
|
|
#define rOFDM0_TxCoeff1 0xca4
|
|
|
|
|
#define rOFDM0_TxCoeff2 0xca8
|
|
|
|
|
#define rOFDM0_TxCoeff3 0xcac
|
|
|
|
|
#define rOFDM0_TxCoeff4 0xcb0
|
|
|
|
|
#define rOFDM0_TxCoeff5 0xcb4
|
|
|
|
|
#define rOFDM0_TxCoeff6 0xcb8
|
|
|
|
|
#define rOFDM0_RxHPParameter 0xce0
|
|
|
|
|
#define rOFDM0_TxPseudoNoiseWgt 0xce4
|
|
|
|
|
#define rOFDM0_FrameSync 0xcf0
|
|
|
|
|
#define rOFDM0_DFSReport 0xcf4
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
|
// 7. PageD(0xD00)
|
|
|
|
|
//
|
|
|
|
|
#define rOFDM1_LSTF 0xd00
|
|
|
|
|
#define rOFDM1_TRxPathEnable 0xd04
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
|
// 8. PageE(0xE00)
|
|
|
|
|
//
|
|
|
|
|
#define rTxAGC_A_Rate18_06 0xe00
|
|
|
|
|
#define rTxAGC_A_Rate54_24 0xe04
|
|
|
|
|
#define rTxAGC_A_CCK1_Mcs32 0xe08
|
|
|
|
|
#define rTxAGC_A_Mcs03_Mcs00 0xe10
|
|
|
|
|
#define rTxAGC_A_Mcs07_Mcs04 0xe14
|
|
|
|
|
#define rTxAGC_A_Mcs11_Mcs08 0xe18
|
|
|
|
|
#define rTxAGC_A_Mcs15_Mcs12 0xe1c
|
|
|
|
|
|
|
|
|
|
#define rTxAGC_B_Rate18_06 0x830
|
|
|
|
|
#define rTxAGC_B_Rate54_24 0x834
|
|
|
|
|
#define rTxAGC_B_CCK1_55_Mcs32 0x838
|
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#define rTxAGC_B_Mcs03_Mcs00 0x83c
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#define rTxAGC_B_Mcs07_Mcs04 0x848
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#define rTxAGC_B_Mcs11_Mcs08 0x84c
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#define rTxAGC_B_Mcs15_Mcs12 0x868
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#define rTxAGC_B_CCK11_A_CCK2_11 0x86c
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#define rFPGA0_IQK 0xe28
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#define rTx_IQK_Tone_A 0xe30
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#define rRx_IQK_Tone_A 0xe34
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#define rTx_IQK_PI_A 0xe38
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#define rRx_IQK_PI_A 0xe3c
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#define rTx_IQK 0xe40
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#define rRx_IQK 0xe44
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#define rIQK_AGC_Pts 0xe48
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#define rIQK_AGC_Rsp 0xe4c
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#define rTx_IQK_Tone_B 0xe50
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#define rRx_IQK_Tone_B 0xe54
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#define rTx_IQK_PI_B 0xe58
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#define rRx_IQK_PI_B 0xe5c
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#define rIQK_AGC_Cont 0xe60
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#define rBlue_Tooth 0xe6c
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#define rRx_Wait_CCA 0xe70
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#define rTx_CCK_RFON 0xe74
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#define rTx_CCK_BBON 0xe78
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#define rTx_OFDM_RFON 0xe7c
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#define rTx_OFDM_BBON 0xe80
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#define rTx_To_Rx 0xe84
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#define rTx_To_Tx 0xe88
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#define rRx_CCK 0xe8c
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#define rTx_Power_Before_IQK_A 0xe94
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#define rTx_Power_After_IQK_A 0xe9c
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#define rRx_Power_Before_IQK_A 0xea0
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#define rRx_Power_Before_IQK_A_2 0xea4
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#define rRx_Power_After_IQK_A 0xea8
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#define rRx_Power_After_IQK_A_2 0xeac
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#define rTx_Power_Before_IQK_B 0xeb4
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#define rTx_Power_After_IQK_B 0xebc
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#define rRx_Power_Before_IQK_B 0xec0
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#define rRx_Power_Before_IQK_B_2 0xec4
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#define rRx_Power_After_IQK_B 0xec8
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#define rRx_Power_After_IQK_B_2 0xecc
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#define rRx_OFDM 0xed0
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#define rRx_Wait_RIFS 0xed4
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#define rRx_TO_Rx 0xed8
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#define rStandby 0xedc
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#define rSleep 0xee0
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#define rPMPD_ANAEN 0xeec
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// 2. Page8(0x800)
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#define bRFMOD 0x1 // Reg 0x800 rFPGA0_RFMOD
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#define bJapanMode 0x2
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#define bCCKTxSC 0x30
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#define bCCKEn 0x1000000
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#define bOFDMEn 0x2000000
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#define bXBTxAGC 0xf00 // Reg 80c rFPGA0_TxGainStage
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#define bXCTxAGC 0xf000
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#define bXDTxAGC 0xf0000
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// 4. PageA(0xA00)
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#define bCCKBBMode 0x3 // Useless
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#define bCCKTxPowerSaving 0x80
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#define bCCKRxPowerSaving 0x40
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#define bCCKSideBand 0x10 // Reg 0xa00 rCCK0_System 20/40 switch
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#define bCCKScramble 0x8 // Useless
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#define bCCKAntDiversity 0x8000
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#define bCCKCarrierRecovery 0x4000
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#define bCCKTxRate 0x3000
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#define bCCKDCCancel 0x0800
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#define bCCKISICancel 0x0400
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#define bCCKMatchFilter 0x0200
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#define bCCKEqualizer 0x0100
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#define bCCKPreambleDetect 0x800000
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#define bCCKFastFalseCCA 0x400000
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#define bCCKChEstStart 0x300000
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#define bCCKCCACount 0x080000
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#define bCCKcs_lim 0x070000
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#define bCCKBistMode 0x80000000
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#define bCCKCCAMask 0x40000000
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#define bCCKTxDACPhase 0x4
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#define bCCKRxADCPhase 0x20000000 //r_rx_clk
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#define bCCKr_cp_mode0 0x0100
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#define bCCKTxDCOffset 0xf0
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#define bCCKRxDCOffset 0xf
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#define bCCKCCAMode 0xc000
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#define bCCKFalseCS_lim 0x3f00
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#define bCCKCS_ratio 0xc00000
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#define bCCKCorgBit_sel 0x300000
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#define bCCKPD_lim 0x0f0000
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#define bCCKNewCCA 0x80000000
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#define bCCKRxHPofIG 0x8000
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#define bCCKRxIG 0x7f00
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#define bCCKLNAPolarity 0x800000
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#define bCCKRx1stGain 0x7f0000
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#define bCCKRFExtend 0x20000000 //CCK Rx Iinital gain polarity
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#define bCCKRxAGCSatLevel 0x1f000000
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#define bCCKRxAGCSatCount 0xe0
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#define bCCKRxRFSettle 0x1f //AGCsamp_dly
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#define bCCKFixedRxAGC 0x8000
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|
|
//#define bCCKRxAGCFormat 0x4000 //remove to HSSI register 0x824
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|
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#define bCCKAntennaPolarity 0x2000
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#define bCCKTxFilterType 0x0c00
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#define bCCKRxAGCReportType 0x0300
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#define bCCKRxDAGCEn 0x80000000
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|
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#define bCCKRxDAGCPeriod 0x20000000
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|
#define bCCKRxDAGCSatLevel 0x1f000000
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|
#define bCCKTimingRecovery 0x800000
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|
|
#define bCCKTxC0 0x3f0000
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|
|
#define bCCKTxC1 0x3f000000
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|
#define bCCKTxC2 0x3f
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|
#define bCCKTxC3 0x3f00
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|
#define bCCKTxC4 0x3f0000
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|
|
#define bCCKTxC5 0x3f000000
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|
|
#define bCCKTxC6 0x3f
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|
|
#define bCCKTxC7 0x3f00
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|
|
#define bCCKDebugPort 0xff0000
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|
|
#define bCCKDACDebug 0x0f000000
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|
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|
|
#define bCCKFalseAlarmEnable 0x8000
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|
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|
|
#define bCCKFalseAlarmRead 0x4000
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|
|
|
|
#define bCCKTRSSI 0x7f
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|
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|
|
#define bCCKRxAGCReport 0xfe
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|
|
|
|
#define bCCKRxReport_AntSel 0x80000000
|
|
|
|
|
#define bCCKRxReport_MFOff 0x40000000
|
|
|
|
|
#define bCCKRxRxReport_SQLoss 0x20000000
|
|
|
|
|
#define bCCKRxReport_Pktloss 0x10000000
|
|
|
|
|
#define bCCKRxReport_Lockedbit 0x08000000
|
|
|
|
|
#define bCCKRxReport_RateError 0x04000000
|
|
|
|
|
#define bCCKRxReport_RxRate 0x03000000
|
|
|
|
|
#define bCCKRxFACounterLower 0xff
|
|
|
|
|
#define bCCKRxFACounterUpper 0xff000000
|
|
|
|
|
#define bCCKRxHPAGCStart 0xe000
|
|
|
|
|
#define bCCKRxHPAGCFinal 0x1c00
|
|
|
|
|
#define bCCKRxFalseAlarmEnable 0x8000
|
|
|
|
|
#define bCCKFACounterFreeze 0x4000
|
|
|
|
|
#define bCCKTxPathSel 0x10000000
|
|
|
|
|
#define bCCKDefaultRxPath 0xc000000
|
|
|
|
|
#define bCCKOptionRxPath 0x3000000
|
|
|
|
|
|
|
|
|
|
// 6. PageE(0xE00)
|
|
|
|
|
#define bSTBCEn 0x4 // Useless
|
|
|
|
|
#define bAntennaMapping 0x10
|
|
|
|
|
#define bNss 0x20
|
|
|
|
|
#define bCFOAntSumD 0x200
|
|
|
|
|
#define bPHYCounterReset 0x8000000
|
|
|
|
|
#define bCFOReportGet 0x4000000
|
|
|
|
|
#define bOFDMContinueTx 0x10000000
|
|
|
|
|
#define bOFDMSingleCarrier 0x20000000
|
|
|
|
|
#define bOFDMSingleTone 0x40000000
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
|
// Other Definition
|
|
|
|
|
//
|
|
|
|
|
|
|
|
|
|
#define bEnable 0x1 // Useless
|
|
|
|
|
#define bDisable 0x0
|
|
|
|
|
|
|
|
|
|
//byte endable for srwrite
|
|
|
|
|
#define bByte0 0x1 // Useless
|
|
|
|
|
#define bByte1 0x2
|
|
|
|
|
#define bByte2 0x4
|
|
|
|
|
#define bByte3 0x8
|
|
|
|
|
#define bWord0 0x3
|
|
|
|
|
#define bWord1 0xc
|
|
|
|
|
#define bDWord 0xf
|
|
|
|
|
|
|
|
|
|
//for PutRegsetting & GetRegSetting BitMask
|
|
|
|
|
#define bMaskByte0 0xff // Reg 0xc50 rOFDM0_XAAGCCore~0xC6f
|
|
|
|
|
#define bMaskByte1 0xff00
|
|
|
|
|
#define bMaskByte2 0xff0000
|
|
|
|
|
#define bMaskByte3 0xff000000
|
|
|
|
|
#define bMaskHWord 0xffff0000
|
|
|
|
|
#define bMaskLWord 0x0000ffff
|
|
|
|
|
#define bMaskDWord 0xffffffff
|
2017-05-11 18:35:20 +00:00
|
|
|
#define bMaskH3Bytes 0xffffff00
|
2015-08-18 19:03:09 +00:00
|
|
|
#define bMask12Bits 0xfff
|
|
|
|
|
#define bMaskH4Bits 0xf0000000
|
|
|
|
|
#define bMaskOFDM_D 0xffc00000
|
|
|
|
|
#define bMaskCCK 0x3f3f3f3f
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/*--------------------------Define Parameters-------------------------------*/
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
#endif
|
|
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