2015-08-18 19:03:09 +00:00
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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*
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******************************************************************************/
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#ifndef __GSPI_OPS_H__
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#define __GSPI_OPS_H__
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/* follwing defination is based on
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* GSPI spec of RTL8723, we temp
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* suppose that it will be the same
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* for diff chips of GSPI, if not
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* we should move it to HAL folder */
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#define SPI_LOCAL_DOMAIN 0x0
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#define WLAN_IOREG_DOMAIN 0x8
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#define FW_FIFO_DOMAIN 0x4
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#define TX_HIQ_DOMAIN 0xc
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#define TX_MIQ_DOMAIN 0xd
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#define TX_LOQ_DOMAIN 0xe
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#define RX_RXFIFO_DOMAIN 0x1f
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//IO Bus domain address mapping
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#define DEFUALT_OFFSET 0x0
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#define SPI_LOCAL_OFFSET 0x10250000
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#define WLAN_IOREG_OFFSET 0x10260000
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#define FW_FIFO_OFFSET 0x10270000
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#define TX_HIQ_OFFSET 0x10310000
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#define TX_MIQ_OFFSET 0x1032000
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#define TX_LOQ_OFFSET 0x10330000
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#define RX_RXOFF_OFFSET 0x10340000
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//SPI Local registers
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#define SPI_REG_TX_CTRL 0x0000 // SPI Tx Control
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#define SPI_REG_STATUS_RECOVERY 0x0004
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#define SPI_REG_INT_TIMEOUT 0x0006
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#define SPI_REG_HIMR 0x0014 // SPI Host Interrupt Mask
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#define SPI_REG_HISR 0x0018 // SPI Host Interrupt Service Routine
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#define SPI_REG_RX0_REQ_LEN 0x001C // RXDMA Request Length
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#define SPI_REG_FREE_TXPG 0x0020 // Free Tx Buffer Page
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#define SPI_REG_HCPWM1 0x0024 // HCI Current Power Mode 1
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#define SPI_REG_HCPWM2 0x0026 // HCI Current Power Mode 2
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#define SPI_REG_HTSFR_INFO 0x0030 // HTSF Informaion
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#define SPI_REG_HRPWM1 0x0080 // HCI Request Power Mode 1
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#define SPI_REG_HRPWM2 0x0082 // HCI Request Power Mode 2
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#define SPI_REG_HPS_CLKR 0x0084 // HCI Power Save Clock
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#define SPI_REG_HSUS_CTRL 0x0086 // SPI HCI Suspend Control
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#define SPI_REG_HIMR_ON 0x0090 //SPI Host Extension Interrupt Mask Always
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#define SPI_REG_HISR_ON 0x0091 //SPI Host Extension Interrupt Status Always
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#define SPI_REG_CFG 0x00F0 //SPI Configuration Register
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#define SPI_TX_CTRL (SPI_REG_TX_CTRL |SPI_LOCAL_OFFSET)
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#define SPI_STATUS_RECOVERY (SPI_REG_STATUS_RECOVERY |SPI_LOCAL_OFFSET)
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#define SPI_INT_TIMEOUT (SPI_REG_INT_TIMEOUT |SPI_LOCAL_OFFSET)
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#define SPI_HIMR (SPI_REG_HIMR |SPI_LOCAL_OFFSET)
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#define SPI_HISR (SPI_REG_HISR |SPI_LOCAL_OFFSET)
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#define SPI_RX0_REQ_LEN_1_BYTE (SPI_REG_RX0_REQ_LEN |SPI_LOCAL_OFFSET)
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#define SPI_FREE_TXPG (SPI_REG_FREE_TXPG |SPI_LOCAL_OFFSET)
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#define SPI_HIMR_DISABLED 0
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//SPI HIMR MASK diff with SDIO
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#define SPI_HISR_RX_REQUEST BIT(0)
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#define SPI_HISR_AVAL BIT(1)
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#define SPI_HISR_TXERR BIT(2)
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#define SPI_HISR_RXERR BIT(3)
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#define SPI_HISR_TXFOVW BIT(4)
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#define SPI_HISR_RXFOVW BIT(5)
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#define SPI_HISR_TXBCNOK BIT(6)
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#define SPI_HISR_TXBCNERR BIT(7)
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#define SPI_HISR_BCNERLY_INT BIT(16)
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#define SPI_HISR_ATIMEND BIT(17)
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#define SPI_HISR_ATIMEND_E BIT(18)
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#define SPI_HISR_CTWEND BIT(19)
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#define SPI_HISR_C2HCMD BIT(20)
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#define SPI_HISR_CPWM1 BIT(21)
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#define SPI_HISR_CPWM2 BIT(22)
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#define SPI_HISR_HSISR_IND BIT(23)
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#define SPI_HISR_GTINT3_IND BIT(24)
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#define SPI_HISR_GTINT4_IND BIT(25)
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#define SPI_HISR_PSTIMEOUT BIT(26)
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#define SPI_HISR_OCPINT BIT(27)
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#define SPI_HISR_TSF_BIT32_TOGGLE BIT(29)
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#define MASK_SPI_HISR_CLEAR (SPI_HISR_TXERR |\
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SPI_HISR_RXERR |\
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SPI_HISR_TXFOVW |\
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SPI_HISR_RXFOVW |\
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SPI_HISR_TXBCNOK |\
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SPI_HISR_TXBCNERR |\
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SPI_HISR_C2HCMD |\
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SPI_HISR_CPWM1 |\
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SPI_HISR_CPWM2 |\
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SPI_HISR_HSISR_IND |\
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SPI_HISR_GTINT3_IND |\
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SPI_HISR_GTINT4_IND |\
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SPI_HISR_PSTIMEOUT |\
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SPI_HISR_OCPINT)
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#define REG_LEN_FORMAT(pcmd, x) SET_BITS_TO_LE_4BYTE(pcmd, 0, 8, x)//(x<<(unsigned int)24)
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#define REG_ADDR_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 8, 16, x)//(x<<(unsigned int)16)
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#define REG_DOMAIN_ID_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 24, 5, x)//(x<<(unsigned int)0)
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#define REG_FUN_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 29, 2, x)//(x<<(unsigned int)5)
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#define REG_RW_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 31, 1, x)//(x<<(unsigned int)7)
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#define FIFO_LEN_FORMAT(pcmd, x) SET_BITS_TO_LE_4BYTE(pcmd, 0, 16, x)//(x<<(unsigned int)24)
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//#define FIFO_ADDR_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 8, 16, x)//(x<<(unsigned int)16)
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#define FIFO_DOMAIN_ID_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 24, 5, x)//(x<<(unsigned int)0)
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#define FIFO_FUN_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 29, 2, x)//(x<<(unsigned int)5)
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#define FIFO_RW_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 31, 1, x)//(x<<(unsigned int)7)
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//get status dword0
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#define GET_STATUS_PUB_PAGE_NUM(status) LE_BITS_TO_4BYTE(status, 24, 8)
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#define GET_STATUS_HI_PAGE_NUM(status) LE_BITS_TO_4BYTE(status, 18, 6)
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#define GET_STATUS_MID_PAGE_NUM(status) LE_BITS_TO_4BYTE(status, 12, 6)
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#define GET_STATUS_LOW_PAGE_NUM(status) LE_BITS_TO_4BYTE(status, 6, 6)
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#define GET_STATUS_HISR_HI6BIT(status) LE_BITS_TO_4BYTE(status, 0, 6)
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//get status dword1
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#define GET_STATUS_HISR_MID8BIT(status) LE_BITS_TO_4BYTE(status + 4, 24, 8)
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#define GET_STATUS_HISR_LOW8BIT(status) LE_BITS_TO_4BYTE(status + 4, 16, 8)
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#define GET_STATUS_ERROR(status) LE_BITS_TO_4BYTE(status + 4, 17, 1)
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#define GET_STATUS_INT(status) LE_BITS_TO_4BYTE(status + 4, 16, 1)
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#define GET_STATUS_RX_LENGTH(status) LE_BITS_TO_4BYTE(status + 4, 0, 16)
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#define RXDESC_SIZE 24
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struct spi_more_data {
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unsigned long more_data;
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unsigned long len;
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};
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#ifdef CONFIG_RTL8188E
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void rtl8188es_set_hal_ops(PADAPTER padapter);
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#define set_hal_ops rtl8188es_set_hal_ops
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#endif
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extern void spi_set_chip_endian(PADAPTER padapter);
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2017-05-11 18:35:20 +00:00
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extern unsigned int spi_write8_endian(ADAPTER *Adapter, unsigned int addr, unsigned int buf, u32 big);
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2015-08-18 19:03:09 +00:00
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extern void spi_set_intf_ops(_adapter *padapter,struct _io_ops *pops);
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extern void spi_set_chip_endian(PADAPTER padapter);
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extern void InitInterrupt8723ASdio(PADAPTER padapter);
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extern void InitSysInterrupt8723ASdio(PADAPTER padapter);
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extern void EnableInterrupt8723ASdio(PADAPTER padapter);
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extern void DisableInterrupt8723ASdio(PADAPTER padapter);
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extern void spi_int_hdl(PADAPTER padapter);
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extern u8 HalQueryTxBufferStatus8723ASdio(PADAPTER padapter);
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#ifdef CONFIG_RTL8723B
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extern void InitInterrupt8723BSdio(PADAPTER padapter);
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extern void InitSysInterrupt8723BSdio(PADAPTER padapter);
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extern void EnableInterrupt8723BSdio(PADAPTER padapter);
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extern void DisableInterrupt8723BSdio(PADAPTER padapter);
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extern u8 HalQueryTxBufferStatus8723BSdio(PADAPTER padapter);
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#endif
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2017-05-11 18:35:20 +00:00
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#ifdef CONFIG_RTL8188E
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extern void InitInterrupt8188EGspi(PADAPTER padapter);
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extern void EnableInterrupt8188EGspi(PADAPTER padapter);
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extern void DisableInterrupt8188EGspi(PADAPTER padapter);
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extern void UpdateInterruptMask8188EGspi(PADAPTER padapter, u32 AddMSR, u32 RemoveMSR);
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extern u8 HalQueryTxBufferStatus8189EGspi(PADAPTER padapter);
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extern u8 HalQueryTxOQTBufferStatus8189EGspi(PADAPTER padapter);
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extern void ClearInterrupt8188EGspi(PADAPTER padapter);
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extern u8 CheckIPSStatus(PADAPTER padapter);
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#endif // CONFIG_RTL8188E
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#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
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extern u8 RecvOnePkt(PADAPTER padapter, u32 size);
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#endif // CONFIG_WOWLAN
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2015-08-18 19:03:09 +00:00
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#endif //__GSPI_OPS_H__
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