mirror of
https://github.com/Mange/rtl8192eu-linux-driver
synced 2024-11-01 19:25:31 +00:00
426 lines
12 KiB
C
426 lines
12 KiB
C
/******************************************************************************
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*
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* Copyright(c) 2007 - 2017 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#include "mp_precomp.h"
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#include "phydm_precomp.h"
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#if (defined(CONFIG_BB_TXBF_API))
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#if (RTL8822B_SUPPORT == 1 || RTL8192F_SUPPORT == 1 ||\
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RTL8822C_SUPPORT == 1 || RTL8198F_SUPPORT == 1 || RTL8814B_SUPPORT == 1)
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/*@Add by YuChen for 8822B MU-MIMO API*/
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/*this function is only used for BFer*/
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u8 phydm_get_ndpa_rate(void *dm_void)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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u8 ndpa_rate = ODM_RATE6M;
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if (dm->rssi_min >= 30) /*@link RSSI > 30%*/
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ndpa_rate = ODM_RATE24M;
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else if (dm->rssi_min <= 25)
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ndpa_rate = ODM_RATE6M;
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PHYDM_DBG(dm, DBG_TXBF, "[%s] ndpa_rate = 0x%x\n", __func__, ndpa_rate);
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return ndpa_rate;
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}
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/*this function is only used for BFer*/
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u8 phydm_get_beamforming_sounding_info(void *dm_void, u16 *throughput,
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u8 total_bfee_num, u8 *tx_rate)
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{
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u8 idx = 0;
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u8 snddecision = 0xff;
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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for (idx = 0; idx < total_bfee_num; idx++) {
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if (dm->support_ic_type & (ODM_RTL8814A)) {
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if ((tx_rate[idx] >= ODM_RATEVHTSS3MCS7 &&
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tx_rate[idx] <= ODM_RATEVHTSS3MCS9))
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snddecision = snddecision & ~(1 << idx);
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} else if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8822C |
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ODM_RTL8812 | ODM_RTL8192F)) {
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if ((tx_rate[idx] >= ODM_RATEVHTSS2MCS7 &&
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tx_rate[idx] <= ODM_RATEVHTSS2MCS9))
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snddecision = snddecision & ~(1 << idx);
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} else if (dm->support_ic_type & (ODM_RTL8814B)) {
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if ((tx_rate[idx] >= ODM_RATEVHTSS4MCS7 &&
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tx_rate[idx] <= ODM_RATEVHTSS4MCS9))
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snddecision = snddecision & ~(1 << idx);
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}
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}
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for (idx = 0; idx < total_bfee_num; idx++) {
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if (throughput[idx] <= 10)
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snddecision = snddecision & ~(1 << idx);
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}
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PHYDM_DBG(dm, DBG_TXBF, "[%s] soundingdecision = 0x%x\n", __func__,
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snddecision);
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return snddecision;
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}
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/*this function is only used for BFer*/
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u8 phydm_get_mu_bfee_snding_decision(void *dm_void, u16 throughput)
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{
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u8 snding_score = 0;
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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/*throughput unit is Mbps*/
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if (throughput >= 500)
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snding_score = 100;
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else if (throughput >= 450)
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snding_score = 90;
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else if (throughput >= 400)
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snding_score = 80;
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else if (throughput >= 350)
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snding_score = 70;
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else if (throughput >= 300)
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snding_score = 60;
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else if (throughput >= 250)
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snding_score = 50;
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else if (throughput >= 200)
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snding_score = 40;
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else if (throughput >= 150)
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snding_score = 30;
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else if (throughput >= 100)
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snding_score = 20;
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else if (throughput >= 50)
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snding_score = 10;
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else
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snding_score = 0;
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PHYDM_DBG(dm, DBG_TXBF, "[%s] snding_score = 0x%x\n", __func__,
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snding_score);
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return snding_score;
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}
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#endif
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#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
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u8 beamforming_get_htndp_tx_rate(void *dm_void, u8 bfer_str_num)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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u8 nr_index = 0;
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u8 ndp_tx_rate;
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/*@Find nr*/
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#if (RTL8814A_SUPPORT == 1)
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if (dm->support_ic_type & ODM_RTL8814A)
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nr_index = tx_bf_nr(hal_txbf_8814a_get_ntx(dm), bfer_str_num);
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else
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#endif
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nr_index = tx_bf_nr(1, bfer_str_num);
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switch (nr_index) {
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case 1:
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ndp_tx_rate = ODM_MGN_MCS8;
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break;
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case 2:
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ndp_tx_rate = ODM_MGN_MCS16;
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break;
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case 3:
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ndp_tx_rate = ODM_MGN_MCS24;
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break;
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default:
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ndp_tx_rate = ODM_MGN_MCS8;
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break;
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}
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return ndp_tx_rate;
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}
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u8 beamforming_get_vht_ndp_tx_rate(void *dm_void, u8 bfer_str_num)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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u8 nr_index = 0;
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u8 ndp_tx_rate;
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/*@Find nr*/
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#if (RTL8814A_SUPPORT == 1)
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if (dm->support_ic_type & ODM_RTL8814A)
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nr_index = tx_bf_nr(hal_txbf_8814a_get_ntx(dm), bfer_str_num);
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else
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#endif
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nr_index = tx_bf_nr(1, bfer_str_num);
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switch (nr_index) {
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case 1:
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ndp_tx_rate = ODM_MGN_VHT2SS_MCS0;
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break;
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case 2:
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ndp_tx_rate = ODM_MGN_VHT3SS_MCS0;
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break;
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case 3:
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ndp_tx_rate = ODM_MGN_VHT4SS_MCS0;
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break;
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default:
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ndp_tx_rate = ODM_MGN_VHT2SS_MCS0;
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break;
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}
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return ndp_tx_rate;
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}
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#endif
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#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
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/*this function is only used for BFer*/
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void phydm_txbf_rfmode(void *dm_void, u8 su_bfee_cnt, u8 mu_bfee_cnt)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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u8 i;
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if (dm->rf_type == RF_1T1R)
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return;
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#if (RTL8822C_SUPPORT == 1)
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if (dm->support_ic_type == ODM_RTL8822C) {
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if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {
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for (i = RF_PATH_A; i <= RF_PATH_B; i++) {
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/*RF mode table write enable*/
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odm_set_rf_reg(dm, (enum rf_path)i, RF_0xef,
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BIT(19), 0x1);
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/*Select RX mode*/
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odm_set_rf_reg(dm, (enum rf_path)i, RF_0x33,
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0xF, 3);
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/*Set Table data*/
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odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3e,
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0x3, 0x2);
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/*Set Table data*/
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odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3f,
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0xfffff, 0x61AFF);
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/*RF mode table write disable*/
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odm_set_rf_reg(dm, (enum rf_path)i, RF_0xef,
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BIT(19), 0x0);
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}
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}
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/*@if Nsts > Nc, don't apply V matrix*/
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odm_set_bb_reg(dm, R_0x1e24, BIT(11), 1);
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if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {
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/*@enable BB TxBF ant mapping register*/
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odm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x2);
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odm_set_bb_reg(dm, R_0x1e24, BIT(30), 1);
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/* logic mapping */
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/* TX BF logic map and TX path en for Nsts = 1~2 */
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odm_set_bb_reg(dm, R_0x820, 0xffff0000, 0x33);
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odm_set_bb_reg(dm, R_0x1e30, 0xffff, 0x404);
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} else {
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/*@Disable BB TxBF ant mapping register*/
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odm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x0);
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odm_set_bb_reg(dm, R_0x1e24, BIT(31), 0);
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/*@1SS~2ss A, AB*/
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odm_set_bb_reg(dm, R_0x820, 0xff, 0x31);
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odm_set_bb_reg(dm, R_0x1e2c, 0xffff, 0x400);
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}
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}
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#endif
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#if (RTL8814B_SUPPORT)
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if (dm->support_ic_type == ODM_RTL8814B) {
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if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {
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for (i = RF_PATH_A; i <= RF_PATH_D; i++) {
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/*RF mode table write enable*/
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odm_set_rf_reg(dm, (enum rf_path)i, RF_0xef,
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BIT(19), 0x1);
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/*Select RX mode*/
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odm_set_rf_reg(dm, (enum rf_path)i, RF_0x33,
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0xF, 2);
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/*Set Table data*/
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odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3e,
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0xfffff, 0x3fc);
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/*Set Table data*/
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odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3f,
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0xfffff, 0x280f7);
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/*Select RX mode*/
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odm_set_rf_reg(dm, (enum rf_path)i, RF_0x33,
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0xF, 3);
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/*Set Table data*/
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odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3e,
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0xfffff, 0x365);
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/*Set Table data*/
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odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3f,
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0xfffff, 0xafcf7);
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/*RF mode table write disable*/
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odm_set_rf_reg(dm, (enum rf_path)i, RF_0xef,
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BIT(19), 0x0);
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}
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}
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/*@if Nsts > Nc, don't apply V matrix*/
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odm_set_bb_reg(dm, R_0x1e24, BIT(11), 1);
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if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {
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/*@enable BB TxBF ant mapping register*/
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odm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x2);
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odm_set_bb_reg(dm, R_0x1e24, BIT(30), 1);
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/* logic mapping */
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/* TX BF logic map and TX path en for Nsts = 1~4 */
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odm_set_bb_reg(dm, R_0x820, 0xffff0000, 0xff55);
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/*verification path-AC*/
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odm_set_bb_reg(dm, R_0x1e30, 0xffffffff, 0xe4e41010);
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} else {
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/*@Disable BB TxBF ant mapping register*/
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odm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x0);
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odm_set_bb_reg(dm, R_0x1e24, BIT(31), 0);
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/*@1SS~4ss A, AB, ABC, ABCD*/
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odm_set_bb_reg(dm, R_0x820, 0xffff, 0xf731);
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odm_set_bb_reg(dm, R_0x1e2c, 0xffffffff, 0xe4240400);
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}
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}
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#endif
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#if (RTL8198F_SUPPORT)
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if (dm->support_ic_type == ODM_RTL8198F) {
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if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {
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for (i = RF_PATH_A; i <= RF_PATH_D; i++) {
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/*RF mode table write enable*/
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odm_set_rf_reg(dm, (enum rf_path)i, RF_0xef,
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BIT(19), 0x1);
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/*Select RX mode*/
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odm_set_rf_reg(dm, (enum rf_path)i, RF_0x30,
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0xfffff, 0x18000);
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/*Set Table data*/
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odm_set_rf_reg(dm, (enum rf_path)i, RF_0x31,
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0xfffff, 0x4f);
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/*Select RX mode*/
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odm_set_rf_reg(dm, (enum rf_path)i, RF_0x32,
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0xfffff, 0x71fc0);
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/*RF mode table write disable*/
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odm_set_rf_reg(dm, (enum rf_path)i, RF_0xef,
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BIT(19), 0x0);
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}
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}
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/*@if Nsts > Nc, don't apply V matrix*/
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odm_set_bb_reg(dm, R_0x1e24, BIT(11), 1);
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if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {
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/*@enable BB TxBF ant mapping register*/
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odm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x2);
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odm_set_bb_reg(dm, R_0x1e24, BIT(30), 1);
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/* logic mapping */
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/* TX BF logic map and TX path en for Nsts = 1~4 */
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odm_set_bb_reg(dm, R_0x820, 0xffff0000, 0xffff);
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odm_set_bb_reg(dm, R_0x1e30, 0xffffffff, 0xe4e4e4e4);
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} else {
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/*@Disable BB TxBF ant mapping register*/
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odm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x0);
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odm_set_bb_reg(dm, R_0x1e24, BIT(31), 0);
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/*@1SS~4ss A, AB, ABC, ABCD*/
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odm_set_bb_reg(dm, R_0x820, 0xffff, 0xf731);
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odm_set_bb_reg(dm, R_0x1e2c, 0xffffffff, 0xe4240400);
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}
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}
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#endif
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}
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void phydm_txbf_avoid_hang(void *dm_void)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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/* avoid CCK CCA hang when the BF mode */
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odm_set_bb_reg(dm, R_0x1e6c, 0x100000, 0x1);
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}
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#if (RTL8814B_SUPPORT == 1)
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void phydm_txbf_80p80_rfmode(void *dm_void, u8 su_bfee_cnt, u8 mu_bfee_cnt)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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u8 i;
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if (dm->rf_type == RF_1T1R)
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return;
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if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {
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for (i = RF_PATH_A; i <= RF_PATH_D; i += 3) {
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/*RF mode table write enable*/
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odm_set_rf_reg(dm, (enum rf_path)i, RF_0xef, BIT(19),
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0x1);
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/*Select RX mode*/
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odm_set_rf_reg(dm, (enum rf_path)i, RF_0x33, 0xF, 2);
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/*Set Table data*/
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odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3e, 0xfffff,
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0x3fc);
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/*Set Table data*/
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odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3f, 0xfffff,
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0x280f7);
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/*Select RX mode*/
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odm_set_rf_reg(dm, (enum rf_path)i, RF_0x33, 0xF, 3);
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/*Set Table data*/
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odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3e, 0xfffff,
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0x365);
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/*Set Table data*/
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odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3f, 0xfffff,
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0xafcf7);
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/*RF mode table write disable*/
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odm_set_rf_reg(dm, (enum rf_path)i, RF_0xef, BIT(19),
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0x0);
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}
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for (i = RF_PATH_B; i <= RF_PATH_C; i++) {
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/*RF mode table write enable*/
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odm_set_rf_reg(dm, (enum rf_path)i, RF_0xef, BIT(19),
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0x1);
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/*Select RX mode*/
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odm_set_rf_reg(dm, (enum rf_path)i, RF_0x33, 0xF, 2);
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/*Set Table data*/
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odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3f, 0xfffff,
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0x280c7);
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/*Set Table data*/
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odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3f, 0xfffff,
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0x280c7);
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/*Select RX mode*/
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odm_set_rf_reg(dm, (enum rf_path)i, RF_0x33, 0xF, 3);
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/*Set Table data*/
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odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3e, 0xfffff,
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0x365);
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/*Set Table data*/
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odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3f, 0xfffff,
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0xafcc7);
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/*RF mode table write disable*/
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odm_set_rf_reg(dm, (enum rf_path)i, RF_0xef, BIT(19),
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0x0);
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}
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}
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/*@if Nsts > Nc, don't apply V matrix*/
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odm_set_bb_reg(dm, R_0x1e24, BIT(11), 1);
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if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {
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/*@enable BB TxBF ant mapping register*/
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odm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x2);
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odm_set_bb_reg(dm, R_0x1e24, BIT(30), 1);
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/* logic mapping */
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/* TX BF logic map and TX path en for Nsts = 1~2 */
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odm_set_bb_reg(dm, R_0x820, 0xff0000, 0x33); /*seg0*/
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odm_set_bb_reg(dm, R_0x824, 0xff00, 0xcc); /*seg1*/
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odm_set_bb_reg(dm, R_0x1e30, 0xffff, 0xe4e4);
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} else {
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/*@Disable BB TxBF ant mapping register*/
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odm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x0);
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odm_set_bb_reg(dm, R_0x1e24, BIT(31), 0);
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/*@1SS~2ss A, AB*/
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odm_set_bb_reg(dm, R_0x820, 0xff, 0x31); /*seg0*/
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odm_set_bb_reg(dm, R_0x824, 0xff, 0xc8); /*seg1*/
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odm_set_bb_reg(dm, R_0x1e2c, 0xffff, 0xe420);
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}
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}
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#endif
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#endif /*PHYSTS_3RD_TYPE_IC*/
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#endif /*CONFIG_BB_TXBF_API*/
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