mirror of
https://github.com/Mange/rtl8192eu-linux-driver
synced 2024-11-27 07:47:43 +00:00
453 lines
14 KiB
C
453 lines
14 KiB
C
/******************************************************************************
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*
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* Copyright(c) 2007 - 2017 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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/******************************************************************************
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* include files
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*****************************************************************************/
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#include "mp_precomp.h"
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#include "phydm_precomp.h"
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#ifdef CONFIG_PSD_TOOL
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u32 phydm_get_psd_data(void *dm_void, u32 psd_tone_idx, u32 igi)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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struct psd_info *dm_psd_table = &dm->dm_psd_table;
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u32 psd_report = 0;
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if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
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odm_set_bb_reg(dm, R_0x1e8c, 0x3ff, psd_tone_idx & 0x3ff);
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odm_set_bb_reg(dm, R_0x1e88, BIT(27) | BIT(26),
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psd_tone_idx >> 10);
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/*PSD trigger start*/
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odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(18), 1);
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ODM_delay_us(10);
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/*PSD trigger stop*/
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odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(18), 0);
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} else if (dm->support_ic_type == ODM_RTL8721D) {
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odm_set_bb_reg(dm, dm_psd_table->psd_reg, 0xfff, psd_tone_idx);
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odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(28), 1);
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/*PSD trigger start*/
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ODM_delay_us(10);
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odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(28), 0);
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/*PSD trigger stop*/
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psd_report = odm_get_bb_reg(dm, dm_psd_table->psd_report_reg,
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0xffffff);
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psd_report = psd_report >> 5;
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} else {
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odm_set_bb_reg(dm, dm_psd_table->psd_reg, 0x3ff, psd_tone_idx);
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/*PSD trigger start*/
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odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(22), 1);
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ODM_delay_us(10);
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/*PSD trigger stop*/
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odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(22), 0);
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}
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if (dm->support_ic_type & ODM_RTL8821C) {
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psd_report = odm_get_bb_reg(dm, dm_psd_table->psd_report_reg,
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0xffffff);
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psd_report = psd_report >> 5;
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} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
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psd_report = odm_get_bb_reg(dm, dm_psd_table->psd_report_reg,
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0xffffff);
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} else {
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psd_report = odm_get_bb_reg(dm, dm_psd_table->psd_report_reg,
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0xffff);
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}
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psd_report = odm_convert_to_db((u64)psd_report) + igi;
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return psd_report;
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}
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u8 psd_result_cali_tone_8821[7] = {21, 28, 33, 93, 98, 105, 127};
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u8 psd_result_cali_val_8821[7] = {67, 69, 71, 72, 71, 69, 67};
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u8 phydm_psd(void *dm_void, u32 igi, u16 start_point, u16 stop_point)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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struct psd_info *dm_psd_table = &dm->dm_psd_table;
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u32 i = 0, mod_tone_idx = 0;
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u32 t = 0;
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u16 fft_max_half_bw = 0;
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u16 psd_fc_channel = dm_psd_table->psd_fc_channel;
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u8 ag_rf_mode_reg = 0;
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u8 is_5G = 0;
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u32 psd_result_tmp = 0;
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u8 psd_result = 0;
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u8 psd_result_cali_tone[7] = {0};
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u8 psd_result_cali_val[7] = {0};
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u8 noise_idx = 0;
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u8 set_result = 0;
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u32 igi_tmp = 0x6e;
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if (dm->support_ic_type == ODM_RTL8821) {
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odm_move_memory(dm, psd_result_cali_tone,
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psd_result_cali_tone_8821, 7);
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odm_move_memory(dm, psd_result_cali_val,
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psd_result_cali_val_8821, 7);
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}
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dm_psd_table->psd_in_progress = 1;
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PHYDM_DBG(dm, ODM_COMP_API, "PSD Start =>\n");
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/* @[Stop DIG]*/
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/* @IGI target at 0dBm & make it can't CCA*/
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if (phydm_pause_func(dm, F00_DIG, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_3, 1,
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&igi_tmp) == PAUSE_FAIL) {
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return PHYDM_SET_FAIL;
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}
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ODM_delay_us(10);
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if (phydm_stop_ic_trx(dm, PHYDM_SET) == PHYDM_SET_FAIL) {
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phydm_pause_func(dm, F00_DIG, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_3,
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1, &igi_tmp);
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return PHYDM_SET_FAIL;
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}
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/* @[Set IGI]*/
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phydm_write_dig_reg(dm, (u8)igi);
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/* @[Backup RF Reg]*/
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dm_psd_table->rf_0x18_bkp = odm_get_rf_reg(dm, RF_PATH_A, RF_0x18,
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RFREG_MASK);
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dm_psd_table->rf_0x18_bkp_b = odm_get_rf_reg(dm, RF_PATH_B, RF_0x18,
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RFREG_MASK);
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if (psd_fc_channel > 14) {
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is_5G = 1;
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if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8812F)) {
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if (psd_fc_channel < 80)
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ag_rf_mode_reg = 0x1;
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else if (psd_fc_channel >= 80 && psd_fc_channel <= 140)
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ag_rf_mode_reg = 0x3;
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else if (psd_fc_channel > 140)
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ag_rf_mode_reg = 0x5;
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} else if (dm->support_ic_type == ODM_RTL8721D) {
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if (psd_fc_channel >= 36 && psd_fc_channel <= 64)
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ag_rf_mode_reg = 0x1;
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else if (psd_fc_channel >= 100 && psd_fc_channel <= 140)
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ag_rf_mode_reg = 0x5;
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else if (psd_fc_channel > 140)
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ag_rf_mode_reg = 0x9;
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} else {
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if (psd_fc_channel >= 36 && psd_fc_channel <= 64)
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ag_rf_mode_reg = 0x1;
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else if (psd_fc_channel >= 100 && psd_fc_channel <= 140)
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ag_rf_mode_reg = 0x3;
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else if (psd_fc_channel > 140)
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ag_rf_mode_reg = 0x5;
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}
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}
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/* Set RF fc*/
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odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0xff, psd_fc_channel);
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odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0xff, psd_fc_channel);
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odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0x300, is_5G);
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odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0x300, is_5G);
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if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8812F)) {
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/* @2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
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odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0x3000,
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dm_psd_table->psd_bw_rf_reg);
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odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0x3000,
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dm_psd_table->psd_bw_rf_reg);
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/* Set RF ag fc mode*/
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odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0x70000,
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ag_rf_mode_reg);
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odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0x70000,
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ag_rf_mode_reg);
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} else {
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/* @2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
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if (dm->support_ic_type == ODM_RTL8721D) {
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odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0x1c00,
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dm_psd_table->psd_bw_rf_reg);
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} else {
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odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0xc00,
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dm_psd_table->psd_bw_rf_reg);
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}
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odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0xc00,
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dm_psd_table->psd_bw_rf_reg);
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/* Set RF ag fc mode*/
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odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0xf0000,
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ag_rf_mode_reg);
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odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0xf0000,
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ag_rf_mode_reg);
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}
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if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
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PHYDM_DBG(dm, ODM_COMP_API, "0x1d70=((0x%x))\n",
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odm_get_bb_reg(dm, R_0x1d70, MASKDWORD));
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else
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PHYDM_DBG(dm, ODM_COMP_API, "0xc50=((0x%x))\n",
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odm_get_bb_reg(dm, R_0xc50, MASKDWORD));
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PHYDM_DBG(dm, ODM_COMP_API, "RF0x18=((0x%x))\n",
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odm_get_rf_reg(dm, RF_PATH_A, RF_0x18, RFREG_MASK));
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/* @[Stop 3-wires]*/
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phydm_stop_3_wire(dm, PHYDM_SET);
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ODM_delay_us(10);
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if (stop_point > (dm_psd_table->fft_smp_point - 1))
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stop_point = (dm_psd_table->fft_smp_point - 1);
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if (start_point > (dm_psd_table->fft_smp_point - 1))
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start_point = (dm_psd_table->fft_smp_point - 1);
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if (start_point > stop_point)
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stop_point = start_point;
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for (i = start_point; i <= stop_point; i++) {
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fft_max_half_bw = (dm_psd_table->fft_smp_point) >> 1;
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if (i < fft_max_half_bw)
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mod_tone_idx = i + fft_max_half_bw;
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else
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mod_tone_idx = i - fft_max_half_bw;
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psd_result_tmp = 0;
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for (t = 0; t < dm_psd_table->sw_avg_time; t++)
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psd_result_tmp += phydm_get_psd_data(dm, mod_tone_idx,
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igi);
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psd_result =
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(u8)((psd_result_tmp / dm_psd_table->sw_avg_time)) -
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dm_psd_table->psd_pwr_common_offset;
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if (dm_psd_table->fft_smp_point == 128 &&
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dm_psd_table->noise_k_en) {
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if (i > psd_result_cali_tone[noise_idx])
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noise_idx++;
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if (noise_idx > 6)
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noise_idx = 6;
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if (psd_result >= psd_result_cali_val[noise_idx])
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psd_result = psd_result -
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psd_result_cali_val[noise_idx];
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else
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psd_result = 0;
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dm_psd_table->psd_result[i] = psd_result;
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}
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PHYDM_DBG(dm, ODM_COMP_API, "[%d] N_cali = %d, PSD = %d\n",
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mod_tone_idx, psd_result_cali_val[noise_idx],
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psd_result);
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}
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/*@[Start 3-wires]*/
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phydm_stop_3_wire(dm, PHYDM_REVERT);
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ODM_delay_us(10);
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/*@[Revert Reg]*/
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set_result = phydm_stop_ic_trx(dm, PHYDM_REVERT);
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odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, RFREG_MASK,
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dm_psd_table->rf_0x18_bkp);
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odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, RFREG_MASK,
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dm_psd_table->rf_0x18_bkp_b);
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PHYDM_DBG(dm, ODM_COMP_API, "PSD finished\n\n");
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phydm_pause_func(dm, F00_DIG, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_3, 1,
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&igi_tmp);
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dm_psd_table->psd_in_progress = 0;
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return PHYDM_SET_SUCCESS;
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}
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void phydm_psd_para_setting(void *dm_void, u8 sw_avg_time, u8 hw_avg_time,
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u8 i_q_setting, u16 fft_smp_point, u8 ant_sel,
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u8 psd_input, u8 channel, u8 noise_k_en)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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struct psd_info *dm_psd_table = &dm->dm_psd_table;
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u8 fft_smp_point_idx = 0;
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dm_psd_table->fft_smp_point = fft_smp_point;
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if (sw_avg_time == 0)
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sw_avg_time = 1;
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dm_psd_table->sw_avg_time = sw_avg_time;
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dm_psd_table->psd_fc_channel = channel;
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dm_psd_table->noise_k_en = noise_k_en;
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if (fft_smp_point == 128)
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fft_smp_point_idx = 0;
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else if (fft_smp_point == 256)
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fft_smp_point_idx = 1;
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else if (fft_smp_point == 512)
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fft_smp_point_idx = 2;
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else if (fft_smp_point == 1024)
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fft_smp_point_idx = 3;
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if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
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odm_set_bb_reg(dm, R_0x1e8c, BIT(11) | BIT(10), i_q_setting);
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odm_set_bb_reg(dm, R_0x1e8c, BIT(13) | BIT(12), hw_avg_time);
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if (fft_smp_point == 4096) {
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odm_set_bb_reg(dm, R_0x1e88, BIT(31) | BIT(30), 0x2);
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} else if (fft_smp_point == 2048) {
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odm_set_bb_reg(dm, R_0x1e88, BIT(31) | BIT(30), 0x1);
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} else {
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odm_set_bb_reg(dm, R_0x1e88, BIT(31) | BIT(30), 0x0);
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odm_set_bb_reg(dm, R_0x1e8c, BIT(15) | BIT(14),
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fft_smp_point_idx);
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}
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odm_set_bb_reg(dm, R_0x1e8c, BIT(17) | BIT(16), ant_sel);
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odm_set_bb_reg(dm, R_0x1e8c, BIT(23) | BIT(22), psd_input);
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} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
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odm_set_bb_reg(dm, R_0x910, BIT(11) | BIT(10), i_q_setting);
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odm_set_bb_reg(dm, R_0x910, BIT(13) | BIT(12), hw_avg_time);
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odm_set_bb_reg(dm, R_0x910, BIT(15) | BIT(14),
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fft_smp_point_idx);
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odm_set_bb_reg(dm, R_0x910, BIT(17) | BIT(16), ant_sel);
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odm_set_bb_reg(dm, R_0x910, BIT(23), psd_input);
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} else if (dm->support_ic_type == ODM_RTL8721D) {
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odm_set_bb_reg(dm, 0x808, BIT(19) | BIT(18), i_q_setting);
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odm_set_bb_reg(dm, 0x808, BIT(21) | BIT(20), hw_avg_time);
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odm_set_bb_reg(dm, 0x808, BIT(23) | BIT(22), fft_smp_point_idx);
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odm_set_bb_reg(dm, 0x804, BIT(5) | BIT(4), ant_sel);
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odm_set_bb_reg(dm, 0x80C, BIT(23), psd_input);
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}
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/*@bw = (*dm->band_width); //ODM_BW20M */
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/*@channel = *(dm->channel);*/
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}
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void phydm_psd_init(void *dm_void)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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struct psd_info *dm_psd_table = &dm->dm_psd_table;
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PHYDM_DBG(dm, ODM_COMP_API, "PSD para init\n");
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dm_psd_table->psd_in_progress = false;
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if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
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dm_psd_table->psd_reg = R_0x1e8c;
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dm_psd_table->psd_report_reg = R_0x2d90;
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/*@2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
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dm_psd_table->psd_bw_rf_reg = 1;
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} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
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dm_psd_table->psd_reg = R_0x910;
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dm_psd_table->psd_report_reg = R_0xf44;
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/*@2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
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if (ODM_IC_11AC_2_SERIES)
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dm_psd_table->psd_bw_rf_reg = 1;
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else
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dm_psd_table->psd_bw_rf_reg = 2;
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} else {
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dm_psd_table->psd_reg = R_0x808;
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dm_psd_table->psd_report_reg = R_0x8b4;
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/*@2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
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dm_psd_table->psd_bw_rf_reg = 2;
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}
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dm_psd_table->psd_pwr_common_offset = 0;
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phydm_psd_para_setting(dm, 1, 2, 3, 128, 0, 0, 7, 0);
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}
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void phydm_psd_debug(void *dm_void, char input[][16], u32 *_used,
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char *output, u32 *_out_len)
|
|
{
|
|
struct dm_struct *dm = (struct dm_struct *)dm_void;
|
|
char help[] = "-h";
|
|
u32 var1[10] = {0};
|
|
u32 used = *_used;
|
|
u32 out_len = *_out_len;
|
|
u8 i = 0;
|
|
|
|
if ((strcmp(input[1], help) == 0)) {
|
|
#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
|
|
if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
|
|
PDM_SNPF(out_len, used, output + used, out_len - used,
|
|
"{0} {sw_avg} {hw_avg 0:3} {1:I,2:Q,3:IQ} {fft_point: 128*(1:4) 2048 4096}\n{path_sel 0~3} {0:ADC, 1:rxdata_fir_in, 2:rx_nbi_nf_stage2} {CH} {noise_k}\n\n");
|
|
else
|
|
#endif
|
|
PDM_SNPF(out_len, used, output + used, out_len - used,
|
|
"{0} {sw_avg} {hw_avg 0:3} {1:I,2:Q,3:IQ} {fft_point: 128*(1:4)} {path_sel 0~3} {0:ADC, 1:RXIQC} {CH} {noise_k}\n");
|
|
|
|
PDM_SNPF(out_len, used, output + used, out_len - used,
|
|
"{1} {IGI(hex)} {start_point} {stop_point}\n");
|
|
goto out;
|
|
}
|
|
|
|
PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
|
|
|
|
if (var1[0] == 0) {
|
|
for (i = 1; i < 10; i++) {
|
|
if (input[i + 1])
|
|
PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
|
|
&var1[i]);
|
|
}
|
|
PDM_SNPF(out_len, used, output + used, out_len - used,
|
|
"sw_avg_time=((%d)), hw_avg_time=((%d)), IQ=((%d)), fft=((%d)), path=((%d)), input =((%d)) ch=((%d)), noise_k=((%d))\n",
|
|
var1[1], var1[2], var1[3], var1[4], var1[5],
|
|
var1[6], (u8)var1[7], (u8)var1[8]);
|
|
phydm_psd_para_setting(dm, (u8)var1[1], (u8)var1[2],
|
|
(u8)var1[3], (u16)var1[4],
|
|
(u8)var1[5], (u8)var1[6],
|
|
(u8)var1[7], (u8)var1[8]);
|
|
|
|
} else if (var1[0] == 1) {
|
|
PHYDM_SSCANF(input[2], DCMD_HEX, &var1[1]);
|
|
PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]);
|
|
PHYDM_SSCANF(input[4], DCMD_DECIMAL, &var1[3]);
|
|
PDM_SNPF(out_len, used, output + used, out_len - used,
|
|
"IGI=((0x%x)), start_point=((%d)), stop_point=((%d))\n",
|
|
var1[1], var1[2], var1[3]);
|
|
dm->debug_components |= ODM_COMP_API;
|
|
if (phydm_psd(dm, var1[1], (u16)var1[2], (u16)var1[3]) ==
|
|
PHYDM_SET_FAIL)
|
|
PDM_SNPF(out_len, used, output + used, out_len - used,
|
|
"PSD_SET_FAIL\n");
|
|
dm->debug_components &= ~(ODM_COMP_API);
|
|
}
|
|
|
|
out:
|
|
*_used = used;
|
|
*_out_len = out_len;
|
|
}
|
|
|
|
u8 phydm_get_psd_result_table(void *dm_void, int index)
|
|
{
|
|
struct dm_struct *dm = (struct dm_struct *)dm_void;
|
|
struct psd_info *dm_psd_table = &dm->dm_psd_table;
|
|
u8 result = 0;
|
|
|
|
if (index < 128)
|
|
result = dm_psd_table->psd_result[index];
|
|
|
|
return result;
|
|
}
|
|
|
|
#endif
|