mirror of
https://github.com/Mange/rtl8192eu-linux-driver
synced 2024-11-01 11:15:31 +00:00
1387cf623d
Version information: 20140812_rtl8192EU_linux_v4.3.1.1_11320 2014-08-12 version 4.3.1.1_11320 Source: ftp://files.dlink.com.au/products/DWA-131/REV_E/Drivers/DWA-131_Linux_driver_v4.3.1.1.zip This version does not currently work on newer kernels, but it does contain USB ID 2001:3319, which a lot of other repos in GitHub does not.
353 lines
10 KiB
C
353 lines
10 KiB
C
/******************************************************************************
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*
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* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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*
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******************************************************************************/
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#define _RTL8192E_XMIT_C_
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//#include <drv_types.h>
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#include <rtl8192e_hal.h>
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void _dbg_dump_tx_info(_adapter *padapter,int frame_tag, u8 *ptxdesc)
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{
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u8 bDumpTxPkt;
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u8 bDumpTxDesc = _FALSE;
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rtw_hal_get_def_var(padapter, HAL_DEF_DBG_DUMP_TXPKT, &(bDumpTxPkt));
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if(bDumpTxPkt ==1){//dump txdesc for data frame
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DBG_871X("dump tx_desc for data frame\n");
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if((frame_tag&0x0f) == DATA_FRAMETAG){
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bDumpTxDesc = _TRUE;
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}
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}
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else if(bDumpTxPkt ==2){//dump txdesc for mgnt frame
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DBG_871X("dump tx_desc for mgnt frame\n");
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if((frame_tag&0x0f) == MGNT_FRAMETAG){
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bDumpTxDesc = _TRUE;
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}
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}
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else if(bDumpTxPkt ==3){//dump early info
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}
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if(bDumpTxDesc){
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// ptxdesc->txdw4 = cpu_to_le32(0x00001006);//RTS Rate=24M
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// ptxdesc->txdw6 = 0x6666f800;
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DBG_8192C("=====================================\n");
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DBG_8192C("Offset00(0x%08x)\n",*((u32 *)(ptxdesc)));
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DBG_8192C("Offset04(0x%08x)\n",*((u32 *)(ptxdesc+4)));
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DBG_8192C("Offset08(0x%08x)\n",*((u32 *)(ptxdesc+8)));
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DBG_8192C("Offset12(0x%08x)\n",*((u32 *)(ptxdesc+12)));
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DBG_8192C("Offset16(0x%08x)\n",*((u32 *)(ptxdesc+16)));
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DBG_8192C("Offset20(0x%08x)\n",*((u32 *)(ptxdesc+20)));
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DBG_8192C("Offset24(0x%08x)\n",*((u32 *)(ptxdesc+24)));
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DBG_8192C("Offset28(0x%08x)\n",*((u32 *)(ptxdesc+28)));
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DBG_8192C("Offset32(0x%08x)\n",*((u32 *)(ptxdesc+32)));
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DBG_8192C("Offset36(0x%08x)\n",*((u32 *)(ptxdesc+36)));
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DBG_8192C("=====================================\n");
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}
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}
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/*
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* Description:
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* Aggregation packets and send to hardware
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*
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* Return:
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* 0 Success
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* -1 Hardware resource(TX FIFO) not ready
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* -2 Software resource(xmitbuf) not ready
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*/
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#ifdef CONFIG_TX_EARLY_MODE
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//#define DBG_EMINFO
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#if RTL8188E_EARLY_MODE_PKT_NUM_10 == 1
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#define EARLY_MODE_MAX_PKT_NUM 10
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#else
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#define EARLY_MODE_MAX_PKT_NUM 5
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#endif
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struct EMInfo{
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u8 EMPktNum;
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u16 EMPktLen[EARLY_MODE_MAX_PKT_NUM];
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};
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void
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InsertEMContent_8192E(
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struct EMInfo *pEMInfo,
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IN pu1Byte VirtualAddress)
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{
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#if RTL8188E_EARLY_MODE_PKT_NUM_10 == 1
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u1Byte index=0;
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u4Byte dwtmp=0;
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#endif
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_rtw_memset(VirtualAddress, 0, EARLY_MODE_INFO_SIZE);
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if(pEMInfo->EMPktNum==0)
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return;
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#ifdef DBG_EMINFO
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{
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int i;
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DBG_8192C("\n%s ==> pEMInfo->EMPktNum =%d\n",__FUNCTION__,pEMInfo->EMPktNum);
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for(i=0;i< EARLY_MODE_MAX_PKT_NUM;i++){
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DBG_8192C("%s ==> pEMInfo->EMPktLen[%d] =%d\n",__FUNCTION__,i,pEMInfo->EMPktLen[i]);
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}
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}
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#endif
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#if RTL8188E_EARLY_MODE_PKT_NUM_10 == 1
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SET_EARLYMODE_PKTNUM(VirtualAddress, pEMInfo->EMPktNum);
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if(pEMInfo->EMPktNum == 1){
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dwtmp = pEMInfo->EMPktLen[0];
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}else{
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dwtmp = pEMInfo->EMPktLen[0];
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dwtmp += ((dwtmp%4)?(4-dwtmp%4):0)+4;
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dwtmp += pEMInfo->EMPktLen[1];
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}
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SET_EARLYMODE_LEN0(VirtualAddress, dwtmp);
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if(pEMInfo->EMPktNum <= 3){
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dwtmp = pEMInfo->EMPktLen[2];
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}else{
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dwtmp = pEMInfo->EMPktLen[2];
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dwtmp += ((dwtmp%4)?(4-dwtmp%4):0)+4;
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dwtmp += pEMInfo->EMPktLen[3];
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}
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SET_EARLYMODE_LEN1(VirtualAddress, dwtmp);
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if(pEMInfo->EMPktNum <= 5){
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dwtmp = pEMInfo->EMPktLen[4];
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}else{
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dwtmp = pEMInfo->EMPktLen[4];
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dwtmp += ((dwtmp%4)?(4-dwtmp%4):0)+4;
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dwtmp += pEMInfo->EMPktLen[5];
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}
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SET_EARLYMODE_LEN2_1(VirtualAddress, dwtmp&0xF);
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SET_EARLYMODE_LEN2_2(VirtualAddress, dwtmp>>4);
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if(pEMInfo->EMPktNum <= 7){
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dwtmp = pEMInfo->EMPktLen[6];
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}else{
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dwtmp = pEMInfo->EMPktLen[6];
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dwtmp += ((dwtmp%4)?(4-dwtmp%4):0)+4;
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dwtmp += pEMInfo->EMPktLen[7];
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}
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SET_EARLYMODE_LEN3(VirtualAddress, dwtmp);
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if(pEMInfo->EMPktNum <= 9){
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dwtmp = pEMInfo->EMPktLen[8];
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}else{
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dwtmp = pEMInfo->EMPktLen[8];
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dwtmp += ((dwtmp%4)?(4-dwtmp%4):0)+4;
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dwtmp += pEMInfo->EMPktLen[9];
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}
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SET_EARLYMODE_LEN4(VirtualAddress, dwtmp);
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#else
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SET_EARLYMODE_PKTNUM(VirtualAddress, pEMInfo->EMPktNum);
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SET_EARLYMODE_LEN0(VirtualAddress, pEMInfo->EMPktLen[0]);
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SET_EARLYMODE_LEN1(VirtualAddress, pEMInfo->EMPktLen[1]);
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SET_EARLYMODE_LEN2_1(VirtualAddress, pEMInfo->EMPktLen[2]&0xF);
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SET_EARLYMODE_LEN2_2(VirtualAddress, pEMInfo->EMPktLen[2]>>4);
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SET_EARLYMODE_LEN3(VirtualAddress, pEMInfo->EMPktLen[3]);
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SET_EARLYMODE_LEN4(VirtualAddress, pEMInfo->EMPktLen[4]);
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#endif
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//RT_PRINT_DATA(COMP_SEND, DBG_LOUD, "EMHdr:", VirtualAddress, 8);
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}
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void UpdateEarlyModeInfo8192E(struct xmit_priv *pxmitpriv,struct xmit_buf *pxmitbuf )
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{
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//_adapter *padapter, struct xmit_frame *pxmitframe,struct tx_servq *ptxservq
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int index,j;
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u16 offset,pktlen;
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PTXDESC_8192E ptxdesc;
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u8 *pmem,*pEMInfo_mem;
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s8 node_num_0=0,node_num_1=0;
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struct EMInfo eminfo;
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struct agg_pkt_info *paggpkt;
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struct xmit_frame *pframe = (struct xmit_frame*)pxmitbuf->priv_data;
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pmem= pframe->buf_addr;
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#ifdef DBG_EMINFO
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DBG_8192C("\n%s ==> agg_num:%d\n",__FUNCTION__, pframe->agg_num);
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for(index=0;index<pframe->agg_num;index++){
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offset = pxmitpriv->agg_pkt[index].offset;
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pktlen = pxmitpriv->agg_pkt[index].pkt_len;
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DBG_8192C("%s ==> agg_pkt[%d].offset=%d\n",__FUNCTION__,index,offset);
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DBG_8192C("%s ==> agg_pkt[%d].pkt_len=%d\n",__FUNCTION__,index,pktlen);
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}
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#endif
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if( pframe->agg_num > EARLY_MODE_MAX_PKT_NUM)
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{
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node_num_0 = pframe->agg_num;
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node_num_1= EARLY_MODE_MAX_PKT_NUM-1;
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}
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for(index=0;index<pframe->agg_num;index++){
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offset = pxmitpriv->agg_pkt[index].offset;
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pktlen = pxmitpriv->agg_pkt[index].pkt_len;
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_rtw_memset(&eminfo,0,sizeof(struct EMInfo));
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if( pframe->agg_num > EARLY_MODE_MAX_PKT_NUM){
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if(node_num_0 > EARLY_MODE_MAX_PKT_NUM){
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eminfo.EMPktNum = EARLY_MODE_MAX_PKT_NUM;
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node_num_0--;
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}
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else{
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eminfo.EMPktNum = node_num_1;
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node_num_1--;
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}
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}
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else{
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eminfo.EMPktNum = pframe->agg_num-(index+1);
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}
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for(j=0;j< eminfo.EMPktNum ;j++){
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eminfo.EMPktLen[j] = pxmitpriv->agg_pkt[index+1+j].pkt_len+4;// 4 bytes CRC
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}
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if(pmem){
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if(index==0){
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ptxdesc = (PTXDESC_8192E)(pmem);
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pEMInfo_mem = ((u8 *)ptxdesc)+TXDESC_SIZE;
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}
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else{
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pmem = pmem + pxmitpriv->agg_pkt[index-1].offset;
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ptxdesc = (PTXDESC_8192E)(pmem);
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pEMInfo_mem = ((u8 *)ptxdesc)+TXDESC_SIZE;
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}
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#ifdef DBG_EMINFO
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DBG_8192C("%s ==> desc.pkt_len=%d\n",__FUNCTION__,ptxdesc->pktlen);
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#endif
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InsertEMContent_8192E(&eminfo,pEMInfo_mem);
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}
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}
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_rtw_memset(pxmitpriv->agg_pkt,0,sizeof(struct agg_pkt_info)*MAX_AGG_PKT_NUM);
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}
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#endif
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u8
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BWMapping_92E(
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IN PADAPTER Adapter,
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IN struct pkt_attrib *pattrib
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)
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{
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u8 BWSettingOfDesc = 0;
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PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
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//DBG_871X("BWMapping pHalData->CurrentChannelBW %d, pattrib->bwmode %d \n",pHalData->CurrentChannelBW,pattrib->bwmode);
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if(pHalData->CurrentChannelBW== CHANNEL_WIDTH_40)
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{
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if(pattrib->bwmode == CHANNEL_WIDTH_40)
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BWSettingOfDesc = 1;
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else
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BWSettingOfDesc = 0;
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}
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else
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BWSettingOfDesc = 0;
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//if(pTcb->bBTTxPacket)
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// BWSettingOfDesc = 0;
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return BWSettingOfDesc;
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}
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u8
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SCMapping_92E(
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IN PADAPTER Adapter,
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IN struct pkt_attrib *pattrib
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)
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{
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u8 SCSettingOfDesc = 0;
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PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
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//DBG_871X("SCMapping: pHalData->CurrentChannelBW %d, pHalData->nCur80MhzPrimeSC %d, pHalData->nCur40MhzPrimeSC %d \n",pHalData->CurrentChannelBW,pHalData->nCur80MhzPrimeSC,pHalData->nCur40MhzPrimeSC);
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if(pHalData->CurrentChannelBW == CHANNEL_WIDTH_80)
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{
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if(pattrib->bwmode == CHANNEL_WIDTH_80)
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{
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SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE;
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}
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else if(pattrib->bwmode == CHANNEL_WIDTH_40)
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{
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if(pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
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SCSettingOfDesc = VHT_DATA_SC_40_LOWER_OF_80MHZ;
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else if(pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
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SCSettingOfDesc = VHT_DATA_SC_40_UPPER_OF_80MHZ;
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else
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DBG_871X("%s- CurrentChannelBW:%d, SCMapping: Not Correct Primary40MHz Setting \n",__FUNCTION__,pHalData->CurrentChannelBW);
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}
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else
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{
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if((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER))
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SCSettingOfDesc = VHT_DATA_SC_20_LOWEST_OF_80MHZ;
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else if((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER))
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SCSettingOfDesc = VHT_DATA_SC_20_LOWER_OF_80MHZ;
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else if((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER))
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SCSettingOfDesc = VHT_DATA_SC_20_UPPER_OF_80MHZ;
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else if((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER))
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SCSettingOfDesc = VHT_DATA_SC_20_UPPERST_OF_80MHZ;
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else
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DBG_871X("%s- CurrentChannelBW:%d, SCMapping: Not Correct Primary40MHz Setting \n",__FUNCTION__,pHalData->CurrentChannelBW);
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}
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}
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else if(pHalData->CurrentChannelBW== CHANNEL_WIDTH_40)
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{
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//DBG_871X("SCMapping: HT Case: pHalData->CurrentChannelBW %d, pHalData->nCur40MhzPrimeSC %d \n",pHalData->CurrentChannelBW,pHalData->nCur40MhzPrimeSC);
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if(pattrib->bwmode == CHANNEL_WIDTH_40)
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{
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SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE;
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}
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else if(pattrib->bwmode == CHANNEL_WIDTH_20)
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{
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if(pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
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{
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SCSettingOfDesc = VHT_DATA_SC_20_UPPER_OF_80MHZ;
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}
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else if(pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
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{
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SCSettingOfDesc = VHT_DATA_SC_20_LOWER_OF_80MHZ;
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}
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else
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{
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SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE;
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}
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}
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}
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else
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{
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SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE;
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}
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return SCSettingOfDesc;
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}
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