mirror of
https://github.com/Mange/rtl8192eu-linux-driver
synced 2024-11-01 19:25:31 +00:00
323 lines
8.2 KiB
C
323 lines
8.2 KiB
C
/******************************************************************************
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*
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* Copyright(c) 2007 - 2017 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#ifndef __PHYDMDIG_H__
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#define __PHYDMDIG_H__
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#define DIG_VERSION "2.3"
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#define DIG_HW 0
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#define DIG_LIMIT_PERIOD 60 /*@60 sec*/
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/*@--------------------Define ---------------------------------------*/
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/*@=== [DIG Boundary] ========================================*/
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/*@DIG coverage mode*/
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#define DIG_MAX_COVERAGR 0x26
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#define DIG_MIN_COVERAGE 0x1c
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#define DIG_MAX_OF_MIN_COVERAGE 0x22
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/*@[DIG Balance mode]*/
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#if (DIG_HW == 1)
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#define DIG_MAX_BALANCE_MODE 0x32
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#else
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#define DIG_MAX_BALANCE_MODE 0x3e
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#endif
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#define DIG_MAX_OF_MIN_BALANCE_MODE 0x2a
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/*@[DIG Performance mode]*/
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#define DIG_MAX_PERFORMANCE_MODE 0x5a
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#define DIG_MAX_OF_MIN_PERFORMANCE_MODE 0x40 /*@[WLANBB-871]*/
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#define DIG_MIN_PERFORMANCE 0x20
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/*@DIG DFS function*/
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#define DIG_MAX_DFS 0x28
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#define DIG_MIN_DFS 0x20
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/*@DIG LPS function*/
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#define DIG_MAX_LPS 0x3e
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#define DIG_MIN_LPS 0x20
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#ifdef PHYDM_TDMA_DIG_SUPPORT
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#define DIG_NUM_OF_TDMA_STATES 2 /*@L, H state*/
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#define DIG_TIMER_MS 250
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#define ONE_SEC_MS 1000
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#endif
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/*@=== [DIG FA Threshold] ======================================*/
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/*Normal*/
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#define DM_DIG_FA_TH0 500
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#define DM_DIG_FA_TH1 750
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/*@LPS*/
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#define DM_DIG_FA_TH0_LPS 4 /* @-> 4 lps */
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#define DM_DIG_FA_TH1_LPS 15 /* @-> 15 lps */
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#define DM_DIG_FA_TH2_LPS 30 /* @-> 30 lps */
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#define RSSI_OFFSET_DIG_LPS 5
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#define DIG_RECORD_NUM 4
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/*@--------------------Enum-----------------------------------*/
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enum dig_goupcheck_level {
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DIG_GOUPCHECK_LEVEL_0,
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DIG_GOUPCHECK_LEVEL_1,
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DIG_GOUPCHECK_LEVEL_2
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};
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enum phydm_dig_mode {
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PHYDM_DIG_PERFORAMNCE_MODE = 0,
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PHYDM_DIG_COVERAGE_MODE = 1,
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};
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#ifdef IS_USE_NEW_TDMA
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enum tdma_dig_timer {
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INIT_TDMA_DIG_TIMMER,
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CANCEL_TDMA_DIG_TIMMER,
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RELEASE_TDMA_DIG_TIMMER
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};
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enum tdma_dig_state {
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TDMA_DIG_LOW_STATE = 0,
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TDMA_DIG_HIGH_STATE = 1,
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NORMAL_DIG = 2
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};
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#endif
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/*@--------------------Define Struct-----------------------------------*/
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#ifdef CFG_DIG_DAMPING_CHK
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struct phydm_dig_recorder_strcut {
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u8 igi_bitmap; /*@Don't add any new parameter before this*/
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u8 igi_history[DIG_RECORD_NUM];
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u32 fa_history[DIG_RECORD_NUM];
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u8 damping_limit_en;
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u8 damping_limit_val; /*@Limit IGI_dyn_min*/
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u32 limit_time;
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u8 limit_rssi;
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};
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#endif
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struct phydm_mcc_dig {
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u8 mcc_rssi_A;
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u8 mcc_rssi_B;
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};
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struct phydm_dig_struct {
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#ifdef CFG_DIG_DAMPING_CHK
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struct phydm_dig_recorder_strcut dig_recorder_t;
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u8 dig_dl_en; /*@damping limit function enable*/
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#endif
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boolean is_dbg_fa_th;
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u8 cur_ig_value;
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u8 rvrt_val;
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u8 igi_backup;
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u8 rx_gain_range_max; /*@dig_dynamic_max*/
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u8 rx_gain_range_min; /*@dig_dynamic_min*/
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u8 dm_dig_max; /*@Absolutly upper bound*/
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u8 dm_dig_min; /*@Absolutly lower bound*/
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u8 dig_max_of_min; /*@Absolutly max of min*/
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boolean is_media_connect;
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u32 ant_div_rssi_max;
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u8 *is_p2p_in_process;
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enum dig_goupcheck_level go_up_chk_lv;
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u16 fa_th[3];
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#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8821C_SUPPORT ||\
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RTL8198F_SUPPORT || RTL8192F_SUPPORT || RTL8195B_SUPPORT ||\
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RTL8822C_SUPPORT || RTL8814B_SUPPORT || RTL8721D_SUPPORT)
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u8 rf_gain_idx;
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u8 agc_table_idx;
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u8 big_jump_lmt[16];
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u8 enable_adjust_big_jump:1;
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u8 big_jump_step1:3;
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u8 big_jump_step2:2;
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u8 big_jump_step3:2;
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#endif
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u8 upcheck_init_val;
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u8 lv0_ratio_reciprocal;
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u8 lv1_ratio_reciprocal;
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#ifdef PHYDM_TDMA_DIG_SUPPORT
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u8 cur_ig_value_tdma;
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u8 low_ig_value;
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u8 tdma_dig_state; /*@To distinguish which state is now.(L-sate or H-state)*/
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u8 tdma_dig_cnt; /*@for phydm_tdma_dig_timer_check use*/
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u8 pre_tdma_dig_cnt;
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u8 sec_factor;
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u32 cur_timestamp;
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u32 pre_timestamp;
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u32 fa_start_timestamp;
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u32 fa_end_timestamp;
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u32 fa_acc_1sec_timestamp;
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#ifdef IS_USE_NEW_TDMA
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u8 tdma_dig_block_cnt;/*@for 1 second dump indicator use*/
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/*@dynamic upper bound for L/H state*/
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u8 tdma_rx_gain_max[DIG_NUM_OF_TDMA_STATES];
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/*@dynamic lower bound for L/H state*/
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u8 tdma_rx_gain_min[DIG_NUM_OF_TDMA_STATES];
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/*To distinguish current state(L-sate or H-state)*/
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#endif
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#endif
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};
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struct phydm_fa_struct {
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u32 cnt_parity_fail;
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u32 cnt_rate_illegal;
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u32 cnt_crc8_fail;
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u32 cnt_crc8_fail_vht;
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u32 cnt_mcs_fail;
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u32 cnt_mcs_fail_vht;
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u32 cnt_ofdm_fail;
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u32 cnt_ofdm_fail_pre; /* @For RTL8881A */
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u32 cnt_cck_fail;
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u32 cnt_all;
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u32 cnt_all_accumulated;
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u32 cnt_all_pre;
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u32 cnt_fast_fsync;
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u32 cnt_sb_search_fail;
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u32 cnt_ofdm_cca;
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u32 cnt_cck_cca;
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u32 cnt_cca_all;
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u32 cnt_bw_usc;
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u32 cnt_bw_lsc;
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u32 cnt_cck_crc32_error;
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u32 cnt_cck_crc32_ok;
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u32 cnt_ofdm_crc32_error;
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u32 cnt_ofdm_crc32_ok;
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u32 cnt_ht_crc32_error;
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u32 cnt_ht_crc32_ok;
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u32 cnt_ht_crc32_error_agg;
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u32 cnt_ht_crc32_ok_agg;
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u32 cnt_vht_crc32_error;
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u32 cnt_vht_crc32_ok;
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u32 cnt_crc32_error_all;
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u32 cnt_crc32_ok_all;
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u32 time_fa_all;
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boolean cck_block_enable;
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boolean ofdm_block_enable;
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u32 dbg_port0;
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boolean edcca_flag;
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};
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#ifdef PHYDM_TDMA_DIG_SUPPORT
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struct phydm_fa_acc_struct {
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u32 cnt_parity_fail;
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u32 cnt_rate_illegal;
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u32 cnt_crc8_fail;
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u32 cnt_mcs_fail;
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u32 cnt_ofdm_fail;
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u32 cnt_ofdm_fail_pre; /*@For RTL8881A*/
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u32 cnt_cck_fail;
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u32 cnt_all;
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u32 cnt_all_pre;
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u32 cnt_fast_fsync;
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u32 cnt_sb_search_fail;
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u32 cnt_ofdm_cca;
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u32 cnt_cck_cca;
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u32 cnt_cca_all;
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u32 cnt_cck_crc32_error;
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u32 cnt_cck_crc32_ok;
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u32 cnt_ofdm_crc32_error;
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u32 cnt_ofdm_crc32_ok;
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u32 cnt_ht_crc32_error;
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u32 cnt_ht_crc32_ok;
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u32 cnt_vht_crc32_error;
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u32 cnt_vht_crc32_ok;
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u32 cnt_crc32_error_all;
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u32 cnt_crc32_ok_all;
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u32 cnt_all_1sec;
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u32 cnt_cca_all_1sec;
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u32 cnt_cck_fail_1sec;
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};
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#endif /*@#ifdef PHYDM_TDMA_DIG_SUPPORT*/
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/*@--------------------Function declaration-----------------------------*/
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void phydm_write_dig_reg(void *dm_void, u8 igi);
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void odm_write_dig(void *dm_void, u8 current_igi);
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u8 phydm_get_igi(void *dm_void, enum bb_path path);
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void phydm_set_dig_val(void *dm_void, u32 *val_buf, u8 val_len);
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void odm_pause_dig(void *dm_void, enum phydm_pause_type pause_type,
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enum phydm_pause_level pause_level, u8 igi_value);
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void phydm_dig_init(void *dm_void);
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void phydm_dig(void *dm_void);
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void phydm_dig_lps_32k(void *dm_void);
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void phydm_dig_by_rssi_lps(void *dm_void);
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void phydm_false_alarm_counter_statistics(void *dm_void);
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#ifdef PHYDM_TDMA_DIG_SUPPORT
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void phydm_set_tdma_dig_timer(void *dm_void);
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void phydm_tdma_dig_timer_check(void *dm_void);
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void phydm_tdma_dig(void *dm_void);
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void phydm_tdma_false_alarm_counter_check(void *dm_void);
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void phydm_tdma_dig_add_interrupt_mask_handler(void *dm_void);
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void phydm_false_alarm_counter_reset(void *dm_void);
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void phydm_false_alarm_counter_acc(void *dm_void, boolean rssi_dump_en);
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void phydm_false_alarm_counter_acc_reset(void *dm_void);
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#ifdef IS_USE_NEW_TDMA
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void phydm_tdma_dig_timers(void *dm_void, u8 state);
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void phydm_tdma_dig_cbk(void *dm_void);
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void phydm_tdma_dig_workitem_callback(void *dm_void);
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void phydm_tdma_fa_cnt_chk(void *dm_void);
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void phydm_tdma_low_dig(void *dm_void);
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void phydm_tdma_high_dig(void *dm_void);
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void phydm_fa_cnt_acc(void *dm_void, boolean rssi_dump_en,
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u8 cur_tdma_dig_state);
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#endif /*@#ifdef IS_USE_NEW_TDMA*/
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#endif /*@#ifdef PHYDM_TDMA_DIG_SUPPORT*/
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void phydm_set_ofdm_agc_tab(void *dm_void, u8 tab_sel);
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void phydm_dig_debug(void *dm_void, char input[][16], u32 *_used, char *output,
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u32 *_out_len);
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#ifdef CONFIG_MCC_DM
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void phydm_mcc_igi_cal(void *dm_void);
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#endif
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#endif
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