mirror of
https://github.com/Mange/rtl8192eu-linux-driver
synced 2024-11-01 11:15:31 +00:00
528 lines
17 KiB
C
528 lines
17 KiB
C
//============================================================
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// Description:
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//
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// This file is for 8812/8821/8811 TXBF mechanism
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//
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//============================================================
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#include "mp_precomp.h"
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#include "../phydm_precomp.h"
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#if (BEAMFORMING_SUPPORT == 1)
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#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1))
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VOID
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HalTxbf8812A_setNDPArate(
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IN PVOID pDM_VOID,
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IN u1Byte BW,
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IN u1Byte Rate
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)
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{
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PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
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ODM_Write1Byte(pDM_Odm, REG_NDPA_OPT_CTRL_8812A, (Rate << 2 | BW));
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}
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VOID
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halTxbfJaguar_RfMode(
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IN PVOID pDM_VOID,
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IN PRT_BEAMFORMING_INFO pBeamInfo
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)
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{
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PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
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if (pDM_Odm->RFType == ODM_1T1R)
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return;
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ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] set TxIQGen\n", __func__));
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ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WeLut_Jaguar, 0x80000, 0x1); /*RF Mode table write enable*/
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ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WeLut_Jaguar, 0x80000, 0x1); /*RF Mode table write enable*/
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if (pBeamInfo->beamformee_su_cnt > 0) {
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// Paath_A
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ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableAddr, 0x78000, 0x3); /*Select RX mode*/
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ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData0, 0xfffff, 0x3F7FF); /*Set Table data*/
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ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData1, 0xfffff, 0xE26BF); /*Enable TXIQGEN in RX mode*/
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// Path_B
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ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableAddr, 0x78000, 0x3); /*Select RX mode*/
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ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData0, 0xfffff, 0x3F7FF); /*Set Table data*/
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ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData1, 0xfffff, 0xE26BF); /*Enable TXIQGEN in RX mode*/
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} else {
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// Paath_A
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ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableAddr, 0x78000, 0x3); /*Select RX mode*/
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ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData0, 0xfffff, 0x3F7FF); /*Set Table data*/
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ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData1, 0xfffff, 0xC26BF); /*Disable TXIQGEN in RX mode*/
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// Path_B
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ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableAddr, 0x78000, 0x3); /*Select RX mode*/
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ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData0, 0xfffff, 0x3F7FF); /*Set Table data*/
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ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData1, 0xfffff, 0xC26BF); /*Disable TXIQGEN in RX mode*/
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}
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ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WeLut_Jaguar, 0x80000, 0x0); /*RF Mode table write disable*/
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ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WeLut_Jaguar, 0x80000, 0x0); /*RF Mode table write disable*/
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if (pBeamInfo->beamformee_su_cnt > 0)
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ODM_SetBBReg(pDM_Odm, rTxPath_Jaguar, bMaskByte1, 0x33);
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else
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ODM_SetBBReg(pDM_Odm, rTxPath_Jaguar, bMaskByte1, 0x11);
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}
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VOID
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halTxbfJaguar_DownloadNDPA(
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IN PVOID pDM_VOID,
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IN u1Byte Idx
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)
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{
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PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
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u1Byte u1bTmp = 0, tmpReg422 = 0, Head_Page;
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u1Byte BcnValidReg = 0, count = 0, DLBcnCount = 0;
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BOOLEAN bSendBeacon = FALSE;
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u1Byte TxPageBndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8812; /*default reseved 1 page for the IC type which is undefined.*/
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PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo;
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PRT_BEAMFORMEE_ENTRY pBeamEntry = pBeamInfo->BeamformeeEntry + Idx;
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PADAPTER Adapter = pDM_Odm->Adapter;
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#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
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*pDM_Odm->pbFwDwRsvdPageInProgress = TRUE;
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#endif
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ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));
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if (Idx == 0)
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Head_Page = 0xFE;
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else
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Head_Page = 0xFE;
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Adapter->HalFunc.GetHalDefVarHandler(Adapter, HAL_DEF_TX_PAGE_BOUNDARY, (pu1Byte)&TxPageBndy);
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/*Set REG_CR bit 8. DMA beacon by SW.*/
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u1bTmp = ODM_Read1Byte(pDM_Odm, REG_CR_8812A + 1);
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ODM_Write1Byte(pDM_Odm, REG_CR_8812A + 1, (u1bTmp | BIT0));
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/*Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.*/
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tmpReg422 = ODM_Read1Byte(pDM_Odm, REG_FWHW_TXQ_CTRL_8812A + 2);
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ODM_Write1Byte(pDM_Odm, REG_FWHW_TXQ_CTRL_8812A + 2, tmpReg422 & (~BIT6));
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if (tmpReg422 & BIT6) {
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ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("SetBeamformDownloadNDPA_8812(): There is an Adapter is sending beacon.\n"));
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bSendBeacon = TRUE;
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}
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/*TDECTRL[15:8] 0x209[7:0] = 0xF6 Beacon Head for TXDMA*/
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ODM_Write1Byte(pDM_Odm, REG_TDECTRL_8812A + 1, Head_Page);
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do {
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/*Clear beacon valid check bit.*/
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BcnValidReg = ODM_Read1Byte(pDM_Odm, REG_TDECTRL_8812A + 2);
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ODM_Write1Byte(pDM_Odm, REG_TDECTRL_8812A + 2, (BcnValidReg | BIT0));
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/*download NDPA rsvd page.*/
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if (pBeamEntry->BeamformEntryCap & BEAMFORMER_CAP_VHT_SU)
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Beamforming_SendVHTNDPAPacket(pDM_Odm, pBeamEntry->MacAddr, pBeamEntry->AID, pBeamEntry->SoundBW, BEACON_QUEUE);
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else
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Beamforming_SendHTNDPAPacket(pDM_Odm, pBeamEntry->MacAddr, pBeamEntry->SoundBW, BEACON_QUEUE);
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/*check rsvd page download OK.*/
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BcnValidReg = ODM_Read1Byte(pDM_Odm, REG_TDECTRL_8812A + 2);
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count = 0;
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while (!(BcnValidReg & BIT0) && count < 20) {
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count++;
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ODM_delay_ms(10);
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BcnValidReg = ODM_Read1Byte(pDM_Odm, REG_TDECTRL_8812A + 2);
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}
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DLBcnCount++;
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} while (!(BcnValidReg & BIT0) && DLBcnCount < 5);
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if (!(BcnValidReg & BIT0))
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ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Download RSVD page failed!\n", __func__));
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/*TDECTRL[15:8] 0x209[7:0] = 0xF6 Beacon Head for TXDMA*/
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ODM_Write1Byte(pDM_Odm, REG_TDECTRL_8812A + 1, TxPageBndy);
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/*To make sure that if there exists an adapter which would like to send beacon.*/
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/*If exists, the origianl value of 0x422[6] will be 1, we should check this to*/
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/*prevent from setting 0x422[6] to 0 after download reserved page, or it will cause*/
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/*the beacon cannot be sent by HW.*/
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/*2010.06.23. Added by tynli.*/
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if (bSendBeacon)
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ODM_Write1Byte(pDM_Odm, REG_FWHW_TXQ_CTRL_8812A + 2, tmpReg422);
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/*Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/
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/*Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/
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u1bTmp = ODM_Read1Byte(pDM_Odm, REG_CR_8812A + 1);
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ODM_Write1Byte(pDM_Odm, REG_CR_8812A + 1, (u1bTmp & (~BIT0)));
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pBeamEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_PROGRESSED;
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#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
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*pDM_Odm->pbFwDwRsvdPageInProgress = FALSE;
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#endif
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}
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VOID
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halTxbfJaguar_FwTxBFCmd(
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IN PVOID pDM_VOID
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)
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{
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PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
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u1Byte Idx, Period0 = 0, Period1 = 0;
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u1Byte PageNum0 = 0xFF, PageNum1 = 0xFF;
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u1Byte u1TxBFParm[3] = {0};
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PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo;
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for (Idx = 0; Idx < BEAMFORMEE_ENTRY_NUM; Idx++) {
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/*Modified by David*/
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if (pBeamInfo->BeamformeeEntry[Idx].bUsed && pBeamInfo->BeamformeeEntry[Idx].BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) {
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if (Idx == 0) {
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if (pBeamInfo->BeamformeeEntry[Idx].bSound)
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PageNum0 = 0xFE;
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else
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PageNum0 = 0xFF; /*stop sounding*/
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Period0 = (u1Byte)(pBeamInfo->BeamformeeEntry[Idx].SoundPeriod);
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} else if (Idx == 1) {
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if (pBeamInfo->BeamformeeEntry[Idx].bSound)
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PageNum1 = 0xFE;
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else
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PageNum1 = 0xFF; /*stop sounding*/
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Period1 = (u1Byte)(pBeamInfo->BeamformeeEntry[Idx].SoundPeriod);
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}
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}
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}
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u1TxBFParm[0] = PageNum0;
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u1TxBFParm[1] = PageNum1;
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u1TxBFParm[2] = (Period1 << 4) | Period0;
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ODM_FillH2CCmd(pDM_Odm, PHYDM_H2C_TXBF, 3, u1TxBFParm);
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ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD,
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("[%s] PageNum0 = %d Period0 = %d, PageNum1 = %d Period1 %d\n", __func__, PageNum0, Period0, PageNum1, Period1));
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}
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VOID
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HalTxbfJaguar_Enter(
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IN PVOID pDM_VOID,
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IN u1Byte BFerBFeeIdx
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)
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{
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PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
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u1Byte i = 0;
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u1Byte BFerIdx = (BFerBFeeIdx & 0xF0) >> 4;
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u1Byte BFeeIdx = (BFerBFeeIdx & 0xF);
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u4Byte CSI_Param;
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PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo;
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RT_BEAMFORMEE_ENTRY BeamformeeEntry;
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RT_BEAMFORMER_ENTRY BeamformerEntry;
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u2Byte STAid = 0;
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ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]Start!\n", __func__));
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halTxbfJaguar_RfMode(pDM_Odm, pBeamformingInfo);
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if (pDM_Odm->RFType == ODM_2T2R)
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ODM_SetBBReg(pDM_Odm, ODM_REG_CSI_CONTENT_VALUE, bMaskDWord, 0x00000000); /*Nc =2*/
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else
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ODM_SetBBReg(pDM_Odm, ODM_REG_CSI_CONTENT_VALUE, bMaskDWord, 0x01081008); /*Nc =1*/
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if ((pBeamformingInfo->beamformer_su_cnt > 0) && (BFerIdx < BEAMFORMER_ENTRY_NUM)) {
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BeamformerEntry = pBeamformingInfo->BeamformerEntry[BFerIdx];
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/*Sounding protocol control*/
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ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8812A, 0xCB);
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/*MAC address/Partial AID of Beamformer*/
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if (BFerIdx == 0) {
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for (i = 0; i < 6 ; i++)
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ODM_Write1Byte(pDM_Odm, (REG_BFMER0_INFO_8812A + i), BeamformerEntry.MacAddr[i]);
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/*CSI report use legacy ofdm so don't need to fill P_AID. */
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/*PlatformEFIOWrite2Byte(Adapter, REG_BFMER0_INFO_8812A+6, BeamformEntry.P_AID); */
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} else {
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for (i = 0; i < 6 ; i++)
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ODM_Write1Byte(pDM_Odm, (REG_BFMER1_INFO_8812A + i), BeamformerEntry.MacAddr[i]);
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/*CSI report use legacy ofdm so don't need to fill P_AID.*/
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/*PlatformEFIOWrite2Byte(Adapter, REG_BFMER1_INFO_8812A+6, BeamformEntry.P_AID);*/
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}
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/*CSI report parameters of Beamformee*/
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if (BeamformerEntry.BeamformEntryCap & BEAMFORMEE_CAP_VHT_SU) {
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if (pDM_Odm->RFType == ODM_2T2R)
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CSI_Param = 0x01090109;
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else
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CSI_Param = 0x01080108;
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} else {
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if (pDM_Odm->RFType == ODM_2T2R)
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CSI_Param = 0x03090309;
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else
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CSI_Param = 0x03080308;
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}
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ODM_Write4Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8812A, CSI_Param);
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ODM_Write4Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW40_8812A, CSI_Param);
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ODM_Write4Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW80_8812A, CSI_Param);
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/*Timeout value for MAC to leave NDP_RX_standby_state (60 us, Test chip) (80 us, MP chip)*/
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ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8812A + 3, 0x50);
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}
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if ((pBeamformingInfo->beamformee_su_cnt > 0) && (BFeeIdx < BEAMFORMEE_ENTRY_NUM)) {
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BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[BFeeIdx];
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if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS))
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STAid = BeamformeeEntry.MacId;
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else
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STAid = BeamformeeEntry.P_AID;
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/*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/
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if (BFeeIdx == 0) {
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ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8812A, STAid);
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ODM_Write1Byte(pDM_Odm, REG_TXBF_CTRL_8812A + 3, ODM_Read1Byte(pDM_Odm, REG_TXBF_CTRL_8812A + 3) | BIT4 | BIT6 | BIT7);
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} else
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ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8812A + 2, STAid | BIT12 | BIT14 | BIT15);
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/*CSI report parameters of Beamformee*/
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if (BFeeIdx == 0) {
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/*Get BIT24 & BIT25*/
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u1Byte tmp = ODM_Read1Byte(pDM_Odm, REG_BFMEE_SEL_8812A + 3) & 0x3;
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ODM_Write1Byte(pDM_Odm, REG_BFMEE_SEL_8812A + 3, tmp | 0x60);
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ODM_Write2Byte(pDM_Odm, REG_BFMEE_SEL_8812A, STAid | BIT9);
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} else {
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/*Set BIT25*/
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ODM_Write2Byte(pDM_Odm, REG_BFMEE_SEL_8812A + 2, STAid | 0xE200);
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}
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phydm_Beamforming_Notify(pDM_Odm);
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}
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}
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VOID
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HalTxbfJaguar_Leave(
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IN PVOID pDM_VOID,
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IN u1Byte Idx
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)
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{
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PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
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PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo;
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RT_BEAMFORMER_ENTRY BeamformerEntry;
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RT_BEAMFORMEE_ENTRY BeamformeeEntry;
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if (Idx < BEAMFORMER_ENTRY_NUM) {
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BeamformerEntry = pBeamformingInfo->BeamformerEntry[Idx];
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BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[Idx];
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} else
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return;
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ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]Start!, IDx = %d\n", __func__, Idx));
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/*Clear P_AID of Beamformee*/
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/*Clear MAC address of Beamformer*/
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/*Clear Associated Bfmee Sel*/
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if (BeamformerEntry.BeamformEntryCap == BEAMFORMING_CAP_NONE) {
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ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8812A, 0xC8);
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if (Idx == 0) {
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ODM_Write4Byte(pDM_Odm, REG_BFMER0_INFO_8812A, 0);
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ODM_Write2Byte(pDM_Odm, REG_BFMER0_INFO_8812A + 4, 0);
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ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8812A, 0);
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ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW40_8812A, 0);
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ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW80_8812A, 0);
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} else {
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ODM_Write4Byte(pDM_Odm, REG_BFMER1_INFO_8812A, 0);
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ODM_Write2Byte(pDM_Odm, REG_BFMER1_INFO_8812A + 4, 0);
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ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8812A, 0);
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ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW40_8812A, 0);
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ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW80_8812A, 0);
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}
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}
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if (BeamformeeEntry.BeamformEntryCap == BEAMFORMING_CAP_NONE) {
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halTxbfJaguar_RfMode(pDM_Odm, pBeamformingInfo);
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if (Idx == 0) {
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ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8812A, 0x0);
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ODM_Write2Byte(pDM_Odm, REG_BFMEE_SEL_8812A, 0);
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} else {
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ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8812A + 2, ODM_Read2Byte(pDM_Odm, REG_TXBF_CTRL_8812A + 2) & 0xF000);
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ODM_Write2Byte(pDM_Odm, REG_BFMEE_SEL_8812A + 2, ODM_Read2Byte(pDM_Odm, REG_BFMEE_SEL_8812A + 2) & 0x60);
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}
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}
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}
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VOID
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HalTxbfJaguar_Status(
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IN PVOID pDM_VOID,
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IN u1Byte Idx
|
|
)
|
|
{
|
|
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
|
u2Byte BeamCtrlVal;
|
|
u4Byte BeamCtrlReg;
|
|
PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo;
|
|
RT_BEAMFORMEE_ENTRY BeamformEntry = pBeamInfo->BeamformeeEntry[Idx];
|
|
|
|
if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS))
|
|
BeamCtrlVal = BeamformEntry.MacId;
|
|
else
|
|
BeamCtrlVal = BeamformEntry.P_AID;
|
|
|
|
if (Idx == 0)
|
|
BeamCtrlReg = REG_TXBF_CTRL_8812A;
|
|
else {
|
|
BeamCtrlReg = REG_TXBF_CTRL_8812A + 2;
|
|
BeamCtrlVal |= BIT12 | BIT14 | BIT15;
|
|
}
|
|
|
|
if (BeamformEntry.BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) {
|
|
if (BeamformEntry.SoundBW == CHANNEL_WIDTH_20)
|
|
BeamCtrlVal |= BIT9;
|
|
else if (BeamformEntry.SoundBW == CHANNEL_WIDTH_40)
|
|
BeamCtrlVal |= (BIT9 | BIT10);
|
|
else if (BeamformEntry.SoundBW == CHANNEL_WIDTH_80)
|
|
BeamCtrlVal |= (BIT9 | BIT10 | BIT11);
|
|
} else
|
|
BeamCtrlVal &= ~(BIT9 | BIT10 | BIT11);
|
|
|
|
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] BeamCtrlVal = 0x%x!\n", __func__, BeamCtrlVal));
|
|
|
|
ODM_Write2Byte(pDM_Odm, BeamCtrlReg, BeamCtrlVal);
|
|
}
|
|
|
|
|
|
|
|
VOID
|
|
HalTxbfJaguar_FwTxBF(
|
|
IN PVOID pDM_VOID,
|
|
IN u1Byte Idx
|
|
)
|
|
{
|
|
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
|
PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo;
|
|
PRT_BEAMFORMEE_ENTRY pBeamEntry = pBeamInfo->BeamformeeEntry + Idx;
|
|
|
|
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));
|
|
|
|
if (pBeamEntry->BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSING)
|
|
halTxbfJaguar_DownloadNDPA(pDM_Odm, Idx);
|
|
|
|
halTxbfJaguar_FwTxBFCmd(pDM_Odm);
|
|
}
|
|
|
|
|
|
VOID
|
|
HalTxbfJaguar_Patch(
|
|
IN PVOID pDM_VOID,
|
|
IN u1Byte Operation
|
|
)
|
|
{
|
|
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
|
PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo;
|
|
|
|
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));
|
|
|
|
if (pBeamInfo->BeamformCap == BEAMFORMING_CAP_NONE)
|
|
return;
|
|
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
|
if (Operation == SCAN_OPT_BACKUP_BAND0)
|
|
ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8812A, 0xC8);
|
|
else if (Operation == SCAN_OPT_RESTORE)
|
|
ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8812A, 0xCB);
|
|
#endif
|
|
}
|
|
|
|
VOID
|
|
HalTxbfJaguar_Clk_8812A(
|
|
IN PVOID pDM_VOID
|
|
)
|
|
{
|
|
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
|
u2Byte u2btmp;
|
|
u1Byte Count = 0, u1btmp;
|
|
PADAPTER Adapter = pDM_Odm->Adapter;
|
|
|
|
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));
|
|
|
|
if (*(pDM_Odm->pbScanInProcess)) {
|
|
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] return by Scan\n", __func__));
|
|
return;
|
|
}
|
|
#if DEV_BUS_TYPE == RT_PCI_INTERFACE
|
|
/*Stop PCIe TxDMA*/
|
|
ODM_Write1Byte(pDM_Odm, REG_PCIE_CTRL_REG_8812A + 1, 0xFE);
|
|
#endif
|
|
|
|
/*Stop Usb TxDMA*/
|
|
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
|
RT_DISABLE_FUNC(Adapter, DF_TX_BIT);
|
|
PlatformReturnAllPendingTxPackets(Adapter);
|
|
#else
|
|
rtw_write_port_cancel(Adapter);
|
|
#endif
|
|
|
|
/*Wait TXFF empty*/
|
|
for (Count = 0; Count < 100; Count++) {
|
|
u2btmp = ODM_Read2Byte(pDM_Odm, REG_TXPKT_EMPTY_8812A);
|
|
u2btmp = u2btmp & 0xfff;
|
|
if (u2btmp != 0xfff) {
|
|
ODM_delay_ms(10);
|
|
continue;
|
|
} else
|
|
break;
|
|
}
|
|
|
|
/*TX pause*/
|
|
ODM_Write1Byte(pDM_Odm, REG_TXPAUSE_8812A, 0xFF);
|
|
|
|
/*Wait TX State Machine OK*/
|
|
for (Count = 0; Count < 100; Count++) {
|
|
if (ODM_Read4Byte(pDM_Odm, REG_SCH_TXCMD_8812A) != 0)
|
|
continue;
|
|
else
|
|
break;
|
|
}
|
|
|
|
|
|
/*Stop RX DMA path*/
|
|
u1btmp = ODM_Read1Byte(pDM_Odm, REG_RXDMA_CONTROL_8812A);
|
|
ODM_Write1Byte(pDM_Odm, REG_RXDMA_CONTROL_8812A, u1btmp | BIT2);
|
|
|
|
for (Count = 0; Count < 100; Count++) {
|
|
u1btmp = ODM_Read1Byte(pDM_Odm, REG_RXDMA_CONTROL_8812A);
|
|
if (u1btmp & BIT1)
|
|
break;
|
|
else
|
|
ODM_delay_ms(10);
|
|
}
|
|
|
|
/*Disable clock*/
|
|
ODM_Write1Byte(pDM_Odm, REG_SYS_CLKR_8812A + 1, 0xf0);
|
|
/*Disable 320M*/
|
|
ODM_Write1Byte(pDM_Odm, REG_AFE_PLL_CTRL_8812A + 3, 0x8);
|
|
/*Enable 320M*/
|
|
ODM_Write1Byte(pDM_Odm, REG_AFE_PLL_CTRL_8812A + 3, 0xa);
|
|
/*Enable clock*/
|
|
ODM_Write1Byte(pDM_Odm, REG_SYS_CLKR_8812A + 1, 0xfc);
|
|
|
|
|
|
/*Release Tx pause*/
|
|
ODM_Write1Byte(pDM_Odm, REG_TXPAUSE_8812A, 0);
|
|
|
|
/*Enable RX DMA path*/
|
|
u1btmp = ODM_Read1Byte(pDM_Odm, REG_RXDMA_CONTROL_8812A);
|
|
ODM_Write1Byte(pDM_Odm, REG_RXDMA_CONTROL_8812A, u1btmp & (~BIT2));
|
|
#if DEV_BUS_TYPE == RT_PCI_INTERFACE
|
|
/*Enable PCIe TxDMA*/
|
|
ODM_Write1Byte(pDM_Odm, REG_PCIE_CTRL_REG_8812A + 1, 0);
|
|
#endif
|
|
/*Start Usb TxDMA*/
|
|
RT_ENABLE_FUNC(Adapter, DF_TX_BIT);
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#endif
|
|
|