mirror of
https://github.com/Mange/rtl8192eu-linux-driver
synced 2024-11-23 14:05:00 +00:00
508 lines
16 KiB
C
508 lines
16 KiB
C
/******************************************************************************
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*
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* Copyright(c) 2016 - 2017 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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/* ************************************************************
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* Description:
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*
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* This file is for 8814A TXBF mechanism
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*
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* ************************************************************ */
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#include "mp_precomp.h"
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#include "../phydm_precomp.h"
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#ifdef PHYDM_BEAMFORMING_SUPPORT
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#if (RTL8814A_SUPPORT == 1)
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boolean
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phydm_beamforming_set_iqgen_8814A(void *dm_void)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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u8 i = 0;
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u16 counter = 0;
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u32 rf_mode[4];
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for (i = RF_PATH_A; i < MAX_RF_PATH; i++)
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odm_set_rf_reg(dm, i, RF_WE_LUT, 0x80000, 0x1); /*RF mode table write enable*/
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while (1) {
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counter++;
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for (i = RF_PATH_A; i < MAX_RF_PATH; i++)
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odm_set_rf_reg(dm, i, RF_RCK_OS, 0xfffff, 0x18000); /*Select Rx mode*/
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ODM_delay_us(2);
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for (i = RF_PATH_A; i < MAX_RF_PATH; i++)
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rf_mode[i] = odm_get_rf_reg(dm, i, RF_RCK_OS, 0xfffff);
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if (rf_mode[0] == 0x18000 && rf_mode[1] == 0x18000 && rf_mode[2] == 0x18000 && rf_mode[3] == 0x18000)
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break;
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else if (counter == 100) {
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PHYDM_DBG(dm, DBG_TXBF, "iqgen setting fail:8814A\n");
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return false;
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}
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}
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for (i = RF_PATH_A; i < MAX_RF_PATH; i++) {
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odm_set_rf_reg(dm, i, RF_TXPA_G1, 0xfffff, 0xBE77F); /*Set Table data*/
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odm_set_rf_reg(dm, i, RF_TXPA_G2, 0xfffff, 0x226BF); /*@Enable TXIQGEN in Rx mode*/
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}
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odm_set_rf_reg(dm, RF_PATH_A, RF_TXPA_G2, 0xfffff, 0xE26BF); /*@Enable TXIQGEN in Rx mode*/
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for (i = RF_PATH_A; i < MAX_RF_PATH; i++)
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odm_set_rf_reg(dm, i, RF_WE_LUT, 0x80000, 0x0); /*RF mode table write disable*/
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return true;
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}
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void hal_txbf_8814a_set_ndpa_rate(void *dm_void, u8 BW, u8 rate)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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odm_write_1byte(dm, REG_NDPA_OPT_CTRL_8814A, BW);
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odm_write_1byte(dm, REG_NDPA_RATE_8814A, (u8)rate);
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}
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void hal_txbf_8814a_get_tx_rate(void *dm_void)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
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struct _RT_BEAMFORMEE_ENTRY *entry;
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struct ra_table *ra_tab = &dm->dm_ra_table;
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struct cmn_sta_info *sta = NULL;
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u8 data_rate = 0xFF;
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u8 macid = 0;
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entry = &(beam_info->beamformee_entry[beam_info->beamformee_cur_idx]);
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macid = (u8)entry->mac_id;
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sta = dm->phydm_sta_info[macid];
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if (is_sta_active(sta)) {
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data_rate = (sta->ra_info.curr_tx_rate) & 0x7f; /*@Bit7 indicates SGI*/
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beam_info->tx_bf_data_rate = data_rate;
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}
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PHYDM_DBG(dm, DBG_TXBF, "[%s] dm->tx_bf_data_rate = 0x%x\n", __func__,
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beam_info->tx_bf_data_rate);
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}
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void hal_txbf_8814a_reset_tx_path(void *dm_void, u8 idx)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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#if DEV_BUS_TYPE == RT_USB_INTERFACE
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struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
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struct _RT_BEAMFORMEE_ENTRY beamformee_entry;
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u8 nr_index = 0, tx_ss = 0;
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if (idx < BEAMFORMEE_ENTRY_NUM)
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beamformee_entry = beamforming_info->beamformee_entry[idx];
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else
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return;
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if (beamforming_info->last_usb_hub != (*dm->hub_usb_mode)) {
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nr_index = tx_bf_nr(hal_txbf_8814a_get_ntx(dm), beamformee_entry.comp_steering_num_of_bfer);
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if (*dm->hub_usb_mode == 2) {
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if (dm->rf_type == RF_4T4R)
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tx_ss = 0xf;
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else if (dm->rf_type == RF_3T3R)
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tx_ss = 0xe;
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else
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tx_ss = 0x6;
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} else if (*dm->hub_usb_mode == 1) /*USB 2.0 always 2Tx*/
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tx_ss = 0x6;
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else
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tx_ss = 0x6;
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if (tx_ss == 0xf) {
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odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x93f);
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odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKDWORD, 0x93f93f0);
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} else if (tx_ss == 0xe) {
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odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x93e);
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odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8814A, MASKDWORD, 0x93e93e0);
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} else if (tx_ss == 0x6) {
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odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x936);
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odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8814A, MASKLWORD, 0x9360);
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}
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if (idx == 0) {
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switch (nr_index) {
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case 0:
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break;
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case 1: /*Nsts = 2 BC*/
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odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366); /*tx2path, BC*/
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break;
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case 2: /*Nsts = 3 BCD*/
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odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee); /*tx3path, BCD*/
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break;
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default: /*nr>3, same as Case 3*/
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odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff); /*tx4path, ABCD*/
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break;
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}
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} else {
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switch (nr_index) {
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case 0:
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break;
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case 1: /*Nsts = 2 BC*/
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odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366); /*tx2path, BC*/
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break;
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case 2: /*Nsts = 3 BCD*/
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odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee); /*tx3path, BCD*/
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break;
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default: /*nr>3, same as Case 3*/
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odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff); /*tx4path, ABCD*/
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break;
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}
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}
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beamforming_info->last_usb_hub = *dm->hub_usb_mode;
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} else
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return;
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#endif
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}
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u8 hal_txbf_8814a_get_ntx(void *dm_void)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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u8 ntx = 0, tx_ss = 3;
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#if DEV_BUS_TYPE == RT_USB_INTERFACE
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tx_ss = *dm->hub_usb_mode;
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#endif
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if (tx_ss == 3 || tx_ss == 2) {
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if (dm->rf_type == RF_4T4R)
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ntx = 3;
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else if (dm->rf_type == RF_3T3R)
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ntx = 2;
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else
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ntx = 1;
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} else if (tx_ss == 1) /*USB 2.0 always 2Tx*/
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ntx = 1;
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else
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ntx = 1;
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PHYDM_DBG(dm, DBG_TXBF, "[%s] ntx = %d\n", __func__, ntx);
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return ntx;
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}
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u8 hal_txbf_8814a_get_nrx(void *dm_void)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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u8 nrx = 0;
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if (dm->rf_type == RF_4T4R)
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nrx = 3;
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else if (dm->rf_type == RF_3T3R)
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nrx = 2;
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else if (dm->rf_type == RF_2T2R)
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nrx = 1;
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else if (dm->rf_type == RF_2T3R)
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nrx = 2;
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else if (dm->rf_type == RF_2T4R)
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nrx = 3;
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else if (dm->rf_type == RF_1T1R)
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nrx = 0;
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else if (dm->rf_type == RF_1T2R)
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nrx = 1;
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else
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nrx = 0;
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PHYDM_DBG(dm, DBG_TXBF, "[%s] nrx = %d\n", __func__, nrx);
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return nrx;
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}
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void hal_txbf_8814a_rf_mode(void *dm_void,
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struct _RT_BEAMFORMING_INFO *beamforming_info,
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u8 idx)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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u8 nr_index = 0;
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u8 tx_ss = 3; /*@default use 3 Tx*/
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struct _RT_BEAMFORMEE_ENTRY beamformee_entry;
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if (idx < BEAMFORMEE_ENTRY_NUM)
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beamformee_entry = beamforming_info->beamformee_entry[idx];
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else
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return;
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nr_index = tx_bf_nr(hal_txbf_8814a_get_ntx(dm), beamformee_entry.comp_steering_num_of_bfer);
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if (dm->rf_type == RF_1T1R)
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return;
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if (beamforming_info->beamformee_su_cnt > 0) {
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#if DEV_BUS_TYPE == RT_USB_INTERFACE
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beamforming_info->last_usb_hub = *dm->hub_usb_mode;
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tx_ss = *dm->hub_usb_mode;
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#endif
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if (tx_ss == 3 || tx_ss == 2) {
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if (dm->rf_type == RF_4T4R)
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tx_ss = 0xf;
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else if (dm->rf_type == RF_3T3R)
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tx_ss = 0xe;
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else
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tx_ss = 0x6;
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} else if (tx_ss == 1) /*USB 2.0 always 2Tx*/
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tx_ss = 0x6;
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else
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tx_ss = 0x6;
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if (tx_ss == 0xf) {
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odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x93f);
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odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKDWORD, 0x93f93f0);
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} else if (tx_ss == 0xe) {
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odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x93e);
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odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8814A, MASKDWORD, 0x93e93e0);
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} else if (tx_ss == 0x6) {
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odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x936);
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odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8814A, MASKLWORD, 0x9360);
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}
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/*@for 8814 19ac(idx 1), 19b4(idx 0), different Tx ant setting*/
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odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, BIT(28) | BIT29, 0x2); /*@enable BB TxBF ant mapping register*/
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odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, BIT30, 0x1); /*@if Nsts > Nc don't apply V matrix*/
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if (idx == 0) {
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switch (nr_index) {
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case 0:
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break;
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case 1: /*Nsts = 2 BC*/
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odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366); /*tx2path, BC*/
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break;
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case 2: /*Nsts = 3 BCD*/
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odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee); /*tx3path, BCD*/
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break;
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default: /*nr>3, same as Case 3*/
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odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff); /*tx4path, ABCD*/
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break;
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}
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} else {
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switch (nr_index) {
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case 0:
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break;
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case 1: /*Nsts = 2 BC*/
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odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366); /*tx2path, BC*/
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break;
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case 2: /*Nsts = 3 BCD*/
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odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee); /*tx3path, BCD*/
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break;
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default: /*nr>3, same as Case 3*/
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odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff); /*tx4path, ABCD*/
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break;
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}
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}
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}
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if (beamforming_info->beamformee_su_cnt == 0 && beamforming_info->beamformer_su_cnt == 0) {
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odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x932); /*set tx_path selection for 8814a BFer bug refine*/
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odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8814A, MASKDWORD, 0x93e9360);
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}
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}
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void hal_txbf_8814a_enter(void *dm_void, u8 bfer_bfee_idx)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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u8 i = 0;
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u8 bfer_idx = (bfer_bfee_idx & 0xF0) >> 4;
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u8 bfee_idx = (bfer_bfee_idx & 0xF);
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struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
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struct _RT_BEAMFORMEE_ENTRY beamformee_entry;
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struct _RT_BEAMFORMER_ENTRY beamformer_entry;
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u16 sta_id = 0, csi_param = 0;
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u8 nc_index = 0, nr_index = 0, grouping = 0, codebookinfo = 0, coefficientsize = 0;
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PHYDM_DBG(dm, DBG_TXBF, "[%s] bfer_idx=%d, bfee_idx=%d\n", __func__,
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bfer_idx, bfee_idx);
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odm_set_mac_reg(dm, REG_SND_PTCL_CTRL_8814A, MASKBYTE1 | MASKBYTE2, 0x0202);
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if (beamforming_info->beamformer_su_cnt > 0 && bfer_idx < BEAMFORMER_ENTRY_NUM) {
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beamformer_entry = beamforming_info->beamformer_entry[bfer_idx];
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/*Sounding protocol control*/
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odm_write_1byte(dm, REG_SND_PTCL_CTRL_8814A, 0xDB);
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/*@MAC address/Partial AID of Beamformer*/
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if (bfer_idx == 0) {
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for (i = 0; i < 6; i++)
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odm_write_1byte(dm, (REG_ASSOCIATED_BFMER0_INFO_8814A + i), beamformer_entry.mac_addr[i]);
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} else {
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for (i = 0; i < 6; i++)
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odm_write_1byte(dm, (REG_ASSOCIATED_BFMER1_INFO_8814A + i), beamformer_entry.mac_addr[i]);
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}
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/*@CSI report parameters of Beamformer*/
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nc_index = hal_txbf_8814a_get_nrx(dm); /*@for 8814A nrx = 3(4 ant), min=0(1 ant)*/
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nr_index = beamformer_entry.num_of_sounding_dim; /*@0x718[7] = 1 use Nsts, 0x718[7] = 0 use reg setting. as Bfee, we use Nsts, so nr_index don't care*/
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grouping = 0;
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/*@for ac = 1, for n = 3*/
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if (beamformer_entry.beamform_entry_cap & BEAMFORMEE_CAP_VHT_SU)
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codebookinfo = 1;
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else if (beamformer_entry.beamform_entry_cap & BEAMFORMEE_CAP_HT_EXPLICIT)
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codebookinfo = 3;
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coefficientsize = 3;
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csi_param = (u16)((coefficientsize << 10) | (codebookinfo << 8) | (grouping << 6) | (nr_index << 3) | (nc_index));
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if (bfer_idx == 0)
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odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW20_8814A, csi_param);
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else
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odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW20_8814A + 2, csi_param);
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/*ndp_rx_standby_timer, 8814 need > 0x56, suggest from Dvaid*/
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odm_write_1byte(dm, REG_SND_PTCL_CTRL_8814A + 3, 0x40);
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}
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if (beamforming_info->beamformee_su_cnt > 0 && bfee_idx < BEAMFORMEE_ENTRY_NUM) {
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beamformee_entry = beamforming_info->beamformee_entry[bfee_idx];
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hal_txbf_8814a_rf_mode(dm, beamforming_info, bfee_idx);
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if (phydm_acting_determine(dm, phydm_acting_as_ibss))
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sta_id = beamformee_entry.mac_id;
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else
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sta_id = beamformee_entry.p_aid;
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/*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/
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if (bfee_idx == 0) {
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odm_write_2byte(dm, REG_TXBF_CTRL_8814A, sta_id);
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odm_write_1byte(dm, REG_TXBF_CTRL_8814A + 3, odm_read_1byte(dm, REG_TXBF_CTRL_8814A + 3) | BIT(4) | BIT(6) | BIT(7));
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} else
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odm_write_2byte(dm, REG_TXBF_CTRL_8814A + 2, sta_id | BIT(14) | BIT(15) | BIT(12));
|
|
|
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/*@CSI report parameters of Beamformee*/
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if (bfee_idx == 0) {
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/*@Get BIT24 & BIT25*/
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u8 tmp = odm_read_1byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A + 3) & 0x3;
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|
|
|
odm_write_1byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A + 3, tmp | 0x60);
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odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A, sta_id | BIT(9));
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} else
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odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2, sta_id | 0xE200); /*Set BIT25*/
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|
|
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phydm_beamforming_notify(dm);
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}
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}
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|
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void hal_txbf_8814a_leave(void *dm_void, u8 idx)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
|
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struct _RT_BEAMFORMER_ENTRY beamformer_entry;
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struct _RT_BEAMFORMEE_ENTRY beamformee_entry;
|
|
|
|
if (idx < BEAMFORMER_ENTRY_NUM) {
|
|
beamformer_entry = beamforming_info->beamformer_entry[idx];
|
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beamformee_entry = beamforming_info->beamformee_entry[idx];
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} else
|
|
return;
|
|
|
|
/*@Clear P_AID of Beamformee*/
|
|
/*@Clear MAC address of Beamformer*/
|
|
/*@Clear Associated Bfmee Sel*/
|
|
|
|
if (beamformer_entry.beamform_entry_cap == BEAMFORMING_CAP_NONE) {
|
|
odm_write_1byte(dm, REG_SND_PTCL_CTRL_8814A, 0xD8);
|
|
if (idx == 0) {
|
|
odm_write_4byte(dm, REG_ASSOCIATED_BFMER0_INFO_8814A, 0);
|
|
odm_write_2byte(dm, REG_ASSOCIATED_BFMER0_INFO_8814A + 4, 0);
|
|
odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW20_8814A, 0);
|
|
} else {
|
|
odm_write_4byte(dm, REG_ASSOCIATED_BFMER1_INFO_8814A, 0);
|
|
odm_write_2byte(dm, REG_ASSOCIATED_BFMER1_INFO_8814A + 4, 0);
|
|
odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW20_8814A + 2, 0);
|
|
}
|
|
}
|
|
|
|
if (beamformee_entry.beamform_entry_cap == BEAMFORMING_CAP_NONE) {
|
|
hal_txbf_8814a_rf_mode(dm, beamforming_info, idx);
|
|
if (idx == 0) {
|
|
odm_write_2byte(dm, REG_TXBF_CTRL_8814A, 0x0);
|
|
odm_write_1byte(dm, REG_TXBF_CTRL_8814A + 3, odm_read_1byte(dm, REG_TXBF_CTRL_8814A + 3) | BIT(4) | BIT(6) | BIT(7));
|
|
odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A, 0);
|
|
} else {
|
|
odm_write_2byte(dm, REG_TXBF_CTRL_8814A + 2, 0x0 | BIT(14) | BIT(15) | BIT(12));
|
|
|
|
odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2, odm_read_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2) & 0x60);
|
|
}
|
|
}
|
|
}
|
|
|
|
void hal_txbf_8814a_status(void *dm_void, u8 idx)
|
|
{
|
|
struct dm_struct *dm = (struct dm_struct *)dm_void;
|
|
u16 beam_ctrl_val, tmp_val;
|
|
u32 beam_ctrl_reg;
|
|
struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
|
|
struct _RT_BEAMFORMEE_ENTRY beamform_entry;
|
|
|
|
if (idx < BEAMFORMEE_ENTRY_NUM)
|
|
beamform_entry = beamforming_info->beamformee_entry[idx];
|
|
else
|
|
return;
|
|
|
|
if (phydm_acting_determine(dm, phydm_acting_as_ibss))
|
|
beam_ctrl_val = beamform_entry.mac_id;
|
|
else
|
|
beam_ctrl_val = beamform_entry.p_aid;
|
|
|
|
PHYDM_DBG(dm, DBG_TXBF, "@%s, beamform_entry.beamform_entry_state = %d",
|
|
__func__, beamform_entry.beamform_entry_state);
|
|
|
|
if (idx == 0)
|
|
beam_ctrl_reg = REG_TXBF_CTRL_8814A;
|
|
else {
|
|
beam_ctrl_reg = REG_TXBF_CTRL_8814A + 2;
|
|
beam_ctrl_val |= BIT(12) | BIT(14) | BIT(15);
|
|
}
|
|
|
|
if (beamform_entry.beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED && beamforming_info->apply_v_matrix == true) {
|
|
if (beamform_entry.sound_bw == CHANNEL_WIDTH_20)
|
|
beam_ctrl_val |= BIT(9);
|
|
else if (beamform_entry.sound_bw == CHANNEL_WIDTH_40)
|
|
beam_ctrl_val |= (BIT(9) | BIT(10));
|
|
else if (beamform_entry.sound_bw == CHANNEL_WIDTH_80)
|
|
beam_ctrl_val |= (BIT(9) | BIT(10) | BIT(11));
|
|
} else {
|
|
PHYDM_DBG(dm, DBG_TXBF, "@%s, Don't apply Vmatrix", __func__);
|
|
beam_ctrl_val &= ~(BIT(9) | BIT(10) | BIT(11));
|
|
}
|
|
|
|
odm_write_2byte(dm, beam_ctrl_reg, beam_ctrl_val);
|
|
/*@disable NDP packet use beamforming */
|
|
tmp_val = odm_read_2byte(dm, REG_TXBF_CTRL_8814A);
|
|
odm_write_2byte(dm, REG_TXBF_CTRL_8814A, tmp_val | BIT(15));
|
|
}
|
|
|
|
void hal_txbf_8814a_fw_txbf(void *dm_void, u8 idx)
|
|
{
|
|
}
|
|
|
|
#endif /* @(RTL8814A_SUPPORT == 1)*/
|
|
|
|
#endif
|