mirror of
https://github.com/Mange/rtl8192eu-linux-driver
synced 2024-12-27 14:31:41 +00:00
1387cf623d
Version information: 20140812_rtl8192EU_linux_v4.3.1.1_11320 2014-08-12 version 4.3.1.1_11320 Source: ftp://files.dlink.com.au/products/DWA-131/REV_E/Drivers/DWA-131_Linux_driver_v4.3.1.1.zip This version does not currently work on newer kernels, but it does contain USB ID 2001:3319, which a lot of other repos in GitHub does not.
236 lines
6.0 KiB
C
236 lines
6.0 KiB
C
/******************************************************************************
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*
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* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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*
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******************************************************************************/
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#include "../odm_precomp.h"
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#if (RTL8192E_SUPPORT == 1)
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void
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odm_ConfigRFReg_8192E(
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IN PDM_ODM_T pDM_Odm,
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IN u4Byte Addr,
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IN u4Byte Data,
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IN ODM_RF_RADIO_PATH_E RF_PATH,
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IN u4Byte RegAddr
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)
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{
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if(Addr == 0xfe || Addr == 0xffe)
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{
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#ifdef CONFIG_LONG_DELAY_ISSUE
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ODM_sleep_ms(50);
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#else
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ODM_delay_ms(50);
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#endif
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}
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else
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{
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ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data);
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// Add 1us delay between BB/RF register setting.
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ODM_delay_us(1);
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//For disable/enable test in high temperature, the B6 value will fail to fill. Suggestion by Ed 20130.
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if(Addr == 0xb6)
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{
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u4Byte getvalue=0;
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u1Byte count =0;
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getvalue = ODM_GetRFReg(pDM_Odm, RF_PATH, Addr, bMaskDWord);
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ODM_delay_us(1);
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while((getvalue>>8)!=(Data>>8))
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{
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count++;
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ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data);
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ODM_delay_us(1);
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getvalue = ODM_GetRFReg(pDM_Odm, RF_PATH, Addr, bMaskDWord);
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ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [B6] getvalue 0x%x, Data 0x%x, count %d\n", getvalue, Data,count));
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if(count>5)
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break;
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}
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}
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if(Addr == 0xb2)
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{
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u4Byte getvalue=0;
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u1Byte count =0;
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getvalue = ODM_GetRFReg(pDM_Odm, RF_PATH, Addr, bMaskDWord);
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ODM_delay_us(1);
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while(getvalue!=Data)
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{
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count++;
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ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data);
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ODM_delay_us(1);
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//Do LCK againg
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ODM_SetRFReg(pDM_Odm, RF_PATH, 0x18, bRFRegOffsetMask, 0x0fc07);
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ODM_delay_us(1);
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getvalue = ODM_GetRFReg(pDM_Odm, RF_PATH, Addr, bMaskDWord);
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ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [B2] getvalue 0x%x, Data 0x%x, count %d\n", getvalue, Data,count));
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if(count>5)
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break;
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}
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}
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}
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}
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void
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odm_ConfigRF_RadioA_8192E(
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IN PDM_ODM_T pDM_Odm,
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IN u4Byte Addr,
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IN u4Byte Data
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)
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{
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u4Byte content = 0x1000; // RF_Content: radioa_txt
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u4Byte maskforPhySet= (u4Byte)(content&0xE000);
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odm_ConfigRFReg_8192E(pDM_Odm, Addr, Data, ODM_RF_PATH_A, Addr|maskforPhySet);
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ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioA] %08X %08X\n", Addr, Data));
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}
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void
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odm_ConfigRF_RadioB_8192E(
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IN PDM_ODM_T pDM_Odm,
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IN u4Byte Addr,
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IN u4Byte Data
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)
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{
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u4Byte content = 0x1001; // RF_Content: radiob_txt
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u4Byte maskforPhySet= (u4Byte)(content&0xE000);
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odm_ConfigRFReg_8192E(pDM_Odm, Addr, Data, ODM_RF_PATH_B, Addr|maskforPhySet);
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ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioB] %08X %08X\n", Addr, Data));
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}
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void
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odm_ConfigMAC_8192E(
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IN PDM_ODM_T pDM_Odm,
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IN u4Byte Addr,
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IN u1Byte Data
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)
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{
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ODM_Write1Byte(pDM_Odm, Addr, Data);
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ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigMACWithHeaderFile: [MAC_REG] %08X %08X\n", Addr, Data));
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}
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void
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odm_ConfigBB_AGC_8192E(
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IN PDM_ODM_T pDM_Odm,
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IN u4Byte Addr,
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IN u4Byte Bitmask,
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IN u4Byte Data
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)
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{
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ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data);
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// Add 1us delay between BB/RF register setting.
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ODM_delay_us(1);
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ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [AGC_TAB] %08X %08X\n", Addr, Data));
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}
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void
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odm_ConfigBB_PHY_REG_PG_8192E(
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IN PDM_ODM_T pDM_Odm,
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IN u4Byte Band,
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IN u4Byte RfPath,
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IN u4Byte TxNum,
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IN u4Byte Addr,
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IN u4Byte Bitmask,
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IN u4Byte Data
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)
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{
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if (Addr == 0xfe || Addr == 0xffe)
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#ifdef CONFIG_LONG_DELAY_ISSUE
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ODM_sleep_ms(50);
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#else
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ODM_delay_ms(50);
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#endif
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else
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{
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#if !(DM_ODM_SUPPORT_TYPE&ODM_AP)
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PHY_StoreTxPowerByRate(pDM_Odm->Adapter, Band, RfPath, TxNum, Addr, Bitmask, Data);
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#endif
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}
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ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X %08X\n", Addr, Bitmask, Data));
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}
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void
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odm_ConfigBB_PHY_8192E(
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IN PDM_ODM_T pDM_Odm,
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IN u4Byte Addr,
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IN u4Byte Bitmask,
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IN u4Byte Data
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)
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{
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if (Addr == 0xfe)
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#ifdef CONFIG_LONG_DELAY_ISSUE
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ODM_sleep_ms(50);
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#else
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ODM_delay_ms(50);
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#endif
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else if (Addr == 0xfd)
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ODM_delay_ms(5);
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else if (Addr == 0xfc)
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ODM_delay_ms(1);
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else if (Addr == 0xfb)
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ODM_delay_us(50);
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else if (Addr == 0xfa)
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ODM_delay_us(5);
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else if (Addr == 0xf9)
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ODM_delay_us(1);
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else
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{
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ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data);
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}
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// Add 1us delay between BB/RF register setting.
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ODM_delay_us(1);
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ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n", Addr, Data));
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}
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void
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odm_ConfigBB_TXPWR_LMT_8192E(
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IN PDM_ODM_T pDM_Odm,
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IN pu1Byte Regulation,
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IN pu1Byte Band,
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IN pu1Byte Bandwidth,
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IN pu1Byte RateSection,
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IN pu1Byte RfPath,
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IN pu1Byte Channel,
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IN pu1Byte PowerLimit
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)
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{
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#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
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PHY_SetTxPowerLimit(pDM_Odm, Regulation, Band,
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Bandwidth, RateSection, RfPath, Channel, PowerLimit);
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#elif (DM_ODM_SUPPORT_TYPE & (ODM_CE))
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PHY_SetTxPowerLimit(pDM_Odm->Adapter, Regulation, Band,
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Bandwidth, RateSection, RfPath, Channel, PowerLimit);
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#endif
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}
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#endif
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