mirror of
https://github.com/Mange/rtl8192eu-linux-driver
synced 2026-03-31 22:49:56 +00:00
Replace rtw_get_current_time() with jiffies
Port of c01fb49636b65ceea513c00966c58b8bdb095c8f
This commit is contained in:
@@ -76,7 +76,7 @@ s32 InitLLTTable8192E(PADAPTER padapter, u8 txpktbuf_bndy)
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value32 = rtw_read32(padapter, REG_AUTO_LLT);
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rtw_write32(padapter, REG_AUTO_LLT, value32 | BIT_AUTO_INIT_LLT);
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start = rtw_get_current_time();
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start = jiffies;
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while (((value32 = rtw_read32(padapter, REG_AUTO_LLT)) & BIT_AUTO_INIT_LLT)
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&& ((passing_time = rtw_get_passing_time_ms(start)) < 1000)
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)
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@@ -367,7 +367,7 @@ static s32 polling_fwdl_chksum(_adapter *adapter, u32 min_cnt, u32 timeout_ms)
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{
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s32 ret = _FAIL;
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u32 value32;
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systime start = rtw_get_current_time();
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systime start = jiffies;
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u32 cnt = 0;
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/* polling CheckSum report */
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@@ -398,7 +398,7 @@ static s32 _FWFreeToGo8192E(_adapter *adapter, u32 min_cnt, u32 timeout_ms)
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{
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s32 ret = _FAIL;
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u32 value32;
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systime start = rtw_get_current_time();
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systime start = jiffies;
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u32 cnt = 0;
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value32 = rtw_read32(adapter, REG_MCUFWDL);
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@@ -554,7 +554,7 @@ FirmwareDownload8192E(
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}
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_FWDownloadEnable_8192E(Adapter, _TRUE);
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fwdl_start_time = rtw_get_current_time();
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fwdl_start_time = jiffies;
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while (!RTW_CANNOT_IO(Adapter)
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&& (write_fw++ < 3 || rtw_get_passing_time_ms(fwdl_start_time) < 500)) {
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/* reset FWDL chksum */
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@@ -3963,7 +3963,7 @@ u8 SetHwReg8192E(PADAPTER Adapter, u8 variable, u8 *val)
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u16 val16;
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u32 reg_200 = 0, reg_204 = 0, reg_214 = 0;
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u32 init_reg_200 = 0, init_reg_204 = 0, init_reg_214 = 0;
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systime start = rtw_get_current_time();
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systime start = jiffies;
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u32 pass_ms;
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int i = 0;
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@@ -38,7 +38,7 @@ void rtl8192e_sreset_xmit_status_check(_adapter *padapter)
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/* total xmit irp = 4 */
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/* RTW_INFO("==>%s free_xmitbuf_cnt(%d),txirp_cnt(%d)\n",__FUNCTION__,pxmitpriv->free_xmitbuf_cnt,pxmitpriv->txirp_cnt); */
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/* if(pxmitpriv->txirp_cnt == NR_XMITBUFF+1) */
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current_time = rtw_get_current_time();
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current_time = jiffies;
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if (0 == pxmitpriv->free_xmitbuf_cnt || 0 == pxmitpriv->free_xmit_extbuf_cnt) {
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@@ -693,7 +693,7 @@ u32 rtl8192eu_hal_init(PADAPTER Adapter)
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rt_rf_power_state eRfPowerStateToSet;
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systime init_start_time = rtw_get_current_time();
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systime init_start_time = jiffies;
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#ifdef DBG_HAL_INIT_PROFILING
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@@ -763,7 +763,7 @@ u32 rtl8192eu_hal_init(PADAPTER Adapter)
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for (hal_init_profiling_i = 0; hal_init_profiling_i < HAL_INIT_STAGES_NUM; hal_init_profiling_i++)
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hal_init_stages_timestamp[hal_init_profiling_i] = 0;
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#define HAL_INIT_PROFILE_TAG(stage) do { hal_init_stages_timestamp[(stage)] = rtw_get_current_time(); } while (0)
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#define HAL_INIT_PROFILE_TAG(stage) do { hal_init_stages_timestamp[(stage)] = jiffies; } while (0)
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#else
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#define HAL_INIT_PROFILE_TAG(stage) do {} while (0)
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#endif /* DBG_HAL_INIT_PROFILING */
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@@ -1123,7 +1123,7 @@ exit:
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RTW_INFO("%s in %dms\n", __FUNCTION__, rtw_get_passing_time_ms(init_start_time));
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#ifdef DBG_HAL_INIT_PROFILING
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hal_init_stages_timestamp[HAL_INIT_STAGES_END] = rtw_get_current_time();
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hal_init_stages_timestamp[HAL_INIT_STAGES_END] = jiffies;
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for (hal_init_profiling_i = 0; hal_init_profiling_i < HAL_INIT_STAGES_NUM - 1; hal_init_profiling_i++) {
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RTW_INFO("DBG_HAL_INIT_PROFILING: %35s, %u, %5u, %5u\n"
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@@ -50,7 +50,7 @@ void interrupt_handler_8192eu(_adapter *padapter, u16 pkt_len, u8 *pbuf)
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if (pHalData->IntArray[0] & IMR_BCNDMAINT0_88E) {
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struct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info;
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u32 last_time = pchsw_info->cur_time;
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pchsw_info->cur_time = rtw_systime_to_ms(rtw_get_current_time());
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pchsw_info->cur_time = rtw_systime_to_ms(jiffies);
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if ((atomic_read(&pchsw_info->chsw_on) == _TRUE) &&
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/* Sometimes we receive multiple interrupts in very little time period, use the follow condition test to filter */
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(pchsw_info->cur_time - last_time > padapter->mlmeextpriv.mlmext_info.bcn_interval - 5) &&
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