mirror of
https://github.com/Mange/rtl8192eu-linux-driver
synced 2024-11-25 06:55:05 +00:00
remove HAL_{BB,MAC,RF,FW}_ENABLE macros
remove HAL_{BB,MAC,RF,FW}_ENABLE macros. They are used to turn on/off by hand some core capabilities we want to be always 'on'. port bb1c456d7f88b60b28b9f51e28031fc67cdb8d7b port b4e1882d750facd317ac2572d6bf36a05b0b0c36 Link: https://lore.kernel.org/r/04248acbd22f9be30d21891926e134490b34036a.1623756906.git.fabioaiuto83@gmail.com
This commit is contained in:
parent
27246f4eb5
commit
539ec6269e
@ -760,9 +760,6 @@ void halrf_segment_iqk_trigger(void *dm_void, boolean clear,
|
||||
return;
|
||||
#endif
|
||||
|
||||
#if DISABLE_BB_RF
|
||||
return;
|
||||
#endif
|
||||
if (iqk_info->rfk_forbidden)
|
||||
return;
|
||||
|
||||
@ -1330,10 +1327,6 @@ void halrf_iqk_trigger(void *dm_void, boolean is_recovery)
|
||||
if (!(rf->rf_supportability & HAL_RF_IQK))
|
||||
return;
|
||||
|
||||
#if DISABLE_BB_RF
|
||||
return;
|
||||
#endif
|
||||
|
||||
if (iqk_info->rfk_forbidden)
|
||||
return;
|
||||
|
||||
@ -1483,9 +1476,6 @@ void halrf_lck_trigger(void *dm_void)
|
||||
if (!(rf->rf_supportability & HAL_RF_LCK))
|
||||
return;
|
||||
|
||||
#if DISABLE_BB_RF
|
||||
return;
|
||||
#endif
|
||||
if (iqk_info->rfk_forbidden)
|
||||
return;
|
||||
while (*dm->is_scan_in_process) {
|
||||
|
@ -1754,10 +1754,6 @@ void phy_set_rf_path_switch_8192e(
|
||||
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
|
||||
#endif
|
||||
|
||||
#ifdef DISABLE_BB_RF
|
||||
return;
|
||||
#endif
|
||||
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
if (IS_92C_SERIAL(hal_data->version_id))
|
||||
_phy_set_rf_path_switch_8192e(adapter, is_main, true);
|
||||
|
@ -1961,10 +1961,6 @@ void phy_set_rf_path_switch_8192e(
|
||||
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
|
||||
#endif
|
||||
|
||||
#if DISABLE_BB_RF
|
||||
return;
|
||||
#endif
|
||||
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
_phy_set_rf_path_switch_8192e(dm, is_main, true);
|
||||
@ -2012,9 +2008,6 @@ boolean phy_query_rf_path_switch_8192e(
|
||||
{
|
||||
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
|
||||
|
||||
#if DISABLE_BB_RF
|
||||
return true;
|
||||
#endif
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
if (IS_2T2R(hal_data->version_id))
|
||||
return _phy_query_rf_path_switch_8192e(adapter, true);
|
||||
|
@ -2070,10 +2070,6 @@ void phy_set_rf_path_switch_8192e(
|
||||
/* HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); */
|
||||
#endif
|
||||
|
||||
#if DISABLE_BB_RF
|
||||
return;
|
||||
#endif
|
||||
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
|
||||
_phy_set_rf_path_switch_8192e(adapter, is_main, true);
|
||||
@ -2123,9 +2119,6 @@ boolean phy_query_rf_path_switch_8192e(
|
||||
{
|
||||
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
|
||||
|
||||
#if DISABLE_BB_RF
|
||||
return true;
|
||||
#endif
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
if (IS_2T2R(hal_data->VersionID))
|
||||
return _phy_query_rf_path_switch_8192e(adapter, true);
|
||||
|
@ -3633,10 +3633,6 @@ VOID _InitBeaconMaxError_8192E(
|
||||
/* Set CCK and OFDM Block "ON" */
|
||||
void _BBTurnOnBlock_8192E(PADAPTER padapter)
|
||||
{
|
||||
#if (DISABLE_BB_RF)
|
||||
return;
|
||||
#endif
|
||||
|
||||
phy_set_bb_reg(padapter, rFPGA0_RFMOD, bCCKEn, 0x1);
|
||||
phy_set_bb_reg(padapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
|
||||
}
|
||||
@ -3647,11 +3643,7 @@ hal_ReadRFType_8192E(
|
||||
{
|
||||
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
|
||||
|
||||
#if DISABLE_BB_RF
|
||||
pHalData->rf_chip = RF_PSEUDO_11N;
|
||||
#else
|
||||
pHalData->rf_chip = RF_6052;
|
||||
#endif
|
||||
|
||||
pHalData->BandSet = BAND_ON_2_4G;
|
||||
|
||||
|
@ -51,10 +51,6 @@ PHY_QueryBBReg8192E(
|
||||
{
|
||||
u32 ReturnValue = 0, OriginalValue, BitShift;
|
||||
|
||||
#if (DISABLE_BB_RF == 1)
|
||||
return 0;
|
||||
#endif
|
||||
|
||||
/* RTW_INFO("--->PHY_QueryBBReg8812(): RegAddr(%#x), BitMask(%#x)\n", RegAddr, BitMask); */
|
||||
|
||||
|
||||
@ -77,10 +73,6 @@ PHY_SetBBReg8192E(
|
||||
{
|
||||
u4Byte OriginalValue, BitShift;
|
||||
|
||||
#if (DISABLE_BB_RF == 1)
|
||||
return;
|
||||
#endif
|
||||
|
||||
if (BitMask != bMaskDWord) {
|
||||
/* if not "double word" write */
|
||||
OriginalValue = rtw_read32(Adapter, RegAddr);
|
||||
@ -230,10 +222,6 @@ PHY_QueryRFReg8192E(
|
||||
{
|
||||
u32 Original_Value, Readback_Value, BitShift;
|
||||
|
||||
#if (DISABLE_BB_RF == 1)
|
||||
return 0;
|
||||
#endif
|
||||
|
||||
Original_Value = phy_RFSerialRead(Adapter, eRFPath, RegAddr);
|
||||
|
||||
BitShift = PHY_CalculateBitShift(BitMask);
|
||||
@ -252,9 +240,6 @@ PHY_SetRFReg8192E(
|
||||
)
|
||||
{
|
||||
u32 Original_Value, BitShift;
|
||||
#if (DISABLE_BB_RF == 1)
|
||||
return;
|
||||
#endif
|
||||
|
||||
if (BitMask == 0)
|
||||
return;
|
||||
|
@ -870,21 +870,17 @@ u32 rtl8192eu_hal_init(PADAPTER Adapter)
|
||||
pHalData->current_channel = 6;/* default set to 6 */
|
||||
|
||||
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MAC);
|
||||
#if (HAL_MAC_ENABLE == 1)
|
||||
status = PHY_MACConfig8192E(Adapter);
|
||||
if (status == _FAIL)
|
||||
goto exit;
|
||||
#endif
|
||||
|
||||
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BB);
|
||||
#if (HAL_BB_ENABLE == 1)
|
||||
status = PHY_BBConfig8192E(Adapter);
|
||||
if (status == _FAIL)
|
||||
goto exit;
|
||||
#endif
|
||||
|
||||
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_RF);
|
||||
#if (HAL_RF_ENABLE == 1)
|
||||
|
||||
status = PHY_RFConfig8192E(Adapter);
|
||||
if (status == _FAIL)
|
||||
goto exit;
|
||||
@ -975,7 +971,6 @@ u32 rtl8192eu_hal_init(PADAPTER Adapter)
|
||||
#endif /* CONFIG_RTW_LED */
|
||||
|
||||
_BBTurnOnBlock_8192E(Adapter);
|
||||
#endif
|
||||
|
||||
/* */
|
||||
/* Joseph Note: Keep RfRegChnlVal for later use. */
|
||||
|
@ -237,8 +237,6 @@
|
||||
|
||||
#define ENABLE_USB_DROP_INCORRECT_OUT
|
||||
|
||||
|
||||
#define DISABLE_BB_RF 0
|
||||
#define RTW_CONFIG_RFREG18_WA
|
||||
/* #define RTL8191C_FPGA_NETWORKTYPE_ADHOC 0 */
|
||||
|
||||
|
@ -15,19 +15,6 @@
|
||||
#ifndef __HAL_PHY_H__
|
||||
#define __HAL_PHY_H__
|
||||
|
||||
|
||||
#if DISABLE_BB_RF
|
||||
#define HAL_FW_ENABLE 0
|
||||
#define HAL_MAC_ENABLE 0
|
||||
#define HAL_BB_ENABLE 0
|
||||
#define HAL_RF_ENABLE 0
|
||||
#else /* FPGA_PHY and ASIC */
|
||||
#define HAL_FW_ENABLE 1
|
||||
#define HAL_MAC_ENABLE 1
|
||||
#define HAL_BB_ENABLE 1
|
||||
#define HAL_RF_ENABLE 1
|
||||
#endif
|
||||
|
||||
#define RF6052_MAX_TX_PWR 0x3F
|
||||
#define RF6052_MAX_REG_88E 0xFF
|
||||
#define RF6052_MAX_REG_92C 0x7F
|
||||
|
Loading…
Reference in New Issue
Block a user