mirror of
https://github.com/Mange/rtl8192eu-linux-driver
synced 2025-12-10 00:04:17 +00:00
Add version v5.6.4
This commit is contained in:
Carlos Garces
@@ -1,6 +1,6 @@
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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* Copyright(c) 2007 - 2017 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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@@ -11,25 +11,21 @@
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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*******************************************************************************/
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*****************************************************************************/
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#ifndef __RTL8188F_SPEC_H__
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#define __RTL8188F_SPEC_H__
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#include <drv_conf.h>
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#define HAL_NAV_UPPER_UNIT_8188F 128 // micro-second
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#define HAL_NAV_UPPER_UNIT_8188F 128 /* micro-second */
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//-----------------------------------------------------
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//
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// 0x0000h ~ 0x00FFh System Configuration
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//
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//-----------------------------------------------------
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#define REG_RSV_CTRL_8188F 0x001C // 3 Byte
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/* -----------------------------------------------------
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*
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* 0x0000h ~ 0x00FFh System Configuration
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*
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* ----------------------------------------------------- */
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#define REG_RSV_CTRL_8188F 0x001C /* 3 Byte */
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#define REG_BT_WIFI_ANTENNA_SWITCH_8188F 0x0038
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#define REG_HSISR_8188F 0x005c
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#define REG_PAD_CTRL1_8188F 0x0064
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@@ -44,11 +40,11 @@
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#define REG_HISR1_8188F 0x00BC
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#define REG_PMC_DBG_CTRL2_8188F 0x00CC
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//-----------------------------------------------------
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//
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// 0x0100h ~ 0x01FFh MACTOP General Configuration
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//
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//-----------------------------------------------------
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/* -----------------------------------------------------
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*
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* 0x0100h ~ 0x01FFh MACTOP General Configuration
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*
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* ----------------------------------------------------- */
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#define REG_C2HEVT_CMD_ID_8188F 0x01A0
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#define REG_C2HEVT_CMD_LEN_8188F 0x01AE
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#define REG_WOWLAN_WAKE_REASON 0x01C7
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@@ -60,52 +56,52 @@
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#define REG_HMEBOX_EXT2_8188F 0x01F8
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#define REG_HMEBOX_EXT3_8188F 0x01FC
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//-----------------------------------------------------
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//
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// 0x0200h ~ 0x027Fh TXDMA Configuration
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//
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//-----------------------------------------------------
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/* -----------------------------------------------------
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*
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* 0x0200h ~ 0x027Fh TXDMA Configuration
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*
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* ----------------------------------------------------- */
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//-----------------------------------------------------
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//
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// 0x0280h ~ 0x02FFh RXDMA Configuration
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//
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//-----------------------------------------------------
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#define REG_RXDMA_CONTROL_8188F 0x0286 // Control the RX DMA.
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/* -----------------------------------------------------
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*
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* 0x0280h ~ 0x02FFh RXDMA Configuration
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*
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* ----------------------------------------------------- */
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#define REG_RXDMA_CONTROL_8188F 0x0286 /* Control the RX DMA. */
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#define REG_RXDMA_MODE_CTRL_8188F 0x0290
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//-----------------------------------------------------
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//
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// 0x0300h ~ 0x03FFh PCIe
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//
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//-----------------------------------------------------
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/* -----------------------------------------------------
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*
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* 0x0300h ~ 0x03FFh PCIe
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*
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* ----------------------------------------------------- */
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#define REG_PCIE_CTRL_REG_8188F 0x0300
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#define REG_INT_MIG_8188F 0x0304 // Interrupt Migration
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#define REG_BCNQ_DESA_8188F 0x0308 // TX Beacon Descriptor Address
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#define REG_HQ_DESA_8188F 0x0310 // TX High Queue Descriptor Address
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#define REG_MGQ_DESA_8188F 0x0318 // TX Manage Queue Descriptor Address
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#define REG_VOQ_DESA_8188F 0x0320 // TX VO Queue Descriptor Address
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#define REG_VIQ_DESA_8188F 0x0328 // TX VI Queue Descriptor Address
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#define REG_BEQ_DESA_8188F 0x0330 // TX BE Queue Descriptor Address
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#define REG_BKQ_DESA_8188F 0x0338 // TX BK Queue Descriptor Address
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#define REG_RX_DESA_8188F 0x0340 // RX Queue Descriptor Address
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#define REG_DBI_WDATA_8188F 0x0348 // DBI Write Data
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#define REG_DBI_RDATA_8188F 0x034C // DBI Read Data
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#define REG_DBI_ADDR_8188F 0x0350 // DBI Address
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#define REG_DBI_FLAG_8188F 0x0352 // DBI Read/Write Flag
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#define REG_MDIO_WDATA_8188F 0x0354 // MDIO for Write PCIE PHY
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#define REG_MDIO_RDATA_8188F 0x0356 // MDIO for Reads PCIE PHY
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#define REG_MDIO_CTL_8188F 0x0358 // MDIO for Control
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#define REG_DBG_SEL_8188F 0x0360 // Debug Selection Register
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#define REG_PCIE_HRPWM_8188F 0x0361 //PCIe RPWM
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#define REG_PCIE_HCPWM_8188F 0x0363 //PCIe CPWM
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#define REG_PCIE_MULTIFET_CTRL_8188F 0x036A //PCIE Multi-Fethc Control
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#define REG_INT_MIG_8188F 0x0304 /* Interrupt Migration */
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#define REG_BCNQ_DESA_8188F 0x0308 /* TX Beacon Descriptor Address */
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#define REG_HQ_DESA_8188F 0x0310 /* TX High Queue Descriptor Address */
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#define REG_MGQ_DESA_8188F 0x0318 /* TX Manage Queue Descriptor Address */
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#define REG_VOQ_DESA_8188F 0x0320 /* TX VO Queue Descriptor Address */
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#define REG_VIQ_DESA_8188F 0x0328 /* TX VI Queue Descriptor Address */
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#define REG_BEQ_DESA_8188F 0x0330 /* TX BE Queue Descriptor Address */
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#define REG_BKQ_DESA_8188F 0x0338 /* TX BK Queue Descriptor Address */
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#define REG_RX_DESA_8188F 0x0340 /* RX Queue Descriptor Address */
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#define REG_DBI_WDATA_8188F 0x0348 /* DBI Write Data */
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#define REG_DBI_RDATA_8188F 0x034C /* DBI Read Data */
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#define REG_DBI_ADDR_8188F 0x0350 /* DBI Address */
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#define REG_DBI_FLAG_8188F 0x0352 /* DBI Read/Write Flag */
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#define REG_MDIO_WDATA_8188F 0x0354 /* MDIO for Write PCIE PHY */
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#define REG_MDIO_RDATA_8188F 0x0356 /* MDIO for Reads PCIE PHY */
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#define REG_MDIO_CTL_8188F 0x0358 /* MDIO for Control */
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#define REG_DBG_SEL_8188F 0x0360 /* Debug Selection Register */
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#define REG_PCIE_HRPWM_8188F 0x0361 /* PCIe RPWM */
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#define REG_PCIE_HCPWM_8188F 0x0363 /* PCIe CPWM */
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#define REG_PCIE_MULTIFET_CTRL_8188F 0x036A /* PCIE Multi-Fethc Control */
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//-----------------------------------------------------
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//
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// 0x0400h ~ 0x047Fh Protocol Configuration
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//
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//-----------------------------------------------------
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/* -----------------------------------------------------
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*
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* 0x0400h ~ 0x047Fh Protocol Configuration
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*
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* ----------------------------------------------------- */
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#define REG_TXPKTBUF_BCNQ_BDNY_8188F 0x0424
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#define REG_TXPKTBUF_MGQ_BDNY_8188F 0x0425
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#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8188F 0x045D
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@@ -115,35 +111,35 @@
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#endif
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#define REG_AMPDU_BURST_MODE_8188F 0x04BC
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//-----------------------------------------------------
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//
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// 0x0500h ~ 0x05FFh EDCA Configuration
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//
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//-----------------------------------------------------
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/* -----------------------------------------------------
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*
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* 0x0500h ~ 0x05FFh EDCA Configuration
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*
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* ----------------------------------------------------- */
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#define REG_SECONDARY_CCA_CTRL_8188F 0x0577
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//-----------------------------------------------------
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//
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// 0x0600h ~ 0x07FFh WMAC Configuration
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//
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//-----------------------------------------------------
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/* -----------------------------------------------------
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*
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* 0x0600h ~ 0x07FFh WMAC Configuration
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*
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* ----------------------------------------------------- */
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//============================================================
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// SDIO Bus Specification
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//============================================================
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/* ************************************************************
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* SDIO Bus Specification
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* ************************************************************ */
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//-----------------------------------------------------
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// SDIO CMD Address Mapping
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//-----------------------------------------------------
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/* -----------------------------------------------------
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* SDIO CMD Address Mapping
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* ----------------------------------------------------- */
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//-----------------------------------------------------
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// I/O bus domain (Host)
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//-----------------------------------------------------
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/* -----------------------------------------------------
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* I/O bus domain (Host)
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* ----------------------------------------------------- */
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//-----------------------------------------------------
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// SDIO register
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//-----------------------------------------------------
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/* -----------------------------------------------------
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* SDIO register
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* ----------------------------------------------------- */
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#define SDIO_REG_HIQ_FREEPG_8188F 0x0020
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#define SDIO_REG_MID_FREEPG_8188F 0x0022
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#define SDIO_REG_LOW_FREEPG_8188F 0x0024
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@@ -154,48 +150,36 @@
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#define SDIO_REG_HCPWM1_8188F 0x0038
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/* indirect access */
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#define SDIO_REG_INDIRECT_REG_CFG_8188F 0x40
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#define SET_INDIRECT_REG_ADDR(_cmd, _addr) SET_BITS_TO_LE_2BYTE(((u8 *)(_cmd)) + 0, 0, 16, (_addr))
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#define SET_INDIRECT_REG_SIZE_1BYTE(_cmd) SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 0, 2, 0)
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#define SET_INDIRECT_REG_SIZE_2BYTE(_cmd) SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 0, 2, 1)
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#define SET_INDIRECT_REG_SIZE_4BYTE(_cmd) SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 0, 2, 2)
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#define SET_INDIRECT_REG_WRITE(_cmd) SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 2, 1, 1)
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#define SET_INDIRECT_REG_READ(_cmd) SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 3, 1, 1)
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#define GET_INDIRECT_REG_RDY(_cmd) LE_BITS_TO_1BYTE(((u8 *)(_cmd)) + 2, 4, 1)
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/* ****************************************************************************
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* 8188 Regsiter Bit and Content definition
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* **************************************************************************** */
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#define SDIO_REG_INDIRECT_REG_DATA_8188F 0x44
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//============================================================================
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// 8188 Regsiter Bit and Content definition
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//============================================================================
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//2 HSISR
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// interrupt mask which needs to clear
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/* 2 HSISR
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* interrupt mask which needs to clear */
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#define MASK_HSISR_CLEAR (HSISR_GPIO12_0_INT |\
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HSISR_SPS_OCP_INT |\
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HSISR_RON_INT |\
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HSISR_PDNINT |\
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HSISR_GPIO9_INT)
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HSISR_SPS_OCP_INT |\
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HSISR_RON_INT |\
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HSISR_PDNINT |\
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HSISR_GPIO9_INT)
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//-----------------------------------------------------
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//
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// 0x0100h ~ 0x01FFh MACTOP General Configuration
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//
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//-----------------------------------------------------
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/* -----------------------------------------------------
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*
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* 0x0100h ~ 0x01FFh MACTOP General Configuration
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*
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* ----------------------------------------------------- */
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//-----------------------------------------------------
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//
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// 0x0200h ~ 0x027Fh TXDMA Configuration
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//
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//-----------------------------------------------------
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/* -----------------------------------------------------
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*
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* 0x0200h ~ 0x027Fh TXDMA Configuration
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*
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* ----------------------------------------------------- */
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//-----------------------------------------------------
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//
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// 0x0280h ~ 0x02FFh RXDMA Configuration
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//
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//-----------------------------------------------------
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/* -----------------------------------------------------
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*
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* 0x0280h ~ 0x02FFh RXDMA Configuration
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*
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* ----------------------------------------------------- */
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#define BIT_USB_RXDMA_AGG_EN BIT(31)
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#define RXDMA_AGG_MODE_EN BIT(1)
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@@ -205,99 +189,87 @@
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#define RW_RELEASE_EN BIT(18)
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#endif
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//-----------------------------------------------------
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//
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// 0x0400h ~ 0x047Fh Protocol Configuration
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//
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//-----------------------------------------------------
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/* -----------------------------------------------------
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*
|
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* 0x0400h ~ 0x047Fh Protocol Configuration
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*
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* ----------------------------------------------------- */
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//----------------------------------------------------------------------------
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// 8188F REG_CCK_CHECK (offset 0x454)
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//----------------------------------------------------------------------------
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#define BIT_BCN_PORT_SEL BIT5
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/* ----------------------------------------------------------------------------
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* 8188F REG_CCK_CHECK (offset 0x454)
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* ---------------------------------------------------------------------------- */
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#define BIT_BCN_PORT_SEL BIT(5)
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//-----------------------------------------------------
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//
|
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// 0x0500h ~ 0x05FFh EDCA Configuration
|
||||
//
|
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//-----------------------------------------------------
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0500h ~ 0x05FFh EDCA Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
|
||||
//-----------------------------------------------------
|
||||
//
|
||||
// 0x0600h ~ 0x07FFh WMAC Configuration
|
||||
//
|
||||
//-----------------------------------------------------
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0600h ~ 0x07FFh WMAC Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
|
||||
//----------------------------------------------------------------------------
|
||||
// 8195 IMR/ISR bits (offset 0xB0, 8bits)
|
||||
//----------------------------------------------------------------------------
|
||||
/* ----------------------------------------------------------------------------
|
||||
* 8195 IMR/ISR bits (offset 0xB0, 8bits)
|
||||
* ---------------------------------------------------------------------------- */
|
||||
#define IMR_DISABLED_8188F 0
|
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// IMR DW0(0x00B0-00B3) Bit 0-31
|
||||
#define IMR_TIMER2_8188F BIT31 // Timeout interrupt 2
|
||||
#define IMR_TIMER1_8188F BIT30 // Timeout interrupt 1
|
||||
#define IMR_PSTIMEOUT_8188F BIT29 // Power Save Time Out Interrupt
|
||||
#define IMR_GTINT4_8188F BIT28 // When GTIMER4 expires, this bit is set to 1
|
||||
#define IMR_GTINT3_8188F BIT27 // When GTIMER3 expires, this bit is set to 1
|
||||
#define IMR_TXBCN0ERR_8188F BIT26 // Transmit Beacon0 Error
|
||||
#define IMR_TXBCN0OK_8188F BIT25 // Transmit Beacon0 OK
|
||||
#define IMR_TSF_BIT32_TOGGLE_8188F BIT24 // TSF Timer BIT32 toggle indication interrupt
|
||||
#define IMR_BCNDMAINT0_8188F BIT20 // Beacon DMA Interrupt 0
|
||||
#define IMR_BCNDERR0_8188F BIT16 // Beacon Queue DMA OK0
|
||||
#define IMR_HSISR_IND_ON_INT_8188F BIT15 // HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1)
|
||||
#define IMR_BCNDMAINT_E_8188F BIT14 // Beacon DMA Interrupt Extension for Win7
|
||||
#define IMR_ATIMEND_8188F BIT12 // CTWidnow End or ATIM Window End
|
||||
#define IMR_C2HCMD_8188F BIT10 // CPU to Host Command INT Status, Write 1 clear
|
||||
#define IMR_CPWM2_8188F BIT9 // CPU power Mode exchange INT Status, Write 1 clear
|
||||
#define IMR_CPWM_8188F BIT8 // CPU power Mode exchange INT Status, Write 1 clear
|
||||
#define IMR_HIGHDOK_8188F BIT7 // High Queue DMA OK
|
||||
#define IMR_MGNTDOK_8188F BIT6 // Management Queue DMA OK
|
||||
#define IMR_BKDOK_8188F BIT5 // AC_BK DMA OK
|
||||
#define IMR_BEDOK_8188F BIT4 // AC_BE DMA OK
|
||||
#define IMR_VIDOK_8188F BIT3 // AC_VI DMA OK
|
||||
#define IMR_VODOK_8188F BIT2 // AC_VO DMA OK
|
||||
#define IMR_RDU_8188F BIT1 // Rx Descriptor Unavailable
|
||||
#define IMR_ROK_8188F BIT0 // Receive DMA OK
|
||||
/* IMR DW0(0x00B0-00B3) Bit 0-31 */
|
||||
#define IMR_TIMER2_8188F BIT(31) /* Timeout interrupt 2 */
|
||||
#define IMR_TIMER1_8188F BIT(30) /* Timeout interrupt 1 */
|
||||
#define IMR_PSTIMEOUT_8188F BIT(29) /* Power Save Time Out Interrupt */
|
||||
#define IMR_GTINT4_8188F BIT(28) /* When GTIMER4 expires, this bit is set to 1 */
|
||||
#define IMR_GTINT3_8188F BIT(27) /* When GTIMER3 expires, this bit is set to 1 */
|
||||
#define IMR_TXBCN0ERR_8188F BIT(26) /* Transmit Beacon0 Error */
|
||||
#define IMR_TXBCN0OK_8188F BIT(25) /* Transmit Beacon0 OK */
|
||||
#define IMR_TSF_BIT32_TOGGLE_8188F BIT(24) /* TSF Timer BIT(32) toggle indication interrupt */
|
||||
#define IMR_BCNDMAINT0_8188F BIT(20) /* Beacon DMA Interrupt 0 */
|
||||
#define IMR_BCNDERR0_8188F BIT(16) /* Beacon Queue DMA OK0 */
|
||||
#define IMR_HSISR_IND_ON_INT_8188F BIT(15) /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */
|
||||
#define IMR_BCNDMAINT_E_8188F BIT(14) /* Beacon DMA Interrupt Extension for Win7 */
|
||||
#define IMR_ATIMEND_8188F BIT(12) /* CTWidnow End or ATIM Window End */
|
||||
#define IMR_C2HCMD_8188F BIT(10) /* CPU to Host Command INT Status, Write 1 clear */
|
||||
#define IMR_CPWM2_8188F BIT(9) /* CPU power Mode exchange INT Status, Write 1 clear */
|
||||
#define IMR_CPWM_8188F BIT(8) /* CPU power Mode exchange INT Status, Write 1 clear */
|
||||
#define IMR_HIGHDOK_8188F BIT(7) /* High Queue DMA OK */
|
||||
#define IMR_MGNTDOK_8188F BIT(6) /* Management Queue DMA OK */
|
||||
#define IMR_BKDOK_8188F BIT(5) /* AC_BK DMA OK */
|
||||
#define IMR_BEDOK_8188F BIT(4) /* AC_BE DMA OK */
|
||||
#define IMR_VIDOK_8188F BIT(3) /* AC_VI DMA OK */
|
||||
#define IMR_VODOK_8188F BIT(2) /* AC_VO DMA OK */
|
||||
#define IMR_RDU_8188F BIT(1) /* Rx Descriptor Unavailable */
|
||||
#define IMR_ROK_8188F BIT(0) /* Receive DMA OK */
|
||||
|
||||
// IMR DW1(0x00B4-00B7) Bit 0-31
|
||||
#define IMR_BCNDMAINT7_8188F BIT27 // Beacon DMA Interrupt 7
|
||||
#define IMR_BCNDMAINT6_8188F BIT26 // Beacon DMA Interrupt 6
|
||||
#define IMR_BCNDMAINT5_8188F BIT25 // Beacon DMA Interrupt 5
|
||||
#define IMR_BCNDMAINT4_8188F BIT24 // Beacon DMA Interrupt 4
|
||||
#define IMR_BCNDMAINT3_8188F BIT23 // Beacon DMA Interrupt 3
|
||||
#define IMR_BCNDMAINT2_8188F BIT22 // Beacon DMA Interrupt 2
|
||||
#define IMR_BCNDMAINT1_8188F BIT21 // Beacon DMA Interrupt 1
|
||||
#define IMR_BCNDOK7_8188F BIT20 // Beacon Queue DMA OK Interrup 7
|
||||
#define IMR_BCNDOK6_8188F BIT19 // Beacon Queue DMA OK Interrup 6
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#define IMR_BCNDOK5_8188F BIT18 // Beacon Queue DMA OK Interrup 5
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#define IMR_BCNDOK4_8188F BIT17 // Beacon Queue DMA OK Interrup 4
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#define IMR_BCNDOK3_8188F BIT16 // Beacon Queue DMA OK Interrup 3
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#define IMR_BCNDOK2_8188F BIT15 // Beacon Queue DMA OK Interrup 2
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#define IMR_BCNDOK1_8188F BIT14 // Beacon Queue DMA OK Interrup 1
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#define IMR_ATIMEND_E_8188F BIT13 // ATIM Window End Extension for Win7
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#define IMR_TXERR_8188F BIT11 // Tx Error Flag Interrupt Status, write 1 clear.
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#define IMR_RXERR_8188F BIT10 // Rx Error Flag INT Status, Write 1 clear
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#define IMR_TXFOVW_8188F BIT9 // Transmit FIFO Overflow
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#define IMR_RXFOVW_8188F BIT8 // Receive FIFO Overflow
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/* IMR DW1(0x00B4-00B7) Bit 0-31 */
|
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#define IMR_BCNDMAINT7_8188F BIT(27) /* Beacon DMA Interrupt 7 */
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#define IMR_BCNDMAINT6_8188F BIT(26) /* Beacon DMA Interrupt 6 */
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#define IMR_BCNDMAINT5_8188F BIT(25) /* Beacon DMA Interrupt 5 */
|
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#define IMR_BCNDMAINT4_8188F BIT(24) /* Beacon DMA Interrupt 4 */
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#define IMR_BCNDMAINT3_8188F BIT(23) /* Beacon DMA Interrupt 3 */
|
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#define IMR_BCNDMAINT2_8188F BIT(22) /* Beacon DMA Interrupt 2 */
|
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#define IMR_BCNDMAINT1_8188F BIT(21) /* Beacon DMA Interrupt 1 */
|
||||
#define IMR_BCNDOK7_8188F BIT(20) /* Beacon Queue DMA OK Interrupt 7 */
|
||||
#define IMR_BCNDOK6_8188F BIT(19) /* Beacon Queue DMA OK Interrupt 6 */
|
||||
#define IMR_BCNDOK5_8188F BIT(18) /* Beacon Queue DMA OK Interrupt 5 */
|
||||
#define IMR_BCNDOK4_8188F BIT(17) /* Beacon Queue DMA OK Interrupt 4 */
|
||||
#define IMR_BCNDOK3_8188F BIT(16) /* Beacon Queue DMA OK Interrupt 3 */
|
||||
#define IMR_BCNDOK2_8188F BIT(15) /* Beacon Queue DMA OK Interrupt 2 */
|
||||
#define IMR_BCNDOK1_8188F BIT(14) /* Beacon Queue DMA OK Interrupt 1 */
|
||||
#define IMR_ATIMEND_E_8188F BIT(13) /* ATIM Window End Extension for Win7 */
|
||||
#define IMR_TXERR_8188F BIT(11) /* Tx Error Flag Interrupt Status, write 1 clear. */
|
||||
#define IMR_RXERR_8188F BIT(10) /* Rx Error Flag INT Status, Write 1 clear */
|
||||
#define IMR_TXFOVW_8188F BIT(9) /* Transmit FIFO Overflow */
|
||||
#define IMR_RXFOVW_8188F BIT(8) /* Receive FIFO Overflow */
|
||||
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
//#define IMR_RX_MASK (IMR_ROK_8188F|IMR_RDU_8188F|IMR_RXFOVW_8188F)
|
||||
#define IMR_TX_MASK (IMR_VODOK_8188F|IMR_VIDOK_8188F|IMR_BEDOK_8188F|IMR_BKDOK_8188F|IMR_MGNTDOK_8188F|IMR_HIGHDOK_8188F)
|
||||
/* #define IMR_RX_MASK (IMR_ROK_8188F|IMR_RDU_8188F|IMR_RXFOVW_8188F) */
|
||||
#define IMR_TX_MASK (IMR_VODOK_8188F | IMR_VIDOK_8188F | IMR_BEDOK_8188F | IMR_BKDOK_8188F | IMR_MGNTDOK_8188F | IMR_HIGHDOK_8188F)
|
||||
|
||||
#define RT_BCN_INT_MASKS (IMR_BCNDMAINT0_8188F | IMR_TXBCN0OK_8188F | IMR_TXBCN0ERR_8188F | IMR_BCNDERR0_8188F)
|
||||
|
||||
#define RT_AC_INT_MASKS (IMR_VIDOK_8188F | IMR_VODOK_8188F | IMR_BEDOK_8188F|IMR_BKDOK_8188F)
|
||||
#define RT_AC_INT_MASKS (IMR_VIDOK_8188F | IMR_VODOK_8188F | IMR_BEDOK_8188F | IMR_BKDOK_8188F)
|
||||
#endif
|
||||
|
||||
//========================================================
|
||||
// General definitions
|
||||
//========================================================
|
||||
|
||||
#define MACID_NUM_8188F 16
|
||||
#define SEC_CAM_ENT_NUM_8188F 16
|
||||
#define NSS_NUM_8188F 1
|
||||
#define BAND_CAP_8188F (BAND_CAP_2G)
|
||||
#define BW_CAP_8188F (BW_CAP_20M | BW_CAP_40M)
|
||||
#define PROTO_CAP_8188F (PROTO_CAP_11B|PROTO_CAP_11G|PROTO_CAP_11N)
|
||||
|
||||
#endif /* __RTL8188F_SPEC_H__ */
|
||||
|
||||
|
||||
Reference in New Issue
Block a user