mirror of
https://github.com/Mange/rtl8192eu-linux-driver
synced 2025-12-10 00:04:17 +00:00
Add version v5.6.4
This commit is contained in:
Carlos Garces
@@ -1,233 +1,188 @@
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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*
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******************************************************************************/
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#include "mp_precomp.h"
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#include "../phydm_precomp.h"
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#if (RTL8192E_SUPPORT == 1)
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void
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odm_ConfigRFReg_8192E(
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IN PDM_ODM_T pDM_Odm,
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IN u4Byte Addr,
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IN u4Byte Data,
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IN ODM_RF_RADIO_PATH_E RF_PATH,
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IN u4Byte RegAddr
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)
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{
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if(Addr == 0xfe || Addr == 0xffe)
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{
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#ifdef CONFIG_LONG_DELAY_ISSUE
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ODM_sleep_ms(50);
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#else
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ODM_delay_ms(50);
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#endif
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}
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else
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{
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ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data);
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// Add 1us delay between BB/RF register setting.
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ODM_delay_us(1);
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//For disable/enable test in high temperature, the B6 value will fail to fill. Suggestion by Ed 20130.
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if(Addr == 0xb6)
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{
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u4Byte getvalue=0;
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u1Byte count =0;
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getvalue = ODM_GetRFReg(pDM_Odm, RF_PATH, Addr, bMaskDWord);
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ODM_delay_us(1);
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while((getvalue>>8)!=(Data>>8))
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{
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count++;
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ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data);
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ODM_delay_us(1);
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getvalue = ODM_GetRFReg(pDM_Odm, RF_PATH, Addr, bMaskDWord);
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ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [B6] getvalue 0x%x, Data 0x%x, count %d\n", getvalue, Data,count));
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if(count>5)
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break;
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}
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}
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if(Addr == 0xb2)
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{
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u4Byte getvalue=0;
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u1Byte count =0;
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getvalue = ODM_GetRFReg(pDM_Odm, RF_PATH, Addr, bMaskDWord);
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ODM_delay_us(1);
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while(getvalue!=Data)
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{
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count++;
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ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data);
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ODM_delay_us(1);
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//Do LCK againg
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ODM_SetRFReg(pDM_Odm, RF_PATH, 0x18, bRFRegOffsetMask, 0x0fc07);
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ODM_delay_us(1);
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getvalue = ODM_GetRFReg(pDM_Odm, RF_PATH, Addr, bMaskDWord);
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ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [B2] getvalue 0x%x, Data 0x%x, count %d\n", getvalue, Data,count));
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if(count>5)
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break;
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}
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}
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}
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}
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void
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odm_ConfigRF_RadioA_8192E(
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IN PDM_ODM_T pDM_Odm,
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IN u4Byte Addr,
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IN u4Byte Data
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)
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{
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u4Byte content = 0x1000; // RF_Content: radioa_txt
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u4Byte maskforPhySet= (u4Byte)(content&0xE000);
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odm_ConfigRFReg_8192E(pDM_Odm, Addr, Data, ODM_RF_PATH_A, Addr|maskforPhySet);
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ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioA] %08X %08X\n", Addr, Data));
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}
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void
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odm_ConfigRF_RadioB_8192E(
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IN PDM_ODM_T pDM_Odm,
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IN u4Byte Addr,
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IN u4Byte Data
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)
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{
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u4Byte content = 0x1001; // RF_Content: radiob_txt
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u4Byte maskforPhySet= (u4Byte)(content&0xE000);
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odm_ConfigRFReg_8192E(pDM_Odm, Addr, Data, ODM_RF_PATH_B, Addr|maskforPhySet);
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ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioB] %08X %08X\n", Addr, Data));
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}
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void
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odm_ConfigMAC_8192E(
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IN PDM_ODM_T pDM_Odm,
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IN u4Byte Addr,
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IN u1Byte Data
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)
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{
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ODM_Write1Byte(pDM_Odm, Addr, Data);
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ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigMACWithHeaderFile: [MAC_REG] %08X %08X\n", Addr, Data));
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}
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void
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odm_ConfigBB_AGC_8192E(
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IN PDM_ODM_T pDM_Odm,
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IN u4Byte Addr,
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IN u4Byte Bitmask,
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IN u4Byte Data
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)
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{
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ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data);
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// Add 1us delay between BB/RF register setting.
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ODM_delay_us(1);
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ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [AGC_TAB] %08X %08X\n", Addr, Data));
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}
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void
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odm_ConfigBB_PHY_REG_PG_8192E(
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IN PDM_ODM_T pDM_Odm,
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IN u4Byte Band,
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IN u4Byte RfPath,
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IN u4Byte TxNum,
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IN u4Byte Addr,
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IN u4Byte Bitmask,
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IN u4Byte Data
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)
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{
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if (Addr == 0xfe || Addr == 0xffe)
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#ifdef CONFIG_LONG_DELAY_ISSUE
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ODM_sleep_ms(50);
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#else
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ODM_delay_ms(50);
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#endif
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else
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{
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#if !(DM_ODM_SUPPORT_TYPE&ODM_AP)
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PHY_StoreTxPowerByRate(pDM_Odm->Adapter, Band, RfPath, TxNum, Addr, Bitmask, Data);
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#endif
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}
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ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X %08X\n", Addr, Bitmask, Data));
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}
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void
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odm_ConfigBB_PHY_8192E(
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IN PDM_ODM_T pDM_Odm,
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IN u4Byte Addr,
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IN u4Byte Bitmask,
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IN u4Byte Data
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)
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{
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if (Addr == 0xfe)
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#ifdef CONFIG_LONG_DELAY_ISSUE
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ODM_sleep_ms(50);
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#else
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ODM_delay_ms(50);
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#endif
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else if (Addr == 0xfd)
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ODM_delay_ms(5);
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else if (Addr == 0xfc)
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ODM_delay_ms(1);
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else if (Addr == 0xfb)
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ODM_delay_us(50);
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else if (Addr == 0xfa)
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ODM_delay_us(5);
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else if (Addr == 0xf9)
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ODM_delay_us(1);
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else
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{
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ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data);
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}
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// Add 1us delay between BB/RF register setting.
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ODM_delay_us(1);
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ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n", Addr, Data));
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}
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void
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odm_ConfigBB_TXPWR_LMT_8192E(
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IN PDM_ODM_T pDM_Odm,
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IN pu1Byte Regulation,
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IN pu1Byte Band,
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IN pu1Byte Bandwidth,
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IN pu1Byte RateSection,
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IN pu1Byte RfPath,
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IN pu1Byte Channel,
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IN pu1Byte PowerLimit
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)
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{
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#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
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PHY_SetTxPowerLimit(pDM_Odm, Regulation, Band,
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Bandwidth, RateSection, RfPath, Channel, PowerLimit);
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#endif
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}
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#endif
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2017 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#include "mp_precomp.h"
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#include "../phydm_precomp.h"
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#if (RTL8192E_SUPPORT == 1)
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void odm_config_rf_reg_8192e(struct dm_struct *dm, u32 addr, u32 data,
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enum rf_path RF_PATH, u32 reg_addr)
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{
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if (addr == 0xfe || addr == 0xffe) {
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#ifdef CONFIG_LONG_DELAY_ISSUE
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ODM_sleep_ms(50);
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#else
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ODM_delay_ms(50);
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#endif
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} else {
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odm_set_rf_reg(dm, RF_PATH, reg_addr, RFREGOFFSETMASK, data);
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/* Add 1us delay between BB/RF register setting. */
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ODM_delay_us(1);
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/* For disable/enable test in high temperature, the B6 value will fail to fill. Suggestion by Ed 20130. */
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if (addr == 0xb6) {
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u32 getvalue = 0;
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u8 count = 0;
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getvalue = odm_get_rf_reg(dm, RF_PATH, addr, MASKDWORD);
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ODM_delay_us(1);
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while ((getvalue >> 8) != (data >> 8)) {
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count++;
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odm_set_rf_reg(dm, RF_PATH, reg_addr, RFREGOFFSETMASK, data);
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ODM_delay_us(1);
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getvalue = odm_get_rf_reg(dm, RF_PATH, addr, MASKDWORD);
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PHYDM_DBG(dm, ODM_COMP_INIT,
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"===> odm_config_rf_with_header_file: [B6] getvalue 0x%x, data 0x%x, count %d\n",
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getvalue, data, count);
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if (count > 5)
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break;
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}
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}
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if (addr == 0xb2) {
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u32 getvalue = 0;
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u8 count = 0;
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getvalue = odm_get_rf_reg(dm, RF_PATH, addr, MASKDWORD);
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ODM_delay_us(1);
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while (getvalue != data) {
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count++;
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odm_set_rf_reg(dm, RF_PATH, reg_addr, RFREGOFFSETMASK, data);
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ODM_delay_us(1);
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/* Do LCK againg */
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odm_set_rf_reg(dm, RF_PATH, RF_0x18, RFREGOFFSETMASK, 0x0fc07);
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ODM_delay_us(1);
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getvalue = odm_get_rf_reg(dm, RF_PATH, addr, MASKDWORD);
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PHYDM_DBG(dm, ODM_COMP_INIT,
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"===> odm_config_rf_with_header_file: [B2] getvalue 0x%x, data 0x%x, count %d\n",
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getvalue, data, count);
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if (count > 5)
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break;
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}
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}
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}
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}
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void odm_config_rf_radio_a_8192e(struct dm_struct *dm, u32 addr, u32 data)
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{
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u32 content = 0x1000; /* RF_Content: radioa_txt */
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u32 maskfor_phy_set = (u32)(content & 0xE000);
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odm_config_rf_reg_8192e(dm, addr, data, RF_PATH_A, addr | maskfor_phy_set);
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PHYDM_DBG(dm, ODM_COMP_INIT,
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"===> odm_config_rf_with_header_file: [RadioA] %08X %08X\n",
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addr, data);
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}
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void odm_config_rf_radio_b_8192e(struct dm_struct *dm, u32 addr, u32 data)
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{
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u32 content = 0x1001; /* RF_Content: radiob_txt */
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u32 maskfor_phy_set = (u32)(content & 0xE000);
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odm_config_rf_reg_8192e(dm, addr, data, RF_PATH_B, addr | maskfor_phy_set);
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PHYDM_DBG(dm, ODM_COMP_INIT,
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"===> odm_config_rf_with_header_file: [RadioB] %08X %08X\n",
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addr, data);
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}
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void odm_config_mac_8192e(struct dm_struct *dm, u32 addr, u8 data)
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{
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odm_write_1byte(dm, addr, data);
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PHYDM_DBG(dm, ODM_COMP_INIT,
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"===> odm_config_mac_with_header_file: [MAC_REG] %08X %08X\n",
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addr, data);
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}
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void odm_config_bb_agc_8192e(struct dm_struct *dm, u32 addr, u32 bitmask,
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u32 data)
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{
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odm_set_bb_reg(dm, addr, bitmask, data);
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/* Add 1us delay between BB/RF register setting. */
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ODM_delay_us(1);
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PHYDM_DBG(dm, ODM_COMP_INIT,
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"===> odm_config_bb_with_header_file: [AGC_TAB] %08X %08X\n",
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addr, data);
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}
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void odm_config_bb_phy_reg_pg_8192e(struct dm_struct *dm, u32 band, u32 rf_path,
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u32 tx_num, u32 addr, u32 bitmask, u32 data)
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{
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if (addr == 0xfe || addr == 0xffe)
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#ifdef CONFIG_LONG_DELAY_ISSUE
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ODM_sleep_ms(50);
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#else
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ODM_delay_ms(50);
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#endif
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else {
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#if (DM_ODM_SUPPORT_TYPE & ODM_CE)
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phy_store_tx_power_by_rate(dm->adapter, band, rf_path, tx_num, addr, bitmask, data);
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#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
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PHY_StoreTxPowerByRate(dm->adapter, band, rf_path, tx_num, addr, bitmask, data);
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#endif
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}
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PHYDM_DBG(dm, ODM_COMP_INIT,
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"===> odm_config_bb_with_header_file: [PHY_REG] %08X %08X %08X\n",
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addr, bitmask, data);
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}
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void odm_config_bb_phy_8192e(struct dm_struct *dm, u32 addr, u32 bitmask,
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u32 data)
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{
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if (addr == 0xfe)
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#ifdef CONFIG_LONG_DELAY_ISSUE
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ODM_sleep_ms(50);
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#else
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ODM_delay_ms(50);
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#endif
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else if (addr == 0xfd)
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ODM_delay_ms(5);
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else if (addr == 0xfc)
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ODM_delay_ms(1);
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else if (addr == 0xfb)
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ODM_delay_us(50);
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else if (addr == 0xfa)
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ODM_delay_us(5);
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else if (addr == 0xf9)
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ODM_delay_us(1);
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else
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odm_set_bb_reg(dm, addr, bitmask, data);
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/* Add 1us delay between BB/RF register setting. */
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ODM_delay_us(1);
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PHYDM_DBG(dm, ODM_COMP_INIT,
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"===> odm_config_bb_with_header_file: [PHY_REG] %08X %08X\n",
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addr, data);
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}
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void odm_config_bb_txpwr_lmt_8192e(struct dm_struct *dm, u8 *regulation,
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u8 *band, u8 *bandwidth, u8 *rate_section,
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u8 *rf_path, u8 *channel, u8 *power_limit)
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{
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#if (DM_ODM_SUPPORT_TYPE & ODM_CE)
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phy_set_tx_power_limit(dm, regulation, band,
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bandwidth, rate_section, rf_path, channel, power_limit);
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#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
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PHY_SetTxPowerLimit(dm, regulation, band,
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bandwidth, rate_section, rf_path, channel, power_limit);
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#endif
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}
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#endif
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