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Add version v5.6.4

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This commit is contained in:
Carlos Garces
2019-11-09 11:12:08 +01:00
parent e7361e951c
commit 1d807f14d8
597 changed files with 314256 additions and 256218 deletions
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1359
hal/phydm/halrf/halphyrf_ap.c Normal file
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hal/phydm/halrf/halphyrf_ap.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __HALPHYRF_H__
#define __HALPHYRF_H__
#include "halrf/halrf_powertracking_ap.h"
#include "halrf/halrf_kfree.h"
#if (RTL8814A_SUPPORT == 1)
#include "halrf/rtl8814a/halrf_iqk_8814a.h"
#endif
#if (RTL8822B_SUPPORT == 1)
#include "halrf/rtl8822b/halrf_iqk_8822b.h"
#endif
#if (RTL8821C_SUPPORT == 1)
#include "halrf/rtl8821c/halrf_iqk_8821c.h"
#endif
#if (RTL8195B_SUPPORT == 1)
// #include "halrf/rtl8195b/halrf.h"
#include "halrf/rtl8195b/halrf_iqk_8195b.h"
#include "halrf/rtl8195b/halrf_txgapk_8195b.h"
#include "halrf/rtl8195b/halrf_dpk_8195b.h"
#endif
#if (RTL8198F_SUPPORT == 1)
#include "halrf/rtl8198f/halrf_iqk_8198f.h"
#include "halrf/rtl8198f/halrf_dpk_8198f.h"
#endif
#if (RTL8814B_SUPPORT == 1)
#include "halrf/rtl8814b/halrf_iqk_8814b.h"
#endif
enum pwrtrack_method {
BBSWING,
TXAGC,
MIX_MODE,
TSSI_MODE
};
typedef void (*func_set_pwr)(void *, enum pwrtrack_method, u8, u8);
typedef void(*func_iqk)(void *, u8, u8, u8);
typedef void (*func_lck)(void *);
/* refine by YuChen for 8814A */
typedef void (*func_swing)(void *, u8 **, u8 **, u8 **, u8 **);
typedef void (*func_swing8814only)(void *, u8 **, u8 **, u8 **, u8 **);
typedef void (*func_all_swing)(void *, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **);
typedef void (*func_all_swing_ex)(void *, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **);
struct txpwrtrack_cfg {
u8 swing_table_size_cck;
u8 swing_table_size_ofdm;
u8 threshold_iqk;
u8 threshold_dpk;
u8 average_thermal_num;
u8 rf_path_count;
u32 thermal_reg_addr;
func_set_pwr odm_tx_pwr_track_set_pwr;
func_iqk do_iqk;
func_lck phy_lc_calibrate;
func_swing get_delta_swing_table;
func_swing8814only get_delta_swing_table8814only;
func_all_swing get_delta_all_swing_table;
func_all_swing_ex get_delta_all_swing_table_ex;
};
void
configure_txpower_track(
void *dm_void,
struct txpwrtrack_cfg *config
);
void
odm_txpowertracking_callback_thermal_meter(
void *dm_void
);
#if (RTL8192E_SUPPORT == 1)
void
odm_txpowertracking_callback_thermal_meter_92e(
void *dm_void
);
#endif
#if (RTL8814A_SUPPORT == 1)
void
odm_txpowertracking_callback_thermal_meter_jaguar_series2(
void *dm_void
);
#elif ODM_IC_11AC_SERIES_SUPPORT
void
odm_txpowertracking_callback_thermal_meter_jaguar_series(
void *dm_void
);
#elif (RTL8197F_SUPPORT == 1 || RTL8822B_SUPPORT == 1)
void
odm_txpowertracking_callback_thermal_meter_jaguar_series3(
void *dm_void
);
#endif
#define IS_CCK_RATE(_rate) (ODM_MGN_1M == _rate || _rate == ODM_MGN_2M || _rate == ODM_MGN_5_5M || _rate == ODM_MGN_11M)
#define ODM_TARGET_CHNL_NUM_2G_5G 59
void
odm_reset_iqk_result(
void *dm_void
);
u8
odm_get_right_chnl_place_for_iqk(
u8 chnl
);
void phydm_rf_init(void *dm_void);
void phydm_rf_watchdog(void *dm_void);
#endif /*#ifndef __HALPHYRF_H__*/

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hal/phydm/halrf/halphyrf_ce.c Normal file
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hal/phydm/halrf/halphyrf_ce.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALPHYRF_H__
#define __HALPHYRF_H__
#include "halrf/halrf_kfree.h"
#if (RTL8814A_SUPPORT == 1)
#include "halrf/rtl8814a/halrf_iqk_8814a.h"
#endif
#if (RTL8822B_SUPPORT == 1)
#include "halrf/rtl8822b/halrf_iqk_8822b.h"
#endif
#if (RTL8821C_SUPPORT == 1)
#include "halrf/rtl8821c/halrf_iqk_8821c.h"
#endif
#if (RTL8195B_SUPPORT == 1)
/* #include "halrf/rtl8195b/halrf.h" */
#include "halrf/rtl8195b/halrf_iqk_8195b.h"
#include "halrf/rtl8195b/halrf_txgapk_8195b.h"
#include "halrf/rtl8195b/halrf_dpk_8195b.h"
#endif
#if (RTL8814B_SUPPORT == 1)
#include "halrf/rtl8814b/halrf_iqk_8814b.h"
#endif
#include "halrf/halrf_powertracking_ce.h"
enum spur_cal_method {
PLL_RESET,
AFE_PHASE_SEL
};
enum pwrtrack_method {
BBSWING,
TXAGC,
MIX_MODE,
TSSI_MODE,
MIX_2G_TSSI_5G_MODE,
MIX_5G_TSSI_2G_MODE
};
typedef void (*func_set_pwr)(void *, enum pwrtrack_method, u8, u8);
typedef void (*func_iqk)(void *, u8, u8, u8);
typedef void (*func_lck)(void *);
typedef void (*func_swing)(void *, u8 **, u8 **, u8 **, u8 **);
typedef void (*func_swing8814only)(void *, u8 **, u8 **, u8 **, u8 **);
typedef void (*func_swing_xtal)(void *, s8 **, s8 **);
typedef void (*func_set_xtal)(void *);
struct txpwrtrack_cfg {
u8 swing_table_size_cck;
u8 swing_table_size_ofdm;
u8 threshold_iqk;
u8 threshold_dpk;
u8 average_thermal_num;
u8 rf_path_count;
u32 thermal_reg_addr;
func_set_pwr odm_tx_pwr_track_set_pwr;
func_iqk do_iqk;
func_lck phy_lc_calibrate;
func_swing get_delta_swing_table;
func_swing8814only get_delta_swing_table8814only;
func_swing_xtal get_delta_swing_xtal_table;
func_set_xtal odm_txxtaltrack_set_xtal;
};
void configure_txpower_track(void *dm_void, struct txpwrtrack_cfg *config);
void odm_clear_txpowertracking_state(void *dm_void);
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
void odm_txpowertracking_callback_thermal_meter(void *dm_void);
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
void odm_txpowertracking_callback_thermal_meter(void *dm);
#else
void odm_txpowertracking_callback_thermal_meter(void *adapter);
#endif
#define ODM_TARGET_CHNL_NUM_2G_5G 59
void odm_reset_iqk_result(void *dm_void);
u8 odm_get_right_chnl_place_for_iqk(u8 chnl);
void phydm_rf_init(void *dm_void);
void phydm_rf_watchdog(void *dm_void);
#endif /*__HALPHYRF_H__*/

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hal/phydm/halrf/halphyrf_iot.c Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALPHYRF_H__
#define __HALPHYRF_H__
#include "halrf/halrf_kfree.h"
#if (RTL8821C_SUPPORT == 1)
#include "halrf/rtl8821c/halrf_iqk_8821c.h"
#endif
#if (RTL8195B_SUPPORT == 1)
// #include "halrf/rtl8195b/halrf.h"
#include "halrf/rtl8195b/halrf_iqk_8195b.h"
#include "halrf/rtl8195b/halrf_txgapk_8195b.h"
#include "halrf/rtl8195b/halrf_dpk_8195b.h"
#endif
#include "halrf/halrf_powertracking_iot.h"
enum spur_cal_method {
PLL_RESET,
AFE_PHASE_SEL
};
enum pwrtrack_method {
BBSWING,
TXAGC,
MIX_MODE,
TSSI_MODE,
MIX_2G_TSSI_5G_MODE,
MIX_5G_TSSI_2G_MODE
};
typedef void (*func_set_pwr)(void *, enum pwrtrack_method, u8, u8);
typedef void(*func_iqk)(void *, u8, u8, u8);
typedef void (*func_lck)(void *);
typedef void (*func_swing)(void *, u8 **, u8 **, u8 **, u8 **);
typedef void (*func_swing8814only)(void *, u8 **, u8 **, u8 **, u8 **);
typedef void(*func_swing_xtal)(void *, s8 **, s8 **);
typedef void(*func_set_xtal)(void *);
struct txpwrtrack_cfg {
u8 swing_table_size_cck;
u8 swing_table_size_ofdm;
u8 threshold_iqk;
u8 threshold_dpk;
u8 average_thermal_num;
u8 rf_path_count;
u32 thermal_reg_addr;
func_set_pwr odm_tx_pwr_track_set_pwr;
func_iqk do_iqk;
func_lck phy_lc_calibrate;
func_swing get_delta_swing_table;
func_swing8814only get_delta_swing_table8814only;
func_swing_xtal get_delta_swing_xtal_table;
func_set_xtal odm_txxtaltrack_set_xtal;
};
void
configure_txpower_track(
void *dm_void,
struct txpwrtrack_cfg *config
);
void
odm_clear_txpowertracking_state(
void *dm_void
);
void
odm_txpowertracking_callback_thermal_meter(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
void *dm_void
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
void *dm
#else
void *adapter
#endif
);
#define ODM_TARGET_CHNL_NUM_2G_5G 59
void
odm_reset_iqk_result(
void *dm_void
);
u8
odm_get_right_chnl_place_for_iqk(
u8 chnl
);
void phydm_rf_init(void *dm_void);
void phydm_rf_watchdog(void *dm_void);
#endif /*#ifndef __HALPHYRF_H__*/

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hal/phydm/halrf/halphyrf_win.c Normal file
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hal/phydm/halrf/halphyrf_win.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __HALPHYRF_H__
#define __HALPHYRF_H__
#if (RTL8814A_SUPPORT == 1)
#include "halrf/rtl8814a/halrf_iqk_8814a.h"
#endif
#if (RTL8822B_SUPPORT == 1)
#include "halrf/rtl8822b/halrf_iqk_8822b.h"
#include "../mac/Halmac_type.h"
#endif
#include "halrf/halrf_powertracking_win.h"
#include "halrf/halrf_kfree.h"
#include "halrf/halrf_txgapcal.h"
#if (RTL8821C_SUPPORT == 1)
#include "halrf/rtl8821c/halrf_iqk_8821c.h"
#endif
#if (RTL8195B_SUPPORT == 1)
// #include "halrf/rtl8195b/halrf.h"
#include "halrf/rtl8195b/halrf_iqk_8195b.h"
#include "halrf/rtl8195b/halrf_txgapk_8195b.h"
#include "halrf/rtl8195b/halrf_dpk_8195b.h"
#endif
#if (RTL8814B_SUPPORT == 1)
#include "halrf/rtl8814b/halrf_iqk_8814b.h"
#endif
enum spur_cal_method {
PLL_RESET,
AFE_PHASE_SEL
};
enum pwrtrack_method {
BBSWING,
TXAGC,
MIX_MODE,
TSSI_MODE,
MIX_2G_TSSI_5G_MODE,
MIX_5G_TSSI_2G_MODE
};
typedef void(*func_set_pwr)(void *, enum pwrtrack_method, u8, u8);
typedef void(*func_iqk)(void *, u8, u8, u8);
typedef void(*func_lck)(void *);
typedef void(*func_swing)(void *, u8 **, u8 **, u8 **, u8 **);
typedef void(*func_swing8814only)(void *, u8 **, u8 **, u8 **, u8 **);
typedef void (*func_swing_xtal)(void *, s8 **, s8 **);
typedef void (*func_set_xtal)(void *);
typedef void(*func_all_swing)(void *, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **);
struct txpwrtrack_cfg {
u8 swing_table_size_cck;
u8 swing_table_size_ofdm;
u8 threshold_iqk;
u8 threshold_dpk;
u8 average_thermal_num;
u8 rf_path_count;
u32 thermal_reg_addr;
func_set_pwr odm_tx_pwr_track_set_pwr;
func_iqk do_iqk;
func_lck phy_lc_calibrate;
func_swing get_delta_swing_table;
func_swing8814only get_delta_swing_table8814only;
func_swing_xtal get_delta_swing_xtal_table;
func_set_xtal odm_txxtaltrack_set_xtal;
func_all_swing get_delta_all_swing_table;
};
void
configure_txpower_track(
struct dm_struct *dm,
struct txpwrtrack_cfg *config
);
void
odm_clear_txpowertracking_state(
struct dm_struct *dm
);
void
odm_txpowertracking_callback_thermal_meter(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
struct dm_struct *dm
#else
void *adapter
#endif
);
#define ODM_TARGET_CHNL_NUM_2G_5G 59
void
odm_reset_iqk_result(
struct dm_struct *dm
);
u8
odm_get_right_chnl_place_for_iqk(
u8 chnl
);
void odm_iq_calibrate(struct dm_struct *dm);
void phydm_rf_init(struct dm_struct *dm);
void phydm_rf_watchdog(struct dm_struct *dm);
#endif /*#ifndef __HALPHYRF_H__*/

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hal/phydm/halrf/halrf.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/*@************************************************************
* include files
* ************************************************************
*/
#include "mp_precomp.h"
#include "phydm_precomp.h"
void halrf_basic_profile(void *dm_void, u32 *_used, char *output, u32 *_out_len)
{
#ifdef CONFIG_PHYDM_DEBUG_FUNCTION
struct dm_struct *dm = (struct dm_struct *)dm_void;
u32 used = *_used;
u32 out_len = *_out_len;
/* HAL RF version List */
PDM_SNPF(out_len, used, output + used, out_len - used, "%-35s\n",
"% HAL RF version %");
PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n",
"Power Tracking", HALRF_POWRTRACKING_VER);
PDM_SNPF(out_len, used, output + used, out_len - used,
" %-35s: %s %s\n", "IQK",
(dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) ? "FW" :
HALRF_IQK_VER,
(halrf_match_iqk_version(dm_void)) ? "(match)" : "(mismatch)");
PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n",
"LCK", HALRF_LCK_VER);
PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n",
"DPK", HALRF_DPK_VER);
PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n",
"KFREE", HALRF_KFREE_VER);
PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n",
"TX 2G Current Calibration", HALRF_PABIASK_VER);
PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n",
"RFK Init. Parameter", HALRF_RFK_INIT_VER);
*_used = used;
*_out_len = out_len;
#endif
}
void halrf_debug_trace(void *dm_void, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _hal_rf_ *rf = &dm->rf_table;
u32 one = 1;
u32 used = *_used;
u32 out_len = *_out_len;
u32 rf_var[10] = {0};
u8 i;
for (i = 0; i < 5; i++)
if (input[i + 1])
PHYDM_SSCANF(input[i + 2], DCMD_DECIMAL, &rf_var[i]);
if (rf_var[0] == 100) {
PDM_SNPF(out_len, used, output + used, out_len - used,
"\n[DBG MSG] RF Selection\n");
PDM_SNPF(out_len, used, output + used, out_len - used,
"00. (( %s ))TX_PWR_TRACK\n",
((rf->rf_dbg_comp & DBG_RF_TX_PWR_TRACK) ? ("V") :
(".")));
PDM_SNPF(out_len, used, output + used, out_len - used,
"01. (( %s ))IQK\n",
((rf->rf_dbg_comp & DBG_RF_IQK) ? ("V") : (".")));
PDM_SNPF(out_len, used, output + used, out_len - used,
"02. (( %s ))LCK\n",
((rf->rf_dbg_comp & DBG_RF_LCK) ? ("V") : (".")));
PDM_SNPF(out_len, used, output + used, out_len - used,
"03. (( %s ))DPK\n",
((rf->rf_dbg_comp & DBG_RF_DPK) ? ("V") : (".")));
PDM_SNPF(out_len, used, output + used, out_len - used,
"04. (( %s ))TXGAPK\n",
((rf->rf_dbg_comp & DBG_RF_TXGAPK) ? ("V") : (".")));
PDM_SNPF(out_len, used, output + used, out_len - used,
"29. (( %s ))MP\n",
((rf->rf_dbg_comp & DBG_RF_MP) ? ("V") : (".")));
PDM_SNPF(out_len, used, output + used, out_len - used,
"30. (( %s ))TMP\n",
((rf->rf_dbg_comp & DBG_RF_TMP) ? ("V") : (".")));
PDM_SNPF(out_len, used, output + used, out_len - used,
"31. (( %s ))INIT\n",
((rf->rf_dbg_comp & DBG_RF_INIT) ? ("V") : (".")));
} else if (rf_var[0] == 101) {
rf->rf_dbg_comp = 0;
PDM_SNPF(out_len, used, output + used, out_len - used,
"Disable all DBG COMP\n");
} else {
if (rf_var[1] == 1) /*enable*/
rf->rf_dbg_comp |= (one << rf_var[0]);
else if (rf_var[1] == 2) /*disable*/
rf->rf_dbg_comp &= ~(one << rf_var[0]);
}
PDM_SNPF(out_len, used, output + used, out_len - used,
"\nCurr-RF_Dbg_Comp = 0x%x\n", rf->rf_dbg_comp);
*_used = used;
*_out_len = out_len;
}
struct halrf_command {
char name[16];
u8 id;
};
enum halrf_CMD_ID {
HALRF_HELP,
HALRF_SUPPORTABILITY,
HALRF_DBG_COMP,
HALRF_PROFILE,
HALRF_IQK_INFO,
HALRF_IQK,
HALRF_IQK_DEBUG,
};
struct halrf_command halrf_cmd_ary[] = {
{"-h", HALRF_HELP},
{"ability", HALRF_SUPPORTABILITY},
{"dbg", HALRF_DBG_COMP},
{"profile", HALRF_PROFILE},
{"iqk_info", HALRF_IQK_INFO},
{"iqk", HALRF_IQK},
{"iqk_dbg", HALRF_IQK_DEBUG},
};
void halrf_cmd_parser(void *dm_void, char input[][16], u32 *_used, char *output,
u32 *_out_len, u32 input_num)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
#ifdef CONFIG_PHYDM_DEBUG_FUNCTION
u8 id = 0;
u32 rf_var[10] = {0};
u32 i, input_idx = 0;
u32 halrf_ary_size =
sizeof(halrf_cmd_ary) / sizeof(struct halrf_command);
u32 used = *_used;
u32 out_len = *_out_len;
/* Parsing Cmd ID */
for (i = 0; i < halrf_ary_size; i++) {
if (strcmp(halrf_cmd_ary[i].name, input[1]) == 0) {
id = halrf_cmd_ary[i].id;
break;
}
}
if (i == halrf_ary_size) {
PDM_SNPF(out_len, used, output + used, out_len - used,
"RF Cmd not found\n");
return;
}
switch (id) {
case HALRF_HELP:
PDM_SNPF(out_len, used, output + used, out_len - used,
"RF cmd ==>\n");
for (i = 0; i < halrf_ary_size - 1; i++) {
PDM_SNPF(out_len, used, output + used, out_len - used,
" %-5d: %s\n", i, halrf_cmd_ary[i + 1].name);
}
break;
case HALRF_SUPPORTABILITY:
halrf_support_ability_debug(dm, &input[0], &used, output,
&out_len);
break;
case HALRF_DBG_COMP:
halrf_debug_trace(dm, &input[0], &used, output, &out_len);
break;
case HALRF_PROFILE:
halrf_basic_profile(dm, &used, output, &out_len);
break;
case HALRF_IQK_INFO:
#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
halrf_iqk_info_dump(dm, &used, output, &out_len);
#endif
break;
case HALRF_IQK:
PDM_SNPF(out_len, used, output + used, out_len - used,
"TRX IQK Trigger\n");
halrf_iqk_trigger(dm, false);
#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
halrf_iqk_info_dump(dm, &used, output, &out_len);
#endif
break;
case HALRF_IQK_DEBUG:
for (i = 0; i < 5; i++) {
if (input[i + 1]) {
PHYDM_SSCANF(input[i + 2], DCMD_HEX,
&rf_var[i]);
input_idx++;
}
}
if (input_idx >= 1) {
#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C))
halrf_iqk_debug(dm, (u32 *)rf_var, &used,
output, &out_len);
#endif
}
break;
default:
break;
}
*_used = used;
*_out_len = out_len;
#endif
}
void halrf_init_debug_setting(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _hal_rf_ *rf = &dm->rf_table;
rf->rf_dbg_comp =
#if DBG
#if 0
/*DBG_RF_TX_PWR_TRACK |*/
/*DBG_RF_IQK | */
/*DBG_RF_LCK | */
/*DBG_RF_DPK | */
/*DBG_RF_DACK | */
/*DBG_RF_TXGAPK | */
/*DBG_RF_MP | */
/*DBG_RF_TMP | */
/*DBG_RF_INIT | */
#endif
#endif
0;
}

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALRF_DEBUG_H__
#define __HALRF_DEBUG_H__
/*@============================================================*/
/*@include files*/
/*@============================================================*/
/*@============================================================*/
/*@Definition */
/*@============================================================*/
#if DBG
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
#define RF_DBG(dm, comp, fmt, args...) \
do { \
if ((comp) & dm->rf_table.rf_dbg_comp) { \
pr_debug("[RF] "); \
RT_PRINTK(fmt, ##args); \
} \
} while (0)
#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
static __inline void RF_DBG(PDM_ODM_T dm, int comp, char *fmt, ...)
{
RT_STATUS rt_status;
va_list args;
char buf[PRINT_MAX_SIZE] = {0};
if ((comp & dm->rf_table.rf_dbg_comp) == 0)
return;
if (fmt == NULL)
return;
va_start(args, fmt);
rt_status = (RT_STATUS)RtlStringCbVPrintfA(buf, PRINT_MAX_SIZE, fmt, args);
va_end(args);
if (rt_status != RT_STATUS_SUCCESS) {
DbgPrint("Failed (%d) to print message to buffer\n", rt_status);
return;
}
DbgPrint("[RF] %s", buf);
}
#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT)
#define RF_DBG(dm, comp, fmt, args...) \
do { \
if ((comp) & dm->rf_table.rf_dbg_comp) { \
RT_DEBUG(COMP_PHYDM, DBG_DMESG, "[RF] " fmt, ##args); \
} \
} while (0)
#else
#define RF_DBG(dm, comp, fmt, args...) \
do { \
struct dm_struct *__dm = dm; \
if ((comp) & __dm->rf_table.rf_dbg_comp) { \
RT_TRACE(((struct rtl_priv *)__dm->adapter), \
COMP_PHYDM, DBG_DMESG, "[RF] " fmt, ##args); \
} \
} while (0)
#endif
#else /*#if DBG*/
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
static __inline void RF_DBG(struct dm_struct *dm, int comp, char *fmt, ...)
{
}
#else
#define RF_DBG(dm, comp, fmt, args...)
#endif
#endif /*#if DBG*/
/*@============================================================*/
/*@ enumeration */
/*@============================================================*/
/*@============================================================*/
/*@ structure */
/*@============================================================*/
/*@============================================================*/
/*@ function prototype */
/*@============================================================*/
void halrf_cmd_parser(void *dm_void, char input[][16], u32 *_used, char *output,
u32 *_out_len, u32 input_num);
void halrf_init_debug_setting(void *dm_void);
#endif /*__HALRF_H__*/

86
hal/phydm/halrf/halrf_dpk.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALRF_DPK_H__
#define __HALRF_DPK_H__
/*@--------------------------Define Parameters-------------------------------*/
#define GAIN_LOSS 1
#define DO_DPK 2
#define DPK_ON 3
#define DPK_LOK 4
#define DPK_TXK 5
#define DAGC 4
#define LOSS_CHK 0
#define GAIN_CHK 1
#define PAS_READ 2
#define AVG_THERMAL_NUM 8
#define AVG_THERMAL_NUM_DPK 8
#define THERMAL_DPK_AVG_NUM 4
/*@---------------------------End Define Parameters---------------------------*/
struct dm_dpk_info {
boolean is_dpk_enable;
boolean is_dpk_pwr_on;
boolean is_dpk_by_channel;
u16 dpk_path_ok;
/*@BIT(15)~BIT(12) : 5G reserved, BIT(11)~BIT(8) 5G_S3~5G_S0*/
/*@BIT(7)~BIT(4) : 2G reserved, BIT(3)~BIT(0) 2G_S3~2G_S0*/
u8 thermal_dpk;
u8 thermal_dpk_avg[AVG_THERMAL_NUM_DPK];
u8 thermal_dpk_avg_index;
#if (RTL8822C_SUPPORT == 1)
u8 result[2][1]; /*path/group*/
u8 tx_agc[2][1]; /*path/group*/
u32 coef[2][1][20]; /*path/group/MDPD coefficient*/
#endif
#if (RTL8198F_SUPPORT == 1 || RTL8192F_SUPPORT == 1 || RTL8197F_SUPPORT == 1)
/*2G DPK data*/
u8 dpk_result[4][3]; /*path/group*/
u8 pwsf_2g[4][3]; /*path/group*/
u32 lut_2g_even[4][3][64]; /*path/group/LUT data*/
u32 lut_2g_odd[4][3][64]; /*path/group/LUT data*/
#endif
#if (RTL8195B_SUPPORT == 1)
/*2G DPK data*/
u8 dpk_2g_result[1][3]; /*path/group*/
u8 pwsf_2g[1][3]; /*path/group*/
u32 lut_2g_even[1][3][16]; /*path/group/LUT data*/
u32 lut_2g_odd[1][3][16]; /*path/group/LUT data*/
/*5G DPK data*/
u8 dpk_5g_result[1][6]; /*path/group*/
u8 pwsf_5g[1][6]; /*path/group*/
u32 lut_5g_even[1][6][16]; /*path/group/LUT data*/
u32 lut_5g_odd[1][6][16]; /*path/group/LUT data*/
#endif
};
#endif /*__HALRF_DPK_H__*/

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hal/phydm/halrf/halrf_features.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALRF_FEATURES_H__
#define __HALRF_FEATURES_H__
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#define CONFIG_HALRF_POWERTRACKING 1
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
#define CONFIG_HALRF_POWERTRACKING 1
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#define CONFIG_HALRF_POWERTRACKING 1
#endif
#endif /*#ifndef __HALRF_FEATURES_H__*/

103
hal/phydm/halrf/halrf_iqk.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALRF_IQK_H__
#define __HALRF_IQK_H__
/*@--------------------------Define Parameters-------------------------------*/
#define LOK_delay 1
#define WBIQK_delay 10
#define TX_IQK 0
#define RX_IQK 1
#define TXIQK 0
#define RXIQK1 1
#define RXIQK2 2
#define kcount_limit_80m 2
#define kcount_limit_others 4
#define rxiqk_gs_limit 10
#define TXWBIQK_EN 1
#define RXWBIQK_EN 1
#define NUM 4
/*@-----------------------End Define Parameters-----------------------*/
struct dm_dack_info {
u32 ic_a;
u32 qc_a;
u32 ic_b;
u32 qc_b;
};
struct dm_iqk_info {
boolean lok_fail[NUM];
boolean iqk_fail[2][NUM];
u32 iqc_matrix[2][NUM];
u8 iqk_times;
u32 rf_reg18;
u32 rf_reg08;
u32 lna_idx;
u8 iqk_step;
u8 rxiqk_step;
u8 tmp1bcc;
u8 txgain;
u8 kcount;
u8 rfk_ing; /*bit0:IQKing, bit1:LCKing, bit2:DPKing*/
boolean rfk_forbidden;
u8 rxbb;
#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 ||\
RTL8195B_SUPPORT == 1 || RTL8198F_SUPPORT == 1 ||\
RTL8814B_SUPPORT == 1 || RTL8822C_SUPPORT == 1)
u32 iqk_channel[2];
boolean iqk_fail_report[2][4][2]; /*channel/path/TRX(TX:0, RX:1) */
/*channel / path / TRX(TX:0, RX:1) / CFIR_real*/
/*channel index = 2 is just for debug*/
u32 iqk_cfir_real[3][4][2][8];
/*channel / path / TRX(TX:0, RX:1) / CFIR_imag*/
/*channel index = 2 is just for debug*/
u32 iqk_cfir_imag[3][4][2][8];
u8 retry_count[2][4][3]; /* channel / path / (TXK:0, RXK1:1, RXK2:2) */
u8 gs_retry_count[2][4][2]; /* channel / path / (GSRXK1:0, GSRXK2:1) */
/* channel / path 0:SRXK1 fail, 1:RXK1 fail 2:RXK2 fail */
u8 rxiqk_fail_code[2][4];
u32 lok_idac[2][4]; /*channel / path*/
u16 rxiqk_agc[2][4]; /*channel / path*/
u32 bypass_iqk[2][4]; /*channel / 0xc94/0xe94*/
u32 txgap_result[8]; /*txagpK result */
u32 tmp_gntwl;
boolean is_btg;
boolean isbnd;
boolean is_reload;
boolean segment_iqk;
boolean is_hwtx;
boolean xym_read;
boolean trximr_enable;
u32 rx_xym[2][10];
u32 tx_xym[2][10];
u32 gs1_xym[2][6];
u32 gs2_xym[2][6];
u32 rxk1_xym[2][6];
#endif
};
#endif /*__HALRF_IQK_H__*/

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hal/phydm/halrf/halrf_kfree.c Normal file
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119
hal/phydm/halrf/halrf_kfree.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALRF_KFREE_H__
#define __HALRF_KFREE_H__
#define KFREE_VERSION "1.0"
#define KFREE_BAND_NUM 6
#define KFREE_CH_NUM 3
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_AP))
#define BB_GAIN_NUM 6
#endif
#define KFREE_FLAG_ON BIT(0)
#define KFREE_FLAG_THERMAL_K_ON BIT(1)
#define KFREE_FLAG_ON_2G BIT(2)
#define KFREE_FLAG_ON_5G BIT(3)
#define PA_BIAS_FLAG_ON BIT(4)
#define PPG_THERMAL_OFFSET_98F 0x50
#define PPG_2GM_TXAB_98F 0x51
#define PPG_2GM_TXCD_98F 0x52
#define PPG_2GL_TXAB_98F 0x53
#define PPG_2GL_TXCD_98F 0x54
#define PPG_5GH_TXAB_98F 0x55
#define PPG_5GH_TXCD_98F 0x56
#define PPG_THERMAL_OFFSET_21C 0x1EF
#define PPG_2G_TXAB_21C 0x1EE
#define PPG_5GL1_TXA_21C 0x1EC
#define PPG_5GL2_TXA_21C 0x1E8
#define PPG_5GM1_TXA_21C 0x1E4
#define PPG_5GM2_TXA_21C 0x1E0
#define PPG_5GH1_TXA_21C 0x1DC
#define PPG_THERMAL_OFFSET_22B 0x3EF
#define PPG_2G_TXAB_22B 0x3EE
#define PPG_2G_TXCD_22B 0x3ED
#define PPG_5GL1_TXA_22B 0x3EC
#define PPG_5GL1_TXB_22B 0x3EB
#define PPG_5GL1_TXC_22B 0x3EA
#define PPG_5GL1_TXD_22B 0x3E9
#define PPG_5GL2_TXA_22B 0x3E8
#define PPG_5GL2_TXB_22B 0x3E7
#define PPG_5GL2_TXC_22B 0x3E6
#define PPG_5GL2_TXD_22B 0x3E5
#define PPG_5GM1_TXA_22B 0x3E4
#define PPG_5GM1_TXB_22B 0x3E3
#define PPG_5GM1_TXC_22B 0x3E2
#define PPG_5GM1_TXD_22B 0x3E1
#define PPG_5GM2_TXA_22B 0x3E0
#define PPG_5GM2_TXB_22B 0x3DF
#define PPG_5GM2_TXC_22B 0x3DE
#define PPG_5GM2_TXD_22B 0x3DD
#define PPG_5GH1_TXA_22B 0x3DC
#define PPG_5GH1_TXB_22B 0x3DB
#define PPG_5GH1_TXC_22B 0x3DA
#define PPG_5GH1_TXD_22B 0x3D9
#define PPG_PABIAS_2GA_22B 0x3D5
#define PPG_PABIAS_2GB_22B 0x3D6
struct odm_power_trim_data {
u8 flag;
u8 pa_bias_flag;
s8 bb_gain[KFREE_BAND_NUM][MAX_RF_PATH];
s8 thermal;
};
enum phydm_kfree_channeltosw {
PHYDM_2G = 0,
PHYDM_5GLB1 = 1,
PHYDM_5GLB2 = 2,
PHYDM_5GMB1 = 3,
PHYDM_5GMB2 = 4,
PHYDM_5GHB = 5,
};
void phydm_get_thermal_trim_offset(void *dm_void);
void phydm_get_power_trim_offset(void *dm_void);
void phydm_get_pa_bias_offset(void *dm_void);
s8 phydm_get_thermal_offset(void *dm_void);
void phydm_clear_kfree_to_rf(void *dm_void, u8 e_rf_path, u8 data);
void phydm_config_kfree(void *dm_void, u8 channel_to_sw);
#endif /*__HALRF_KFREE_H__*/

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hal/phydm/halrf/halrf_powertracking.c Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/*@************************************************************
* include files
* ************************************************************
*/
#include "mp_precomp.h"
#include "phydm_precomp.h"
boolean
odm_check_power_status(void *dm_void)
{
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
struct dm_struct *dm = (struct dm_struct *)dm_void;
PADAPTER *adapter = dm->adapter;
RT_RF_POWER_STATE rt_state;
MGNT_INFO *mgnt_info = &((PADAPTER)adapter)->MgntInfo;
/* 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence. */
if (mgnt_info->init_adpt_in_progress == true) {
RF_DBG(dm, DBG_RF_INIT,
"check_pow_status Return true, due to initadapter\n");
return true;
}
/*
* 2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK.
*/
((PADAPTER)adapter)->HalFunc.GetHwRegHandler((PADAPTER)adapter, HW_VAR_RF_STATE, (u8 *)(&rt_state));
if (((PADAPTER)adapter)->bDriverStopped || ((PADAPTER)adapter)->bDriverIsGoingToPnpSetPowerSleep || rt_state == eRfOff) {
RF_DBG(dm, DBG_RF_INIT,
"check_pow_status Return false, due to %d/%d/%d\n",
((PADAPTER)adapter)->bDriverStopped,
((PADAPTER)adapter)->bDriverIsGoingToPnpSetPowerSleep,
rt_state);
return false;
}
#endif
return true;
}
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
void halrf_update_pwr_track(void *dm_void, u8 rate)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
u8 path_idx = 0;
#endif
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Pwr Track Get rate=0x%x\n", rate);
dm->tx_rate = rate;
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#if DEV_BUS_TYPE == RT_PCI_INTERFACE
#if USE_WORKITEM
odm_schedule_work_item(&dm->ra_rpt_workitem);
#else
if (dm->support_ic_type == ODM_RTL8821) {
#if (RTL8821A_SUPPORT == 1)
odm_tx_pwr_track_set_pwr8821a(dm, MIX_MODE, RF_PATH_A, 0);
#endif
} else if (dm->support_ic_type == ODM_RTL8812) {
for (path_idx = RF_PATH_A; path_idx < MAX_PATH_NUM_8812A; path_idx++) {
#if (RTL8812A_SUPPORT == 1)
odm_tx_pwr_track_set_pwr8812a(dm, MIX_MODE, path_idx, 0);
#endif
}
} else if (dm->support_ic_type == ODM_RTL8723B) {
#if (RTL8723B_SUPPORT == 1)
odm_tx_pwr_track_set_pwr_8723b(dm, MIX_MODE, RF_PATH_A, 0);
#endif
} else if (dm->support_ic_type == ODM_RTL8192E) {
for (path_idx = RF_PATH_A; path_idx < MAX_PATH_NUM_8192E; path_idx++) {
#if (RTL8192E_SUPPORT == 1)
odm_tx_pwr_track_set_pwr92_e(dm, MIX_MODE, path_idx, 0);
#endif
}
} else if (dm->support_ic_type == ODM_RTL8188E) {
#if (RTL8188E_SUPPORT == 1)
odm_tx_pwr_track_set_pwr88_e(dm, MIX_MODE, RF_PATH_A, 0);
#endif
}
#endif
#else
odm_schedule_work_item(&dm->ra_rpt_workitem);
#endif
#endif
}
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void halrf_update_init_rate_work_item_callback(
void *context)
{
void *adapter = (void *)context;
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
struct dm_struct *dm = &hal_data->DM_OutSrc;
u8 p = 0;
if (dm->support_ic_type == ODM_RTL8821) {
#if (RTL8821A_SUPPORT == 1)
odm_tx_pwr_track_set_pwr8821a(dm, MIX_MODE, RF_PATH_A, 0);
#endif
} else if (dm->support_ic_type == ODM_RTL8812) {
#if (RTL8812A_SUPPORT == 1)
/*Don't know how to include &c*/
for (p = RF_PATH_A; p < MAX_PATH_NUM_8812A; p++)
odm_tx_pwr_track_set_pwr8812a(dm, MIX_MODE, p, 0);
#endif
} else if (dm->support_ic_type == ODM_RTL8723B) {
#if (RTL8723B_SUPPORT == 1)
odm_tx_pwr_track_set_pwr_8723b(dm, MIX_MODE, RF_PATH_A, 0);
#endif
} else if (dm->support_ic_type == ODM_RTL8192E) {
#if (RTL8192E_SUPPORT == 1)
/*Don't know how to include &c*/
for (p = RF_PATH_A; p < MAX_PATH_NUM_8192E; p++)
odm_tx_pwr_track_set_pwr92_e(dm, MIX_MODE, p, 0);
#endif
} else if (dm->support_ic_type == ODM_RTL8188E) {
#if (RTL8188E_SUPPORT == 1)
odm_tx_pwr_track_set_pwr88_e(dm, MIX_MODE, RF_PATH_A, 0);
#endif
}
}
#endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALRF_POWER_TRACKING_H__
#define __HALRF_POWER_TRACKING_H__
boolean
odm_check_power_status(void *dm_void);
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
void halrf_update_pwr_track(void *dm_void, u8 rate);
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void halrf_update_init_rate_work_item_callback(
void *context);
#endif
#endif /*#ifndef __HALRF_POWERTRACKING_H__*/

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __HALRF_POWERTRACKING_H__
#define __HALRF_POWERTRACKING_H__
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
#ifdef RTK_AC_SUPPORT
#define ODM_IC_11AC_SERIES_SUPPORT 1
#else
#define ODM_IC_11AC_SERIES_SUPPORT 0
#endif
#else
#define ODM_IC_11AC_SERIES_SUPPORT 1
#endif
#define DPK_DELTA_MAPPING_NUM 13
#define index_mapping_HP_NUM 15
#define DELTA_SWINGIDX_SIZE 30
#define DELTA_SWINTSSI_SIZE 61
#define BAND_NUM 3
#define MAX_RF_PATH 4
#define TXSCALE_TABLE_SIZE 37
#define CCK_TABLE_SIZE_8723D 41
/* JJ ADD 20161014 */
#define CCK_TABLE_SIZE_8710B 41
#define IQK_MAC_REG_NUM 4
#define IQK_ADDA_REG_NUM 16
#define IQK_BB_REG_NUM_MAX 10
#define IQK_BB_REG_NUM 9
#define AVG_THERMAL_NUM 8
#define AVG_THERMAL_NUM_DPK 8
#define THERMAL_DPK_AVG_NUM 4
#define iqk_matrix_reg_num 8
/* #define IQK_MATRIX_SETTINGS_NUM 1+24+21 */
#define IQK_MATRIX_SETTINGS_NUM (14+24+21) /* Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G */
#if !defined(_OUTSRC_COEXIST)
#define OFDM_TABLE_SIZE_92D 43
#define OFDM_TABLE_SIZE 37
#define CCK_TABLE_SIZE 33
#define CCK_TABLE_SIZE_88F 21
#define CCK_TABLE_SIZE_8192F 41
/* #define OFDM_TABLE_SIZE_92E 54 */
/* #define CCK_TABLE_SIZE_92E 54 */
extern u32 ofdm_swing_table[OFDM_TABLE_SIZE_92D];
extern u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8];
extern u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8];
extern u32 ofdm_swing_table_new[OFDM_TABLE_SIZE_92D];
extern u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8];
extern u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8];
extern u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16];
extern u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16];
extern u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16];
extern u32 cck_swing_table_ch1_ch14_8192f[CCK_TABLE_SIZE_8192F];
#endif
#define ODM_OFDM_TABLE_SIZE 37
#define ODM_CCK_TABLE_SIZE 33
/* <20140613, YuChen> In case fail to read TxPowerTrack.txt, we use the table of 88E as the default table. */
extern u8 delta_swing_table_idx_2ga_p_default[DELTA_SWINGIDX_SIZE];
extern u8 delta_swing_table_idx_2ga_n_default[DELTA_SWINGIDX_SIZE];
static u8 delta_swing_table_idx_2ga_p_8188e[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9};
static u8 delta_swing_table_idx_2ga_n_8188e[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11};
/* extern u32 ofdm_swing_table_92e[OFDM_TABLE_SIZE_92E];
* extern u8 cck_swing_table_ch1_ch13_92e[CCK_TABLE_SIZE_92E][8];
* extern u8 cck_swing_table_ch14_92e[CCK_TABLE_SIZE_92E][8]; */
#ifdef CONFIG_WLAN_HAL_8192EE
#define OFDM_TABLE_SIZE_92E 54
#define CCK_TABLE_SIZE_92E 54
extern u32 ofdm_swing_table_92e[OFDM_TABLE_SIZE_92E];
extern u8 cck_swing_table_ch1_ch13_92e[CCK_TABLE_SIZE_92E][8];
extern u8 cck_swing_table_ch14_92e[CCK_TABLE_SIZE_92E][8];
#endif
#define OFDM_TABLE_SIZE_8812 43
#define AVG_THERMAL_NUM_8812 4
#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 ||\
RTL8821C_SUPPORT == 1 || RTL8198F_SUPPORT == 1 ||\
RTL8814B_SUPPORT == 1)
extern u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE];
#elif(ODM_IC_11AC_SERIES_SUPPORT)
extern unsigned int ofdm_swing_table_8812[OFDM_TABLE_SIZE_8812];
#endif
extern u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D];
/* JJ ADD 20161014 */
extern u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B];
#define dm_check_txpowertracking odm_txpowertracking_check
struct iqk_matrix_regs_setting {
boolean is_iqk_done;
s32 value[1][iqk_matrix_reg_num];
};
struct dm_rf_calibration_struct {
/* for tx power tracking */
u32 rega24; /* for TempCCK */
s32 rege94;
s32 rege9c;
s32 regeb4;
s32 regebc;
/* u8 is_txpowertracking; */
u8 tx_powercount;
boolean is_txpowertracking_init;
boolean is_txpowertracking;
u8 txpowertrack_control; /* for mp mode, turn off txpwrtracking as default */
u8 tm_trigger;
u8 internal_pa_5g[2]; /* pathA / pathB */
u8 thermal_meter[2]; /* thermal_meter, index 0 for RFIC0, and 1 for RFIC1 */
u8 thermal_value;
u8 thermal_value_lck;
u8 thermal_value_iqk;
s8 thermal_value_delta; /* delta of thermal_value and efuse thermal */
u8 thermal_value_avg[AVG_THERMAL_NUM];
u8 thermal_value_avg_index;
u8 thermal_value_rx_gain;
u8 thermal_value_crystal;
u8 thermal_value_dpk_store;
u8 thermal_value_dpk_track;
boolean txpowertracking_in_progress;
boolean is_reloadtxpowerindex;
u8 is_rf_pi_enable;
u32 txpowertracking_callback_cnt; /* cosa add for debug */
u8 is_cck_in_ch14;
u8 CCK_index;
u8 OFDM_index[MAX_RF_PATH];
s8 power_index_offset;
s8 delta_power_index;
s8 delta_power_index_last;
boolean is_tx_power_changed;
struct iqk_matrix_regs_setting iqk_matrix_reg_setting[IQK_MATRIX_SETTINGS_NUM];
u8 delta_lck;
u8 delta_swing_table_idx_2g_cck_a_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_a_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_b_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_b_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_c_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_c_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_d_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_d_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2ga_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2ga_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gb_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gb_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gc_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gc_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gd_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gd_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5ga_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5ga_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gb_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gb_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gc_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gc_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gd_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gd_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_tssi_table_2g_cck_a[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2g_cck_b[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2g_cck_c[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2g_cck_d[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2ga[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2gb[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2gc[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2gd[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_5ga[BAND_NUM][DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_5gb[BAND_NUM][DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_5gc[BAND_NUM][DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_5gd[BAND_NUM][DELTA_SWINTSSI_SIZE];
s8 delta_swing_table_xtal_p[DELTA_SWINGIDX_SIZE];
s8 delta_swing_table_xtal_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2ga_p_8188e[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2ga_n_8188e[DELTA_SWINGIDX_SIZE];
u8 bb_swing_idx_ofdm[MAX_RF_PATH];
u8 bb_swing_idx_ofdm_current;
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
u8 bb_swing_idx_ofdm_base[MAX_RF_PATH];
#else
u8 bb_swing_idx_ofdm_base;
#endif
boolean bb_swing_flag_ofdm;
u8 bb_swing_idx_cck;
u8 bb_swing_idx_cck_current;
u8 bb_swing_idx_cck_base;
u8 default_ofdm_index;
u8 default_cck_index;
boolean bb_swing_flag_cck;
s8 absolute_ofdm_swing_idx[MAX_RF_PATH];
s8 remnant_ofdm_swing_idx[MAX_RF_PATH];
s8 absolute_cck_swing_idx[MAX_RF_PATH];
s8 remnant_cck_swing_idx;
s8 modify_tx_agc_value; /*Remnat compensate value at tx_agc */
boolean modify_tx_agc_flag_path_a;
boolean modify_tx_agc_flag_path_b;
boolean modify_tx_agc_flag_path_c;
boolean modify_tx_agc_flag_path_d;
boolean modify_tx_agc_flag_path_a_cck;
boolean modify_tx_agc_flag_path_b_cck;
s8 kfree_offset[MAX_RF_PATH];
/* -------------------------------------------------------------------- */
/* for IQK */
u32 regc04;
u32 reg874;
u32 regc08;
u32 regb68;
u32 regb6c;
u32 reg870;
u32 reg860;
u32 reg864;
boolean is_iqk_initialized;
boolean is_lck_in_progress;
boolean is_antenna_detected;
boolean is_need_iqk;
boolean is_iqk_in_progress;
boolean is_iqk_pa_off;
u8 delta_iqk;
u32 ADDA_backup[IQK_ADDA_REG_NUM];
u32 IQK_MAC_backup[IQK_MAC_REG_NUM];
u32 IQK_BB_backup_recover[9];
u32 IQK_BB_backup[IQK_BB_REG_NUM];
u32 tx_iqc_8723b[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */
u32 rx_iqc_8723b[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */
u32 tx_iqc_8703b[3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
u32 rx_iqc_8703b[2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/
u64 iqk_start_time;
u64 iqk_total_progressing_time;
u64 iqk_progressing_time;
u64 lck_progressing_time;
u32 lok_result;
u8 iqk_step;
u8 kcount;
u8 retry_count[4][2]; /* [4]: path ABCD, [2] TXK, RXK */
boolean is_mp_mode;
/* for APK */
u32 ap_koutput[2][2]; /* path A/B; output1_1a/output1_2a */
u8 is_ap_kdone;
u8 is_apk_thermal_meter_ignore;
u8 is_dp_done;
#if 0 /*move below members to halrf_dpk.h*/
u8 is_dp_path_aok;
u8 is_dp_path_bok;
u8 is_dp_path_cok;
u8 is_dp_path_dok;
u8 dp_path_a_result[3];
u8 dp_path_b_result[3];
u8 dp_path_c_result[3];
u8 dp_path_d_result[3];
boolean is_dpk_enable;
u32 txrate[11];
u8 pwsf_2g_a[3];
u8 pwsf_2g_b[3];
u8 pwsf_2g_c[3];
u8 pwsf_2g_d[3];
u32 lut_2g_even_a[3][64];
u32 lut_2g_odd_a[3][64];
u32 lut_2g_even_b[3][64];
u32 lut_2g_odd_b[3][64];
u32 lut_2g_even_c[3][64];
u32 lut_2g_odd_c[3][64];
u32 lut_2g_even_d[3][64];
u32 lut_2g_odd_d[3][64];
u1Byte is_5g_pdk_a_ok;
u1Byte is_5g_pdk_b_ok;
u1Byte is_5g_pdk_c_ok;
u1Byte is_5g_pdk_d_ok;
u1Byte pwsf_5g_a[9];
u1Byte pwsf_5g_b[9];
u1Byte pwsf_5g_c[9];
u1Byte pwsf_5g_d[9];
u4Byte lut_5g_even_a[9][16];
u4Byte lut_5g_odd_a[9][16];
u4Byte lut_5g_even_b[9][16];
u4Byte lut_5g_odd_b[9][16];
u4Byte lut_5g_even_c[9][16];
u4Byte lut_5g_odd_c[9][16];
u4Byte lut_5g_even_d[9][16];
u4Byte lut_5g_odd_d[9][16];
u8 thermal_value_dpk;
u8 thermal_value_dpk_avg[AVG_THERMAL_NUM_DPK];
u8 thermal_value_dpk_avg_index;
#endif
s8 modify_tx_agc_value_ofdm;
s8 modify_tx_agc_value_cck;
/*Add by Yuchen for Kfree Phydm*/
u8 reg_rf_kfree_enable; /*for registry*/
u8 rf_kfree_enable; /*for efuse enable check*/
u32 tx_lok[2];
};
void
odm_txpowertracking_check_ap(
void *dm_void
);
void
odm_txpowertracking_check(
void *dm_void
);
void
odm_txpowertracking_thermal_meter_init(
void *dm_void
);
void
odm_txpowertracking_init(
void *dm_void
);
void
odm_txpowertracking_check_mp(
void *dm_void
);
void
odm_txpowertracking_check_ce(
void *dm_void
);
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
void
odm_txpowertracking_callback_thermal_meter92c(
void *adapter
);
void
odm_txpowertracking_callback_rx_gain_thermal_meter92d(
void *adapter
);
void
odm_txpowertracking_callback_thermal_meter92d(
void *adapter
);
void
odm_txpowertracking_direct_call92c(
void *adapter
);
void
odm_txpowertracking_thermal_meter_check(
void *adapter
);
#endif
#endif /*#ifndef __HALRF_POWER_TRACKING_H__*/

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALRF_POWERTRACKING_H__
#define __HALRF_POWERTRACKING_H__
#define DPK_DELTA_MAPPING_NUM 13
#define index_mapping_HP_NUM 15
#define OFDM_TABLE_SIZE 43
#define CCK_TABLE_SIZE 33
#define CCK_TABLE_SIZE_88F 21
#define TXSCALE_TABLE_SIZE 37
#define CCK_TABLE_SIZE_8723D 41
/*@JJ ADD 20161014 */
#define CCK_TABLE_SIZE_8710B 41
#define CCK_TABLE_SIZE_8192F 41
#define TXPWR_TRACK_TABLE_SIZE 30
#define DELTA_SWINGIDX_SIZE 30
#define DELTA_SWINTSSI_SIZE 61
#define BAND_NUM 4
#define AVG_THERMAL_NUM 8
#define IQK_MAC_REG_NUM 4
#define IQK_ADDA_REG_NUM 16
#define IQK_BB_REG_NUM_MAX 10
#define IQK_BB_REG_NUM 9
#define iqk_matrix_reg_num 8
#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
#else
/* Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G */
#define IQK_MATRIX_SETTINGS_NUM (14 + 24 + 21)
#endif
extern u32 ofdm_swing_table[OFDM_TABLE_SIZE];
extern u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8];
extern u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8];
extern u32 ofdm_swing_table_new[OFDM_TABLE_SIZE];
extern u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8];
extern u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8];
extern u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16];
extern u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16];
extern u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16];
extern u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D];
/*@JJ ADD 20161014 */
extern u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B];
extern u32 cck_swing_table_ch1_ch14_8192f[CCK_TABLE_SIZE_8192F];
extern u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE];
/*@<20121018, Kordan> In case fail to read TxPowerTrack.txt */
/* we use the table of 88E as the default table. */
#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
#else
extern u8 delta_swing_table_idx_2ga_p_8188e[];
extern u8 delta_swing_table_idx_2ga_n_8188e[];
#endif
#define dm_check_txpowertracking odm_txpowertracking_check
struct iqk_matrix_regs_setting {
boolean is_iqk_done;
s32 value[3][iqk_matrix_reg_num];
boolean is_bw_iqk_result_saved[3];
};
struct dm_rf_calibration_struct {
/* for tx power tracking */
u32 rega24; /* for TempCCK */
s32 rege94;
s32 rege9c;
s32 regeb4;
s32 regebc;
u8 tx_powercount;
boolean is_txpowertracking_init;
boolean is_txpowertracking;
/* for mp mode, turn off txpwrtracking as default */
u8 txpowertrack_control;
u8 tm_trigger;
u8 internal_pa_5g[2]; /* pathA / pathB */
/* thermal_meter, index 0 for RFIC0, and 1 for RFIC1 */
u8 thermal_meter[2];
u8 thermal_value;
u8 thermal_value_lck;
u8 thermal_value_iqk;
s8 thermal_value_delta; /* delta of thermal_value and efuse thermal */
u8 thermal_value_dpk;
u8 thermal_value_avg[AVG_THERMAL_NUM];
u8 thermal_value_avg_index;
u8 thermal_value_rx_gain;
u8 thermal_value_crystal;
u8 thermal_value_dpk_store;
u8 thermal_value_dpk_track;
boolean txpowertracking_in_progress;
boolean is_reloadtxpowerindex;
u8 is_rf_pi_enable;
u32 txpowertracking_callback_cnt; /* cosa add for debug */
/*@---------------------- Tx power Tracking ---------------------- */
u8 is_cck_in_ch14;
u8 CCK_index;
u8 OFDM_index[MAX_RF_PATH];
s8 power_index_offset[MAX_RF_PATH];
s8 delta_power_index[MAX_RF_PATH];
s8 delta_power_index_last[MAX_RF_PATH];
boolean is_tx_power_changed;
s8 xtal_offset;
s8 xtal_offset_last;
u8 xtal_offset_eanble;
struct iqk_matrix_regs_setting
iqk_matrix_reg_setting[IQK_MATRIX_SETTINGS_NUM];
u8 delta_lck;
s8 bb_swing_diff_2g, bb_swing_diff_5g; /* Unit: dB */
u8 delta_swing_table_idx_2g_cck_a_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_a_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_b_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_b_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_c_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_c_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_d_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_d_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2ga_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2ga_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gb_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gb_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gc_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gc_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gd_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gd_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5ga_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5ga_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gb_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gb_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gc_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gc_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gd_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gd_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_tssi_table_2g_cck_a[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2g_cck_b[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2g_cck_c[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2g_cck_d[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2ga[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2gb[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2gc[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2gd[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_5ga[BAND_NUM][DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_5gb[BAND_NUM][DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_5gc[BAND_NUM][DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_5gd[BAND_NUM][DELTA_SWINTSSI_SIZE];
s8 delta_swing_table_xtal_p[DELTA_SWINGIDX_SIZE];
s8 delta_swing_table_xtal_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2ga_p_8188e[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2ga_n_8188e[DELTA_SWINGIDX_SIZE];
u8 bb_swing_idx_ofdm[MAX_RF_PATH];
u8 bb_swing_idx_ofdm_current;
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
u8 bb_swing_idx_ofdm_base[MAX_RF_PATH];
#else
u8 bb_swing_idx_ofdm_base;
#endif
boolean default_bb_swing_index_flag;
boolean bb_swing_flag_ofdm;
u8 bb_swing_idx_cck;
u8 bb_swing_idx_cck_current;
u8 bb_swing_idx_cck_base;
u8 default_ofdm_index;
u8 default_cck_index;
boolean bb_swing_flag_cck;
s8 absolute_ofdm_swing_idx[MAX_RF_PATH];
s8 remnant_ofdm_swing_idx[MAX_RF_PATH];
s8 absolute_cck_swing_idx[MAX_RF_PATH];
s8 remnant_cck_swing_idx;
s8 modify_tx_agc_value; /*Remnat compensate value at tx_agc */
boolean modify_tx_agc_flag_path_a;
boolean modify_tx_agc_flag_path_b;
boolean modify_tx_agc_flag_path_c;
boolean modify_tx_agc_flag_path_d;
boolean modify_tx_agc_flag_path_a_cck;
boolean modify_tx_agc_flag_path_b_cck;
s8 kfree_offset[MAX_RF_PATH];
/*@----------------------------------------------------------------- */
/* for IQK */
u32 regc04;
u32 reg874;
u32 regc08;
u32 regb68;
u32 regb6c;
u32 reg870;
u32 reg860;
u32 reg864;
boolean is_iqk_initialized;
boolean is_lck_in_progress;
boolean is_antenna_detected;
boolean is_need_iqk;
boolean is_iqk_in_progress;
boolean is_iqk_pa_off;
u8 delta_iqk;
u32 ADDA_backup[IQK_ADDA_REG_NUM];
u32 IQK_MAC_backup[IQK_MAC_REG_NUM];
u32 IQK_BB_backup_recover[9];
u32 IQK_BB_backup[IQK_BB_REG_NUM];
/* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */
u32 tx_iqc_8723b[2][3][2];
/* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */
u32 rx_iqc_8723b[2][2][2];
/* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */
u32 tx_iqc_8703b[3][2];
/* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */
u32 rx_iqc_8703b[2][2];
/* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */
u32 tx_iqc_8723d[2][3][2];
/* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */
u32 rx_iqc_8723d[2][2][2];
/* JJ ADD 20161014 */
/* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */
u32 tx_iqc_8710b[2][3][2];
/* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */
u32 rx_iqc_8710b[2][2][2];
u8 iqk_step;
u8 kcount;
u8 retry_count[4][2]; /* [4]: path ABCD, [2] TXK, RXK */
boolean is_mp_mode;
/*@<James> IQK time measurement */
u64 iqk_start_time;
u64 iqk_progressing_time;
u64 iqk_total_progressing_time;
u64 lck_progressing_time;
u32 lok_result;
/* for APK */
u32 ap_koutput[2][2]; /* path A/B; output1_1a/output1_2a */
u8 is_ap_kdone;
u8 is_apk_thermal_meter_ignore;
/* DPK */
boolean is_dpk_fail;
u8 is_dp_done;
u8 is_dp_path_aok;
u8 is_dp_path_bok;
u32 tx_lok[2];
u32 dpk_tx_agc;
s32 dpk_gain;
u32 dpk_thermal[4];
s8 modify_tx_agc_value_ofdm;
s8 modify_tx_agc_value_cck;
/*@Add by Yuchen for Kfree Phydm*/
u8 reg_rf_kfree_enable; /*for registry*/
u8 rf_kfree_enable; /*for efuse enable check*/
};
void odm_txpowertracking_check(void *dm_void);
void odm_txpowertracking_init(void *dm_void);
void odm_txpowertracking_check_ap(void *dm_void);
void odm_txpowertracking_thermal_meter_init(void *dm_void);
void odm_txpowertracking_init(void *dm_void);
void odm_txpowertracking_check_mp(void *dm_void);
void odm_txpowertracking_check_ce(void *dm_void);
void odm_txpowertracking_direct_ce(void *dm_void);
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
void odm_txpowertracking_callback_thermal_meter92c(
void *adapter);
void odm_txpowertracking_callback_rx_gain_thermal_meter92d(
void *adapter);
void odm_txpowertracking_callback_thermal_meter92d(
void *adapter);
void odm_txpowertracking_direct_call92c(
void *adapter);
void odm_txpowertracking_thermal_meter_check(
void *adapter);
#endif
#endif /*__HALRF_POWER_TRACKING_H__*/

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALRF_POWERTRACKING_H__
#define __HALRF_POWERTRACKING_H__
#define DPK_DELTA_MAPPING_NUM 13
#define index_mapping_HP_NUM 15
#define OFDM_TABLE_SIZE 43
#define CCK_TABLE_SIZE 33
#define CCK_TABLE_SIZE_88F 21
#define TXSCALE_TABLE_SIZE 37
#define CCK_TABLE_SIZE_8723D 41
/* JJ ADD 20161014 */
#define CCK_TABLE_SIZE_8710B 41
#define CCK_TABLE_SIZE_8192F 41
#define CCK_TABLE_SIZE_8721D 41
#define TXPWR_TRACK_TABLE_SIZE 30
#define DELTA_SWINGIDX_SIZE 30
#define DELTA_SWINTSSI_SIZE 61
#define BAND_NUM 4
#define AVG_THERMAL_NUM 8
#define IQK_MAC_REG_NUM 4
#define IQK_ADDA_REG_NUM 16
#define IQK_BB_REG_NUM_MAX 10
#define IQK_BB_REG_NUM 9
#define iqk_matrix_reg_num 8
#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
#else
#define IQK_MATRIX_SETTINGS_NUM (14+24+21) /* Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G */
#endif
extern u32 ofdm_swing_table[OFDM_TABLE_SIZE];
extern u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8];
extern u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8];
extern u32 ofdm_swing_table_new[OFDM_TABLE_SIZE];
extern u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8];
extern u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8];
extern u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16];
extern u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16];
extern u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16];
extern u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D];
/* JJ ADD 20161014 */
extern u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B];
extern u32 cck_swing_table_ch1_ch14_8192f[CCK_TABLE_SIZE_8192F];
extern u32 cck_swing_table_ch1_ch14_8721d[CCK_TABLE_SIZE_8721D];
extern u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE];
/* <20121018, Kordan> In case fail to read TxPowerTrack.txt, we use the table of 88E as the default table. */
#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
#else
static u8 delta_swing_table_idx_2ga_p_8188e[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9};
static u8 delta_swing_table_idx_2ga_n_8188e[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11};
#endif
void
odm_txpowertracking_init(
void *dm_void
);
#define dm_check_txpowertracking odm_txpowertracking_check
struct iqk_matrix_regs_setting {
boolean is_iqk_done;
s32 value[3][iqk_matrix_reg_num];
boolean is_bw_iqk_result_saved[3];
};
struct dm_rf_calibration_struct {
/* for tx power tracking */
u32 rega24; /* for TempCCK */
s32 rege94;
s32 rege9c;
s32 regeb4;
s32 regebc;
u8 tx_powercount;
boolean is_txpowertracking_init;
boolean is_txpowertracking;
u8 txpowertrack_control; /* for mp mode, turn off txpwrtracking as default */
u8 tm_trigger;
u8 internal_pa_5g[2]; /* pathA / pathB */
u8 thermal_meter[2]; /* thermal_meter, index 0 for RFIC0, and 1 for RFIC1 */
u8 thermal_value;
u8 thermal_value_lck;
u8 thermal_value_iqk;
s8 thermal_value_delta; /* delta of thermal_value and efuse thermal */
u8 thermal_value_dpk;
u8 thermal_value_avg[AVG_THERMAL_NUM];
u8 thermal_value_avg_index;
u8 thermal_value_rx_gain;
u8 thermal_value_crystal;
u8 thermal_value_dpk_store;
u8 thermal_value_dpk_track;
boolean txpowertracking_in_progress;
boolean is_reloadtxpowerindex;
u8 is_rf_pi_enable;
u32 txpowertracking_callback_cnt; /* cosa add for debug */
/* ------------------------- Tx power Tracking ------------------------- */
u8 is_cck_in_ch14;
u8 CCK_index;
u8 OFDM_index[MAX_RF_PATH];
s8 power_index_offset[MAX_RF_PATH];
s8 delta_power_index[MAX_RF_PATH];
s8 delta_power_index_last[MAX_RF_PATH];
boolean is_tx_power_changed;
s8 xtal_offset;
s8 xtal_offset_last;
struct iqk_matrix_regs_setting iqk_matrix_reg_setting[IQK_MATRIX_SETTINGS_NUM];
u8 delta_lck;
s8 bb_swing_diff_2g, bb_swing_diff_5g; /* Unit: dB */
u8 delta_swing_table_idx_2g_cck_a_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_a_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_b_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_b_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_c_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_c_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_d_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_d_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2ga_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2ga_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gb_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gb_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gc_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gc_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gd_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gd_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5ga_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5ga_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gb_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gb_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gc_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gc_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gd_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gd_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_tssi_table_2g_cck_a[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2g_cck_b[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2g_cck_c[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2g_cck_d[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2ga[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2gb[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2gc[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2gd[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_5ga[BAND_NUM][DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_5gb[BAND_NUM][DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_5gc[BAND_NUM][DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_5gd[BAND_NUM][DELTA_SWINTSSI_SIZE];
s8 delta_swing_table_xtal_p[DELTA_SWINGIDX_SIZE];
s8 delta_swing_table_xtal_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2ga_p_8188e[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2ga_n_8188e[DELTA_SWINGIDX_SIZE];
u8 bb_swing_idx_ofdm[MAX_RF_PATH];
u8 bb_swing_idx_ofdm_current;
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE | ODM_IOT))
u8 bb_swing_idx_ofdm_base[MAX_RF_PATH];
#else
u8 bb_swing_idx_ofdm_base;
#endif
boolean default_bb_swing_index_flag;
boolean bb_swing_flag_ofdm;
u8 bb_swing_idx_cck;
u8 bb_swing_idx_cck_current;
u8 bb_swing_idx_cck_base;
u8 default_ofdm_index;
u8 default_cck_index;
boolean bb_swing_flag_cck;
s8 absolute_ofdm_swing_idx[MAX_RF_PATH];
s8 remnant_ofdm_swing_idx[MAX_RF_PATH];
s8 absolute_cck_swing_idx[MAX_RF_PATH];
s8 remnant_cck_swing_idx;
s8 modify_tx_agc_value; /*Remnat compensate value at tx_agc */
boolean modify_tx_agc_flag_path_a;
boolean modify_tx_agc_flag_path_b;
boolean modify_tx_agc_flag_path_c;
boolean modify_tx_agc_flag_path_d;
boolean modify_tx_agc_flag_path_a_cck;
boolean modify_tx_agc_flag_path_b_cck;
s8 kfree_offset[MAX_RF_PATH];
/* -------------------------------------------------------------------- */
/* for IQK */
u32 regc04;
u32 reg874;
u32 regc08;
u32 regb68;
u32 regb6c;
u32 reg870;
u32 reg860;
u32 reg864;
boolean is_iqk_initialized;
boolean is_lck_in_progress;
boolean is_antenna_detected;
boolean is_need_iqk;
boolean is_iqk_in_progress;
boolean is_iqk_pa_off;
u8 delta_iqk;
u32 ADDA_backup[IQK_ADDA_REG_NUM];
u32 IQK_MAC_backup[IQK_MAC_REG_NUM];
u32 IQK_BB_backup_recover[9];
u32 IQK_BB_backup[IQK_BB_REG_NUM];
u32 tx_iqc_8723b[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */
u32 rx_iqc_8723b[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */
u32 tx_iqc_8703b[3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
u32 rx_iqc_8703b[2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/
u32 tx_iqc_8723d[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
u32 rx_iqc_8723d[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/
/* JJ ADD 20161014 */
u32 tx_iqc_8710b[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
u32 rx_iqc_8710b[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/
u8 iqk_step;
u8 kcount;
u8 retry_count[4][2]; /* [4]: path ABCD, [2] TXK, RXK */
boolean is_mp_mode;
/* <James> IQK time measurement */
u32 iqk_start_time;
u32 iqk_progressing_time;
u32 iqk_total_progressing_time;
u32 lck_progressing_time;
u32 lok_result;
/* for APK */
u32 ap_koutput[2][2]; /* path A/B; output1_1a/output1_2a */
u8 is_ap_kdone;
u8 is_apk_thermal_meter_ignore;
/* DPK */
boolean is_dpk_fail;
u8 is_dp_done;
u8 is_dp_path_aok;
u8 is_dp_path_bok;
u32 tx_lok[2];
u32 dpk_tx_agc;
s32 dpk_gain;
u32 dpk_thermal[4];
s8 modify_tx_agc_value_ofdm;
s8 modify_tx_agc_value_cck;
/*Add by Yuchen for Kfree Phydm*/
u8 reg_rf_kfree_enable; /*for registry*/
u8 rf_kfree_enable; /*for efuse enable check*/
};
void
odm_txpowertracking_check(
void *dm_void
);
void
odm_txpowertracking_check_ap(
void *dm_void
);
void
odm_txpowertracking_thermal_meter_init(
void *dm_void
);
void
odm_txpowertracking_check_mp(
void *dm_void
);
void
odm_txpowertracking_check_iot(
void *dm_void
);
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
void
odm_txpowertracking_callback_thermal_meter92c(
void *adapter
);
void
odm_txpowertracking_callback_rx_gain_thermal_meter92d(
void *adapter
);
void
odm_txpowertracking_callback_thermal_meter92d(
void *adapter
);
void
odm_txpowertracking_direct_call92c(
void *adapter
);
void
odm_txpowertracking_thermal_meter_check(
void *adapter
);
#endif
#endif /*#ifndef __HALRF_POWER_TRACKING_H__*/

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hal/phydm/halrf/halrf_powertracking_win.c Normal file
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hal/phydm/halrf/halrf_powertracking_win.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __HALRF_POWERTRACKING_H__
#define __HALRF_POWERTRACKING_H__
#define DPK_DELTA_MAPPING_NUM 13
#define index_mapping_HP_NUM 15
#define TXSCALE_TABLE_SIZE 37
#define OFDM_TABLE_SIZE 43
#define CCK_TABLE_SIZE 33
#define CCK_TABLE_SIZE_8723D 41
#define TXPWR_TRACK_TABLE_SIZE 30
#define DELTA_SWINGIDX_SIZE 30
#define DELTA_SWINTSSI_SIZE 61
#define BAND_NUM 3
#define MAX_RF_PATH 4
#define CCK_TABLE_SIZE_88F 21
/* JJ ADD 20161014 */
#define CCK_TABLE_SIZE_8710B 41
#define CCK_TABLE_SIZE_8192F 41
#define dm_check_txpowertracking odm_txpowertracking_check
#define IQK_MATRIX_SETTINGS_NUM (14+24+21) /* Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G */
#define AVG_THERMAL_NUM 8
#define iqk_matrix_reg_num 8
#define IQK_MAC_REG_NUM 4
#define IQK_ADDA_REG_NUM 16
#define IQK_BB_REG_NUM 9
extern u32 ofdm_swing_table[OFDM_TABLE_SIZE];
extern u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8];
extern u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8];
extern u32 ofdm_swing_table_new[OFDM_TABLE_SIZE];
extern u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8];
extern u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8];
extern u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16];
extern u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16];
extern u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16];
extern u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D];
/* JJ ADD 20161014 */
extern u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B];
extern u32 cck_swing_table_ch1_ch14_8192f[CCK_TABLE_SIZE_8192F];
extern u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE];
/* <20121018, Kordan> In case fail to read TxPowerTrack.txt, we use the table of 88E as the default table. */
static u8 delta_swing_table_idx_2ga_p_8188e[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9};
static u8 delta_swing_table_idx_2ga_n_8188e[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11};
void
odm_txpowertracking_check(
void *dm_void
);
void
odm_txpowertracking_check_ap(
void *dm_void
);
void
odm_txpowertracking_thermal_meter_init(
void *dm_void
);
void
odm_txpowertracking_init(
void *dm_void
);
void
odm_txpowertracking_check_mp(
void *dm_void
);
void
odm_txpowertracking_check_ce(
void *dm_void
);
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
void
odm_txpowertracking_thermal_meter_check(
void *adapter
);
#endif
struct iqk_matrix_regs_setting {
boolean is_iqk_done;
s32 value[3][iqk_matrix_reg_num];
boolean is_bw_iqk_result_saved[3];
};
struct dm_rf_calibration_struct {
/* for tx power tracking */
u32 rega24; /* for TempCCK */
s32 rege94;
s32 rege9c;
s32 regeb4;
s32 regebc;
/* u8 is_txpowertracking; */
u8 tx_powercount;
boolean is_txpowertracking_init;
boolean is_txpowertracking;
u8 txpowertrack_control; /* for mp mode, turn off txpwrtracking as default */
u8 tm_trigger;
u8 internal_pa_5g[2]; /* pathA / pathB */
u8 thermal_meter[2]; /* thermal_meter, index 0 for RFIC0, and 1 for RFIC1 */
u8 thermal_value;
u8 thermal_value_lck;
u8 thermal_value_iqk;
u8 thermal_value_dpk;
s8 thermal_value_delta; /* delta of thermal_value and efuse thermal */
u8 thermal_value_avg[AVG_THERMAL_NUM];
u8 thermal_value_avg_index;
u8 thermal_value_rx_gain;
boolean is_reloadtxpowerindex;
u8 is_rf_pi_enable;
u32 txpowertracking_callback_cnt; /* cosa add for debug */
/* ------------------------- Tx power Tracking ------------------------- */
u8 is_cck_in_ch14;
u8 CCK_index;
u8 OFDM_index[MAX_RF_PATH];
s8 power_index_offset[MAX_RF_PATH];
s8 delta_power_index[MAX_RF_PATH];
s8 delta_power_index_last[MAX_RF_PATH];
boolean is_tx_power_changed;
s8 xtal_offset;
s8 xtal_offset_last;
struct iqk_matrix_regs_setting iqk_matrix_reg_setting[IQK_MATRIX_SETTINGS_NUM];
u8 delta_lck;
s8 bb_swing_diff_2g, bb_swing_diff_5g; /* Unit: dB */
u8 delta_swing_table_idx_2g_cck_a_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_a_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_b_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_b_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_c_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_c_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_d_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_d_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2ga_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2ga_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gb_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gb_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gc_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gc_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gd_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gd_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5ga_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5ga_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gb_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gb_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gc_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gc_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gd_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gd_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_tssi_table_2g_cck_a[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2g_cck_b[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2g_cck_c[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2g_cck_d[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2ga[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2gb[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2gc[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2gd[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_5ga[BAND_NUM][DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_5gb[BAND_NUM][DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_5gc[BAND_NUM][DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_5gd[BAND_NUM][DELTA_SWINTSSI_SIZE];
s8 delta_swing_table_xtal_p[DELTA_SWINGIDX_SIZE];
s8 delta_swing_table_xtal_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2ga_p_8188e[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2ga_n_8188e[DELTA_SWINGIDX_SIZE];
u8 bb_swing_idx_ofdm[MAX_RF_PATH];
u8 bb_swing_idx_ofdm_current;
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
u8 bb_swing_idx_ofdm_base[MAX_RF_PATH];
#else
u8 bb_swing_idx_ofdm_base;
#endif
boolean default_bb_swing_index_flag;
boolean bb_swing_flag_ofdm;
u8 bb_swing_idx_cck;
u8 bb_swing_idx_cck_current;
u8 bb_swing_idx_cck_base;
u8 default_ofdm_index;
u8 default_cck_index;
boolean bb_swing_flag_cck;
s8 absolute_ofdm_swing_idx[MAX_RF_PATH];
s8 remnant_ofdm_swing_idx[MAX_RF_PATH];
s8 absolute_cck_swing_idx[MAX_RF_PATH];
s8 remnant_cck_swing_idx;
s8 modify_tx_agc_value; /*Remnat compensate value at tx_agc */
boolean modify_tx_agc_flag_path_a;
boolean modify_tx_agc_flag_path_b;
boolean modify_tx_agc_flag_path_c;
boolean modify_tx_agc_flag_path_d;
boolean modify_tx_agc_flag_path_a_cck;
boolean modify_tx_agc_flag_path_b_cck;
s8 kfree_offset[MAX_RF_PATH];
/* -------------------------------------------------------------------- */
/* for IQK */
u32 regc04;
u32 reg874;
u32 regc08;
u32 regb68;
u32 regb6c;
u32 reg870;
u32 reg860;
u32 reg864;
boolean is_iqk_initialized;
boolean is_lck_in_progress;
boolean is_antenna_detected;
boolean is_need_iqk;
boolean is_iqk_in_progress;
boolean is_iqk_pa_off;
u8 delta_iqk;
u32 ADDA_backup[IQK_ADDA_REG_NUM];
u32 IQK_MAC_backup[IQK_MAC_REG_NUM];
u32 IQK_BB_backup_recover[9];
u32 IQK_BB_backup[IQK_BB_REG_NUM];
u32 tx_iqc_8723b[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */
u32 rx_iqc_8723b[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */
u32 tx_iqc_8703b[3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
u32 rx_iqc_8703b[2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/
u32 tx_iqc_8723d[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
u32 rx_iqc_8723d[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/
/* JJ ADD 20161014 */
u32 tx_iqc_8710b[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
u32 rx_iqc_8710b[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/
u64 iqk_start_time;
u64 iqk_total_progressing_time;
u64 iqk_progressing_time;
u64 lck_progressing_time;
u32 lok_result;
u8 iqk_step;
u8 kcount;
u8 retry_count[4][2]; /* [4]: path ABCD, [2] TXK, RXK */
boolean is_mp_mode;
/* for APK */
u32 ap_koutput[2][2]; /* path A/B; output1_1a/output1_2a */
u8 is_ap_kdone;
u8 is_apk_thermal_meter_ignore;
/* DPK */
boolean is_dpk_fail;
u8 is_dp_done;
u8 is_dp_path_aok;
u8 is_dp_path_bok;
u32 tx_lok[2];
u32 dpk_tx_agc;
s32 dpk_gain;
u32 dpk_thermal[4];
s8 modify_tx_agc_value_ofdm;
s8 modify_tx_agc_value_cck;
/*Add by Yuchen for Kfree Phydm*/
u8 reg_rf_kfree_enable; /*for registry*/
u8 rf_kfree_enable; /*for efuse enable check*/
};
#endif /*#ifndef __HALRF_POWER_TRACKING_H__*/

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
/*@===========================================================
* include files
*============================================================
*/
#include "mp_precomp.h"
#include "phydm_precomp.h"
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
u64 _sqrt(u64 x)
{
u64 i = 0;
u64 j = x / 2 + 1;
while (i <= j) {
u64 mid = (i + j) / 2;
u64 sq = mid * mid;
if (sq == x)
return mid;
else if (sq < x)
i = mid + 1;
else
j = mid - 1;
}
return j;
}
u32 halrf_get_psd_data(
struct dm_struct *dm,
u32 point)
{
struct _hal_rf_ *rf = &(dm->rf_table);
struct _halrf_psd_data *psd = &(rf->halrf_psd_data);
u32 psd_val = 0, psd_reg, psd_report, psd_point, psd_start, i, delay_time;
#if (DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)
if (dm->support_interface == ODM_ITRF_USB || dm->support_interface == ODM_ITRF_SDIO) {
if (psd->average == 0)
delay_time = 100;
else
delay_time = 0;
}
#endif
#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
if (dm->support_interface == ODM_ITRF_PCIE) {
if (psd->average == 0)
delay_time = 1000;
else
delay_time = 100;
}
#endif
if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C)) {
psd_reg = R_0x910;
psd_report = R_0xf44;
} else {
psd_reg = R_0x808;
psd_report = R_0x8b4;
}
if (dm->support_ic_type & ODM_RTL8710B) {
psd_point = 0xeffffc00;
psd_start = 0x10000000;
} else {
psd_point = 0xffbffc00;
psd_start = 0x00400000;
}
psd_val = odm_get_bb_reg(dm, psd_reg, MASKDWORD);
psd_val &= psd_point;
psd_val |= point;
odm_set_bb_reg(dm, psd_reg, MASKDWORD, psd_val);
psd_val |= psd_start;
odm_set_bb_reg(dm, psd_reg, MASKDWORD, psd_val);
for (i = 0; i < delay_time; i++)
ODM_delay_us(1);
psd_val = odm_get_bb_reg(dm, psd_report, MASKDWORD);
if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8710B)) {
psd_val &= MASKL3BYTES;
psd_val = psd_val / 32;
} else {
psd_val &= MASKLWORD;
}
return psd_val;
}
void halrf_psd(
struct dm_struct *dm,
u32 point,
u32 start_point,
u32 stop_point,
u32 average)
{
struct _hal_rf_ *rf = &(dm->rf_table);
struct _halrf_psd_data *psd = &(rf->halrf_psd_data);
u32 i = 0, j = 0, k = 0;
u32 psd_reg, avg_org, point_temp, average_tmp, mode;
u64 data_tatal = 0, data_temp[64] = {0};
psd->buf_size = 256;
mode = average >> 16;
if (mode == 1)
average_tmp = average & 0xffff;
else if (mode == 2)
average_tmp = 1;
if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C))
psd_reg = R_0x910;
else
psd_reg = R_0x808;
#if 0
dbg_print("[PSD]point=%d, start_point=%d, stop_point=%d, average=%d, average_tmp=%d, buf_size=%d\n",
point, start_point, stop_point, average, average_tmp, psd->buf_size);
#endif
for (i = 0; i < psd->buf_size; i++)
psd->psd_data[i] = 0;
if (dm->support_ic_type & ODM_RTL8710B)
avg_org = odm_get_bb_reg(dm, psd_reg, 0x30000);
else
avg_org = odm_get_bb_reg(dm, psd_reg, 0x3000);
if (mode == 1) {
if (dm->support_ic_type & ODM_RTL8710B)
odm_set_bb_reg(dm, psd_reg, 0x30000, 0x1);
else
odm_set_bb_reg(dm, psd_reg, 0x3000, 0x1);
}
#if 0
if (avg_temp == 0)
avg = 1;
else if (avg_temp == 1)
avg = 8;
else if (avg_temp == 2)
avg = 16;
else if (avg_temp == 3)
avg = 32;
#endif
i = start_point;
while (i < stop_point) {
data_tatal = 0;
if (i >= point)
point_temp = i - point;
else
point_temp = i;
for (k = 0; k < average_tmp; k++) {
data_temp[k] = halrf_get_psd_data(dm, point_temp);
data_tatal = data_tatal + (data_temp[k] * data_temp[k]);
#if 0
if ((k % 20) == 0)
dbg_print("\n ");
dbg_print("0x%x ", data_temp[k]);
#endif
}
#if 0
/*dbg_print("\n");*/
#endif
data_tatal = ((data_tatal * 100) / average_tmp);
psd->psd_data[j] = (u32)_sqrt(data_tatal);
i++;
j++;
}
#if 0
for (i = 0; i < psd->buf_size; i++) {
if ((i % 20) == 0)
dbg_print("\n ");
dbg_print("0x%x ", psd->psd_data[i]);
}
dbg_print("\n\n");
#endif
if (dm->support_ic_type & ODM_RTL8710B)
odm_set_bb_reg(dm, psd_reg, 0x30000, avg_org);
else
odm_set_bb_reg(dm, psd_reg, 0x3000, avg_org);
}
u32 halrf_get_iqk_psd_data(
struct dm_struct *dm,
u32 point)
{
struct _hal_rf_ *rf = &(dm->rf_table);
struct _halrf_psd_data *psd = &(rf->halrf_psd_data);
u32 psd_val, psd_val1, psd_val2, psd_point, i, delay_time;
#if (DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)
if (dm->support_interface == ODM_ITRF_USB || dm->support_interface == ODM_ITRF_SDIO) {
delay_time = 0;
}
#endif
#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
if (dm->support_interface == ODM_ITRF_PCIE) {
delay_time = 150;
}
#endif
psd_point = odm_get_bb_reg(dm, R_0x1b2c, MASKDWORD);
psd_point &= 0xF000FFFF;
point &= 0xFFF;
psd_point = psd_point | (point << 16);
odm_set_bb_reg(dm, R_0x1b2c, MASKDWORD, psd_point);
odm_set_bb_reg(dm, R_0x1b34, MASKDWORD, 0x1);
odm_set_bb_reg(dm, R_0x1b34, MASKDWORD, 0x0);
for (i = 0; i < delay_time; i++)
ODM_delay_us(1);
odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x00250001);
psd_val1 = odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD);
psd_val1 = (psd_val1 & 0x07FF0000) >> 16;
odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x002e0001);
psd_val2 = odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD);
psd_val = (psd_val1 << 21) + (psd_val2 >> 11);
return psd_val;
}
void halrf_iqk_psd(
struct dm_struct *dm,
u32 point,
u32 start_point,
u32 stop_point,
u32 average)
{
struct _hal_rf_ *rf = &(dm->rf_table);
struct _halrf_psd_data *psd = &(rf->halrf_psd_data);
u32 i = 0, j = 0, k = 0;
u32 psd_reg, avg_org, point_temp, average_tmp, mode;
u64 data_tatal = 0, data_temp[64] = {0};
s32 point_8814B;
psd->buf_size = 256;
mode = average >> 16;
if (mode == 1)
average_tmp = average & 0xffff;
else if (mode == 2) {
if (dm->support_ic_type & ODM_RTL8814B)
average_tmp = average & 0xffff;
else
average_tmp = 1;
}
#if 0
DbgPrint("[PSD]point=%d, start_point=%d, stop_point=%d, average=0x%x, average_tmp=%d, buf_size=%d, mode=%d\n",
point, start_point, stop_point, average, average_tmp, psd->buf_size, mode);
#endif
for (i = 0; i < psd->buf_size; i++)
psd->psd_data[i] = 0;
i = start_point;
while (i < stop_point) {
data_tatal = 0;
if (i >= point)
point_temp = i - point;
else
{
if (dm->support_ic_type & ODM_RTL8814B)
{
point_8814B = i -point -1;
point_temp = point_8814B & 0xfff;
}
else
point_temp = i;
}
for (k = 0; k < average_tmp; k++) {
data_temp[k] = halrf_get_iqk_psd_data(dm, point_temp);
/*data_tatal = data_tatal + (data_temp[k] * data_temp[k]);*/
data_tatal = data_tatal + data_temp[k];
#if 0
if ((k % 20) == 0)
DbgPrint("\n ");
DbgPrint("0x%x ", data_temp[k]);
#endif
}
/*data_tatal = ((data_tatal * 100) / average_tmp);*/
/*psd->psd_data[j] = (u32)_sqrt(data_tatal);*/
psd->psd_data[j] = (u32)((data_tatal * 10) / average_tmp);
i++;
j++;
}
#if 0
DbgPrint("\n [iqk psd]psd result:\n");
for (i = 0; i < psd->buf_size; i++) {
if ((i % 20) == 0)
DbgPrint("\n ");
DbgPrint("0x%x ", psd->psd_data[i]);
}
DbgPrint("\n\n");
#endif
}
enum rt_status
halrf_psd_init(
struct dm_struct *dm)
{
enum rt_status ret_status = RT_STATUS_SUCCESS;
struct _hal_rf_ *rf = &(dm->rf_table);
struct _halrf_psd_data *psd = &(rf->halrf_psd_data);
if (psd->psd_progress) {
ret_status = RT_STATUS_PENDING;
} else {
psd->psd_progress = 1;
if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8814B))
halrf_iqk_psd(dm, psd->point, psd->start_point, psd->stop_point, psd->average);
else
halrf_psd(dm, psd->point, psd->start_point, psd->stop_point, psd->average);
psd->psd_progress = 0;
}
return ret_status;
}
enum rt_status
halrf_psd_query(
struct dm_struct *dm,
u32 *outbuf,
u32 buf_size)
{
enum rt_status ret_status = RT_STATUS_SUCCESS;
struct _hal_rf_ *rf = &(dm->rf_table);
struct _halrf_psd_data *psd = &(rf->halrf_psd_data);
if (psd->psd_progress)
ret_status = RT_STATUS_PENDING;
else
PlatformMoveMemory(outbuf, psd->psd_data, 0x400);
return ret_status;
}
enum rt_status
halrf_psd_init_query(
struct dm_struct *dm,
u32 *outbuf,
u32 point,
u32 start_point,
u32 stop_point,
u32 average,
u32 buf_size)
{
enum rt_status ret_status = RT_STATUS_SUCCESS;
struct _hal_rf_ *rf = &(dm->rf_table);
struct _halrf_psd_data *psd = &(rf->halrf_psd_data);
psd->point = point;
psd->start_point = start_point;
psd->stop_point = stop_point;
psd->average = average;
if (psd->psd_progress) {
ret_status = RT_STATUS_PENDING;
} else {
psd->psd_progress = 1;
halrf_psd(dm, psd->point, psd->start_point, psd->stop_point, psd->average);
PlatformMoveMemory(outbuf, psd->psd_data, 0x400);
psd->psd_progress = 0;
}
return ret_status;
}
#endif /*#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)*/

52
hal/phydm/halrf/halrf_psd.h Normal file
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@@ -0,0 +1,52 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __HALRF_PSD_H__
#define __HALRF_PSD_H__
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
struct _halrf_psd_data {
u32 point;
u32 start_point;
u32 stop_point;
u32 average;
u32 buf_size;
u32 psd_data[256];
u32 psd_progress;
};
enum rt_status
halrf_psd_init(
struct dm_struct *dm);
enum rt_status
halrf_psd_query(
struct dm_struct *dm,
u32 *outbuf,
u32 buf_size);
enum rt_status
halrf_psd_init_query(
struct dm_struct *dm,
u32 *outbuf,
u32 point,
u32 start_point,
u32 stop_point,
u32 average,
u32 buf_size);
#endif /*#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)*/
#endif /*#__HALRF_PSD_H__*/

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "mp_precomp.h"
#include "phydm_precomp.h"
void odm_bub_sort(u32 *data, u32 n)
{
int i, j, temp, sp;
for (i = n - 1; i >= 0; i--) {
sp = 1;
for (j = 0; j < i; j++) {
if (data[j] < data[j + 1]) {
temp = data[j];
data[j] = data[j + 1];
data[j + 1] = temp;
sp = 0;
}
}
if (sp == 1)
break;
}
}
#if (RTL8197F_SUPPORT == 1)
u4Byte
odm_tx_gain_gap_psd_8197f(
void *dm_void,
u1Byte rf_path,
u4Byte rf56)
{
PDM_ODM_T dm = (PDM_ODM_T)dm_void;
u1Byte i, j;
u4Byte psd_vaule[5], psd_avg_time = 5, psd_vaule_temp;
u4Byte iqk_ctl_addr[2][6] = {{0xe30, 0xe34, 0xe50, 0xe54, 0xe38, 0xe3c},
{0xe50, 0xe54, 0xe30, 0xe34, 0xe58, 0xe5c}};
u4Byte psd_finish_bit[2] = {0x04000000, 0x20000000};
u4Byte psd_fail_bit[2] = {0x08000000, 0x40000000};
u4Byte psd_cntl_value[2][2] = {{0x38008c1c, 0x10008c1c},
{0x38008c2c, 0x10008c2c}};
u4Byte psd_report_addr[2] = {0xea0, 0xec0};
odm_set_rf_reg(dm, rf_path, RF_0xdf, bRFRegOffsetMask, 0x00e02);
ODM_delay_us(100);
odm_set_bb_reg(dm, R_0xe28, 0xffffffff, 0x0);
odm_set_rf_reg(dm, rf_path, RF_0x56, 0xfff, rf56);
while (rf56 != (odm_get_rf_reg(dm, rf_path, RF_0x56, 0xfff)))
odm_set_rf_reg(dm, rf_path, RF_0x56, 0xfff, rf56);
odm_set_bb_reg(dm, R_0xd94, 0xffffffff, 0x44FFBB44);
odm_set_bb_reg(dm, R_0xe70, 0xffffffff, 0x00400040);
odm_set_bb_reg(dm, R_0xc04, 0xffffffff, 0x6f005403);
odm_set_bb_reg(dm, R_0xc08, 0xffffffff, 0x000804e4);
odm_set_bb_reg(dm, R_0x874, 0xffffffff, 0x04203400);
odm_set_bb_reg(dm, R_0xe28, 0xffffffff, 0x80800000);
odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][0], 0xffffffff, psd_cntl_value[rf_path][0]);
odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][1], 0xffffffff, psd_cntl_value[rf_path][1]);
odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][2], 0xffffffff, psd_cntl_value[rf_path][0]);
odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][3], 0xffffffff, psd_cntl_value[rf_path][0]);
odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][4], 0xffffffff, 0x8215001F);
odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][5], 0xffffffff, 0x2805001F);
odm_set_bb_reg(dm, R_0xe40, 0xffffffff, 0x81007C00);
odm_set_bb_reg(dm, R_0xe44, 0xffffffff, 0x81004800);
odm_set_bb_reg(dm, R_0xe4c, 0xffffffff, 0x0046a8d0);
for (i = 0; i < psd_avg_time; i++) {
for (j = 0; j < 1000; j++) {
odm_set_bb_reg(dm, R_0xe48, 0xffffffff, 0xfa005800);
odm_set_bb_reg(dm, R_0xe48, 0xffffffff, 0xf8005800);
while (!odm_get_bb_reg(dm, R_0xeac, psd_finish_bit[rf_path]))
; /*wait finish bit*/
if (!odm_get_bb_reg(dm, R_0xeac, psd_fail_bit[rf_path])) { /*check fail bit*/
psd_vaule[i] = odm_get_bb_reg(dm, psd_report_addr[rf_path], 0xffffffff);
if (psd_vaule[i] > 0xffff)
break;
}
}
RF_DBG(dm, DBG_RF_IQK,
"[TGGC] rf0=0x%x rf56=0x%x rf56_reg=0x%x time=%d psd_vaule=0x%x\n",
odm_get_rf_reg(dm, rf_path, RF_0x0, 0xff), rf56,
odm_get_rf_reg(dm, rf_path, RF_0x56, 0xfff), j,
psd_vaule[i]);
}
odm_bub_sort(psd_vaule, psd_avg_time);
psd_vaule_temp = psd_vaule[(UINT)(psd_avg_time / 2)];
odm_set_bb_reg(dm, R_0xd94, 0xffffffff, 0x44BBBB44);
odm_set_bb_reg(dm, R_0xe70, 0xffffffff, 0x80408040);
odm_set_bb_reg(dm, R_0xc04, 0xffffffff, 0x6f005433);
odm_set_bb_reg(dm, R_0xc08, 0xffffffff, 0x000004e4);
odm_set_bb_reg(dm, R_0x874, 0xffffffff, 0x04003400);
odm_set_bb_reg(dm, R_0xe28, 0xffffffff, 0x00000000);
RF_DBG(dm, DBG_RF_IQK,
"[TGGC] rf0=0x%x rf56=0x%x rf56_reg=0x%x psd_vaule_temp=0x%x\n",
odm_get_rf_reg(dm, rf_path, RF_0x0, 0xff), rf56,
odm_get_rf_reg(dm, rf_path, RF_0x56, 0xfff), psd_vaule_temp);
odm_set_rf_reg(dm, rf_path, RF_0xdf, bRFRegOffsetMask, 0x00602);
return psd_vaule_temp;
}
void odm_tx_gain_gap_calibration_8197f(
void *dm_void)
{
PDM_ODM_T dm = (PDM_ODM_T)dm_void;
u1Byte rf_path, rf0_idx, rf0_idx_current, rf0_idx_next, i, delta_gain_retry = 3;
s1Byte delta_gain_gap_pre, delta_gain_gap[2][11];
u4Byte rf56_current, rf56_next, psd_value_current, psd_value_next;
u4Byte psd_gap, rf56_current_temp[2][11];
s4Byte rf33[2][11];
memset(rf33, 0x0, sizeof(rf33));
for (rf_path = RF_PATH_A; rf_path <= RF_PATH_B; rf_path++) {
if (rf_path == RF_PATH_A)
odm_set_bb_reg(dm, R_0x88c, (BIT(21) | BIT(20)), 0x3); /*disable 3-wire*/
else if (rf_path == RF_PATH_B)
odm_set_bb_reg(dm, R_0x88c, (BIT(23) | BIT(22)), 0x3); /*disable 3-wire*/
ODM_delay_us(100);
for (rf0_idx = 1; rf0_idx <= 10; rf0_idx++) {
rf0_idx_current = 3 * (rf0_idx - 1) + 1;
odm_set_rf_reg(dm, rf_path, RF_0x0, 0xff, rf0_idx_current);
ODM_delay_us(100);
rf56_current_temp[rf_path][rf0_idx] = odm_get_rf_reg(dm, rf_path, RF_0x56, 0xfff);
rf56_current = rf56_current_temp[rf_path][rf0_idx];
rf0_idx_next = 3 * rf0_idx + 1;
odm_set_rf_reg(dm, rf_path, RF_0x0, 0xff, rf0_idx_next);
ODM_delay_us(100);
rf56_next = odm_get_rf_reg(dm, rf_path, RF_0x56, 0xfff);
RF_DBG(dm, DBG_RF_IQK,
"[TGGC] rf56_current[%d][%d]=0x%x rf56_next[%d][%d]=0x%x\n",
rf_path, rf0_idx, rf56_current, rf_path, rf0_idx,
rf56_next);
if ((rf56_current >> 5) == (rf56_next >> 5)) {
delta_gain_gap[rf_path][rf0_idx] = 0;
RF_DBG(dm, DBG_RF_IQK,
"[TGGC] rf56_current[11:5] == rf56_next[%d][%d][11:5]=0x%x delta_gain_gap[%d][%d]=%d\n",
rf_path, rf0_idx, (rf56_next >> 5),
rf_path, rf0_idx,
delta_gain_gap[rf_path][rf0_idx]);
continue;
}
RF_DBG(dm, DBG_RF_IQK,
"[TGGC] rf56_current[%d][%d][11:5]=0x%x != rf56_next[%d][%d][11:5]=0x%x\n",
rf_path, rf0_idx, (rf56_current >> 5), rf_path,
rf0_idx, (rf56_next >> 5));
for (i = 0; i < delta_gain_retry; i++) {
psd_value_current = odm_tx_gain_gap_psd_8197f(dm, rf_path, rf56_current);
psd_value_next = odm_tx_gain_gap_psd_8197f(dm, rf_path, rf56_next - 2);
psd_gap = psd_value_next / (psd_value_current / 1000);
#if 0
if (psd_gap > 1413)
delta_gain_gap[rf_path][rf0_idx] = 1;
else if (psd_gap > 1122)
delta_gain_gap[rf_path][rf0_idx] = 0;
else
delta_gain_gap[rf_path][rf0_idx] = -1;
#endif
if (psd_gap > 1445)
delta_gain_gap[rf_path][rf0_idx] = 1;
else if (psd_gap > 1096)
delta_gain_gap[rf_path][rf0_idx] = 0;
else
delta_gain_gap[rf_path][rf0_idx] = -1;
if (i == 0)
delta_gain_gap_pre = delta_gain_gap[rf_path][rf0_idx];
RF_DBG(dm, DBG_RF_IQK,
"[TGGC] psd_value_current=0x%x psd_value_next=0x%x psd_value_next/psd_value_current=%d delta_gain_gap[%d][%d]=%d\n",
psd_value_current, psd_value_next,
psd_gap, rf_path, rf0_idx,
delta_gain_gap[rf_path][rf0_idx]);
if (i == 0 && delta_gain_gap[rf_path][rf0_idx] == 0)
break;
if (delta_gain_gap_pre != delta_gain_gap[rf_path][rf0_idx]) {
delta_gain_gap[rf_path][rf0_idx] = 0;
RF_DBG(dm, DBG_RF_IQK, "[TGGC] delta_gain_gap_pre(%d) != delta_gain_gap[%d][%d](%d) time=%d\n",
delta_gain_gap_pre, rf_path, rf0_idx, delta_gain_gap[rf_path][rf0_idx], i);
break;
}
RF_DBG(dm, DBG_RF_IQK,
"[TGGC] delta_gain_gap_pre(%d) == delta_gain_gap[%d][%d](%d) time=%d\n",
delta_gain_gap_pre, rf_path, rf0_idx,
delta_gain_gap[rf_path][rf0_idx], i);
}
}
if (rf_path == RF_PATH_A)
odm_set_bb_reg(dm, R_0x88c, (BIT(21) | BIT(20)), 0x0); /*enable 3-wire*/
else if (rf_path == RF_PATH_B)
odm_set_bb_reg(dm, R_0x88c, (BIT(23) | BIT(22)), 0x0); /*enable 3-wire*/
ODM_delay_us(100);
}
#if 0
/*odm_set_bb_reg(dm, R_0x88c, (BIT(23) | BIT(22) | BIT(21) | BIT(20)), 0x0);*/ /*enable 3-wire*/
#endif
for (rf_path = RF_PATH_A; rf_path <= RF_PATH_B; rf_path++) {
odm_set_rf_reg(dm, rf_path, RF_0xef, bRFRegOffsetMask, 0x00100);
for (rf0_idx = 1; rf0_idx <= 10; rf0_idx++) {
rf33[rf_path][rf0_idx] = rf33[rf_path][rf0_idx] + (rf56_current_temp[rf_path][rf0_idx] & 0x1f);
for (i = rf0_idx; i <= 10; i++)
rf33[rf_path][rf0_idx] = rf33[rf_path][rf0_idx] + delta_gain_gap[rf_path][i];
if (rf33[rf_path][rf0_idx] >= 0x1d)
rf33[rf_path][rf0_idx] = 0x1d;
else if (rf33[rf_path][rf0_idx] <= 0x2)
rf33[rf_path][rf0_idx] = 0x2;
rf33[rf_path][rf0_idx] = rf33[rf_path][rf0_idx] + ((rf0_idx - 1) * 0x4000) + (rf56_current_temp[rf_path][rf0_idx] & 0xfffe0);
RF_DBG(dm, DBG_RF_IQK,
"[TGGC] rf56[%d][%d]=0x%05x rf33[%d][%d]=0x%05x\n",
rf_path, rf0_idx,
rf56_current_temp[rf_path][rf0_idx], rf_path,
rf0_idx, rf33[rf_path][rf0_idx]);
odm_set_rf_reg(dm, rf_path, RF_0x33, bRFRegOffsetMask, rf33[rf_path][rf0_idx]);
}
odm_set_rf_reg(dm, rf_path, RF_0xef, bRFRegOffsetMask, 0x00000);
}
}
#endif
void odm_tx_gain_gap_calibration(void *dm_void)
{
PDM_ODM_T dm = (PDM_ODM_T)dm_void;
#if (RTL8197F_SUPPORT == 1)
if (dm->SupportICType & ODM_RTL8197F)
odm_tx_gain_gap_calibration_8197f(dm_void);
#endif
}

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hal/phydm/halrf/halrf_txgapcal.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALRF_TXGAPCAL_H__
#define __HALRF_TXGAPCAL_H__
void odm_tx_gain_gap_calibration(void *dm_void);
#endif /*__HALRF_TXGAPCAL_H__*/

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hal/phydm/halrf/rtl8192e/halrf_8192e_ap.c Normal file
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hal/phydm/halrf/rtl8192e/halrf_8192e_ap.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __HALRF_8192E_H__
#define __HALRF_8192E_H__
/*--------------------------Define Parameters-------------------------------*/
#if (DM_ODM_SUPPORT_TYPE & ODM_CE)
#define IQK_DELAY_TIME_92E 15 /* ms */
#else
#define IQK_DELAY_TIME_92E 10
#endif
#define index_mapping_NUM_92E 15
#define AVG_THERMAL_NUM_92E 4
#define RF_T_METER_92E 0x42
#include "../halphyrf_ap.h"
void configure_txpower_track_8192e(
struct txpwrtrack_cfg *config
);
void
get_delta_swing_table_8192e(
void *dm_void,
u8 **temperature_up_a,
u8 **temperature_down_a,
u8 **temperature_up_b,
u8 **temperature_down_b
);
void do_iqk_8192e(
void *dm_void,
u8 delta_thermal_index,
u8 thermal_value,
u8 threshold
);
void
odm_tx_pwr_track_set_pwr92_e(
void *dm_void,
enum pwrtrack_method method,
u8 rf_path,
u8 channel_mapped_index
);
/* 1 7. IQK */
void
phy_iq_calibrate_8192e(
void *dm_void,
boolean is_recovery);
/*
* LC calibrate
* */
void
phy_lc_calibrate_8192e(
void *dm_void
);
/*
* AP calibrate
* */
void
phy_ap_calibrate_8192e(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
struct dm_struct *dm,
#else
void *adapter,
#endif
s8 delta);
void
_phy_save_adda_registers_92e(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
struct dm_struct *dm,
#else
void *adapter,
#endif
u32 *adda_reg,
u32 *adda_backup,
u32 register_num
);
void
_phy_path_adda_on_92e(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
struct dm_struct *dm,
#else
void *adapter,
#endif
u32 *adda_reg,
boolean is_path_a_on,
boolean is2T
);
void
_phy_mac_setting_calibration_92e(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
struct dm_struct *dm,
#else
void *adapter,
#endif
u32 *mac_reg,
u32 *mac_backup
);
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
void
_phy_path_a_stand_by(
struct dm_struct *dm
);
#endif
void
halrf_rf_lna_setting_8192e(
struct dm_struct *dm,
enum halrf_lna_set type
);
#endif /*#ifndef __HALRF_8192E_H__*/

2029
hal/phydm/halrf/rtl8192e/halrf_8192e_ce.c Normal file
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68
hal/phydm/halrf/rtl8192e/halrf_8192e_ce.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __HALRF_8192E_H__
#define __HALRF_8192E_H__
/*--------------------------Define Parameters-------------------------------*/
#if (DM_ODM_SUPPORT_TYPE & ODM_CE)
#define IQK_DELAY_TIME_92E 15 /* ms */
#else
#define IQK_DELAY_TIME_92E 10
#endif
#define index_mapping_NUM_92E 15
#define AVG_THERMAL_NUM_92E 4
#define RF_T_METER_92E 0x42
#include "../halphyrf_ce.h"
void configure_txpower_track_8192e(struct txpwrtrack_cfg *config);
void get_delta_swing_table_8192e(void *dm_void, u8 **temperature_up_a,
u8 **temperature_down_a, u8 **temperature_up_b,
u8 **temperature_down_b);
void do_iqk_8192e(void *dm_void, u8 delta_thermal_index, u8 thermal_value,
u8 threshold);
void odm_tx_pwr_track_set_pwr92_e(void *dm_void, enum pwrtrack_method method,
u8 rf_path, u8 channel_mapped_index);
/* 1 7. IQK */
void phy_iq_calibrate_8192e(void *dm_void, boolean is_recovery);
/*
* LC calibrate
* */
void phy_lc_calibrate_8192e(void *dm_void);
void _phy_save_adda_registers_92e(struct dm_struct *dm, u32 *adda_reg,
u32 *adda_backup, u32 register_num);
void _phy_path_adda_on_92e(struct dm_struct *dm, u32 *adda_reg,
boolean is_path_a_on, boolean is2T);
void _phy_mac_setting_calibration_92e(struct dm_struct *dm, u32 *mac_reg,
u32 *mac_backup);
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
void _phy_path_a_stand_by(struct dm_struct *dm);
#endif
void halrf_rf_lna_setting_8192e(struct dm_struct *dm, enum halrf_lna_set type);
#endif /*#ifndef __HALRF_8192E_H__*/

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hal/phydm/halrf/rtl8192e/halrf_8192e_win.c Normal file
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hal/phydm/halrf/rtl8192e/halrf_8192e_win.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __HALRF_8192E_H__
#define __HALRF_8192E_H__
/*--------------------------Define Parameters-------------------------------*/
#if (DM_ODM_SUPPORT_TYPE & ODM_CE)
#define IQK_DELAY_TIME_92E 15 /* ms */
#else
#define IQK_DELAY_TIME_92E 10
#endif
#define index_mapping_NUM_92E 15
#define AVG_THERMAL_NUM_92E 4
#define RF_T_METER_92E 0x42
#include "halrf/halphyrf_win.h"
void configure_txpower_track_8192e(
struct txpwrtrack_cfg *config
);
void
get_delta_swing_table_8192e(
void *dm_void,
u8 **temperature_up_a,
u8 **temperature_down_a,
u8 **temperature_up_b,
u8 **temperature_down_b
);
void do_iqk_8192e(
void *dm_void,
u8 delta_thermal_index,
u8 thermal_value,
u8 threshold
);
void
odm_tx_pwr_track_set_pwr92_e(
void *dm_void,
enum pwrtrack_method method,
u8 rf_path,
u8 channel_mapped_index
);
/* 1 7. IQK */
void
phy_iq_calibrate_8192e(
void *dm_void,
boolean is_recovery);
/*
* LC calibrate
* */
void
phy_lc_calibrate_8192e(
void *dm_void
);
/*
* AP calibrate
* */
#if 0
void
phy_ap_calibrate_8192e(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
struct dm_struct *dm,
#else
void *adapter,
#endif
s8 delta);
void
phy_digital_predistortion_8192e(void *adapter);
#endif
void
_phy_save_adda_registers_92e(
struct dm_struct *dm,
u32 *adda_reg,
u32 *adda_backup,
u32 register_num
);
void
_phy_path_adda_on_92e(
struct dm_struct *dm,
u32 *adda_reg,
boolean is_path_a_on,
boolean is2T
);
void
_phy_mac_setting_calibration_92e(
struct dm_struct *dm,
u32 *mac_reg,
u32 *mac_backup
);
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
void
_phy_path_a_stand_by(
struct dm_struct *dm
);
#endif
void
halrf_rf_lna_setting_8192e(
struct dm_struct *dm,
enum halrf_lna_set type
);
#endif /*#ifndef __HALRF_8192E_H__*/