mirror of
https://github.com/Mange/rtl8192eu-linux-driver
synced 2024-11-01 03:05:34 +00:00
184 lines
6.1 KiB
C
184 lines
6.1 KiB
C
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2018 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#ifndef __RTW_CHPLAN_H__
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#define __RTW_CHPLAN_H__
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enum rtw_chplan_id {
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/* ===== 0x00 ~ 0x1F, legacy channel plan ===== */
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RTW_CHPLAN_FCC = 0x00,
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RTW_CHPLAN_IC = 0x01,
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RTW_CHPLAN_ETSI = 0x02,
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RTW_CHPLAN_SPAIN = 0x03,
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RTW_CHPLAN_FRANCE = 0x04,
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RTW_CHPLAN_MKK = 0x05,
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RTW_CHPLAN_MKK1 = 0x06,
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RTW_CHPLAN_ISRAEL = 0x07,
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RTW_CHPLAN_TELEC = 0x08,
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RTW_CHPLAN_GLOBAL_DOAMIN = 0x09,
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RTW_CHPLAN_WORLD_WIDE_13 = 0x0A,
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RTW_CHPLAN_TAIWAN = 0x0B,
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RTW_CHPLAN_CHINA = 0x0C,
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RTW_CHPLAN_SINGAPORE_INDIA_MEXICO = 0x0D,
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RTW_CHPLAN_KOREA = 0x0E,
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RTW_CHPLAN_TURKEY = 0x0F,
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RTW_CHPLAN_JAPAN = 0x10,
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RTW_CHPLAN_FCC_NO_DFS = 0x11,
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RTW_CHPLAN_JAPAN_NO_DFS = 0x12,
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RTW_CHPLAN_WORLD_WIDE_5G = 0x13,
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RTW_CHPLAN_TAIWAN_NO_DFS = 0x14,
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/* ===== 0x20 ~ 0x7F, new channel plan ===== */
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RTW_CHPLAN_WORLD_NULL = 0x20,
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RTW_CHPLAN_ETSI1_NULL = 0x21,
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RTW_CHPLAN_FCC1_NULL = 0x22,
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RTW_CHPLAN_MKK1_NULL = 0x23,
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RTW_CHPLAN_ETSI2_NULL = 0x24,
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RTW_CHPLAN_FCC1_FCC1 = 0x25,
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RTW_CHPLAN_WORLD_ETSI1 = 0x26,
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RTW_CHPLAN_MKK1_MKK1 = 0x27,
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RTW_CHPLAN_WORLD_KCC1 = 0x28,
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RTW_CHPLAN_WORLD_FCC2 = 0x29,
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RTW_CHPLAN_FCC2_NULL = 0x2A,
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RTW_CHPLAN_IC1_IC2 = 0x2B,
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RTW_CHPLAN_MKK2_NULL = 0x2C,
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RTW_CHPLAN_WORLD_CHILE1= 0x2D,
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RTW_CHPLAN_WORLD1_WORLD1 = 0x2E,
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RTW_CHPLAN_WORLD_CHILE2 = 0x2F,
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RTW_CHPLAN_WORLD_FCC3 = 0x30,
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RTW_CHPLAN_WORLD_FCC4 = 0x31,
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RTW_CHPLAN_WORLD_FCC5 = 0x32,
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RTW_CHPLAN_WORLD_FCC6 = 0x33,
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RTW_CHPLAN_FCC1_FCC7 = 0x34,
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RTW_CHPLAN_WORLD_ETSI2 = 0x35,
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RTW_CHPLAN_WORLD_ETSI3 = 0x36,
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RTW_CHPLAN_MKK1_MKK2 = 0x37,
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RTW_CHPLAN_MKK1_MKK3 = 0x38,
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RTW_CHPLAN_FCC1_NCC1 = 0x39,
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RTW_CHPLAN_ETSI1_ETSI1 = 0x3A,
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RTW_CHPLAN_ETSI1_ACMA1 = 0x3B,
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RTW_CHPLAN_ETSI1_ETSI6 = 0x3C,
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RTW_CHPLAN_ETSI1_ETSI12 = 0x3D,
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RTW_CHPLAN_KCC1_KCC2 = 0x3E,
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RTW_CHPLAN_FCC1_FCC11 = 0x3F,
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RTW_CHPLAN_FCC1_NCC2 = 0x40,
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RTW_CHPLAN_GLOBAL_NULL = 0x41,
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RTW_CHPLAN_ETSI1_ETSI4 = 0x42,
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RTW_CHPLAN_FCC1_FCC2 = 0x43,
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RTW_CHPLAN_FCC1_NCC3 = 0x44,
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RTW_CHPLAN_WORLD_ACMA1 = 0x45,
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RTW_CHPLAN_FCC1_FCC8 = 0x46,
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RTW_CHPLAN_WORLD_ETSI6 = 0x47,
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RTW_CHPLAN_WORLD_ETSI7 = 0x48,
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RTW_CHPLAN_WORLD_ETSI8 = 0x49,
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RTW_CHPLAN_IC2_IC2 = 0x4A,
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RTW_CHPLAN_KCC1_KCC3 = 0x4B,
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RTW_CHPLAN_FCC1_FCC15 = 0x4C,
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RTW_CHPLAN_WORLD_ETSI9 = 0x50,
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RTW_CHPLAN_WORLD_ETSI10 = 0x51,
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RTW_CHPLAN_WORLD_ETSI11 = 0x52,
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RTW_CHPLAN_FCC1_NCC4 = 0x53,
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RTW_CHPLAN_WORLD_ETSI12 = 0x54,
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RTW_CHPLAN_FCC1_FCC9 = 0x55,
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RTW_CHPLAN_WORLD_ETSI13 = 0x56,
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RTW_CHPLAN_FCC1_FCC10 = 0x57,
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RTW_CHPLAN_MKK2_MKK4 = 0x58,
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RTW_CHPLAN_WORLD_ETSI14 = 0x59,
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RTW_CHPLAN_FCC1_FCC5 = 0x60,
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RTW_CHPLAN_FCC2_FCC7 = 0x61,
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RTW_CHPLAN_FCC2_FCC1 = 0x62,
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RTW_CHPLAN_WORLD_ETSI15 = 0x63,
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RTW_CHPLAN_MKK2_MKK5 = 0x64,
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RTW_CHPLAN_ETSI1_ETSI16 = 0x65,
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RTW_CHPLAN_FCC1_FCC14 = 0x66,
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RTW_CHPLAN_FCC1_FCC12 = 0x67,
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RTW_CHPLAN_FCC2_FCC14 = 0x68,
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RTW_CHPLAN_FCC2_FCC12 = 0x69,
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RTW_CHPLAN_ETSI1_ETSI17 = 0x6A,
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RTW_CHPLAN_WORLD_FCC16 = 0x6B,
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RTW_CHPLAN_WORLD_FCC13 = 0x6C,
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RTW_CHPLAN_FCC2_FCC15 = 0x6D,
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RTW_CHPLAN_WORLD_FCC12 = 0x6E,
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RTW_CHPLAN_NULL_ETSI8 = 0x6F,
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RTW_CHPLAN_NULL_ETSI18 = 0x70,
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RTW_CHPLAN_NULL_ETSI17 = 0x71,
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RTW_CHPLAN_NULL_ETSI19 = 0x72,
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RTW_CHPLAN_WORLD_FCC7 = 0x73,
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RTW_CHPLAN_FCC2_FCC17 = 0x74,
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RTW_CHPLAN_WORLD_ETSI20 = 0x75,
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RTW_CHPLAN_FCC2_FCC11 = 0x76,
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RTW_CHPLAN_WORLD_ETSI21 = 0x77,
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RTW_CHPLAN_FCC1_FCC18 = 0x78,
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RTW_CHPLAN_MKK2_MKK1 = 0x79,
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RTW_CHPLAN_MAX,
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RTW_CHPLAN_REALTEK_DEFINE = 0x7F,
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RTW_CHPLAN_UNSPECIFIED = 0xFF,
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};
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u8 rtw_chplan_get_default_regd(u8 id);
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bool rtw_chplan_is_empty(u8 id);
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#define rtw_is_channel_plan_valid(chplan) (((chplan) < RTW_CHPLAN_MAX || (chplan) == RTW_CHPLAN_REALTEK_DEFINE) && !rtw_chplan_is_empty(chplan))
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#define rtw_is_legacy_channel_plan(chplan) ((chplan) < 0x20)
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struct _RT_CHANNEL_INFO;
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u8 init_channel_set(_adapter *padapter, u8 ChannelPlan, struct _RT_CHANNEL_INFO *channel_set);
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#define IS_ALPHA2_NO_SPECIFIED(_alpha2) ((*((u16 *)(_alpha2))) == 0xFFFF)
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#define RTW_MODULE_RTL8821AE_HMC_M2 BIT0 /* RTL8821AE(HMC + M.2) */
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#define RTW_MODULE_RTL8821AU BIT1 /* RTL8821AU */
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#define RTW_MODULE_RTL8812AENF_NGFF BIT2 /* RTL8812AENF(8812AE+8761)_NGFF */
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#define RTW_MODULE_RTL8812AEBT_HMC BIT3 /* RTL8812AEBT(8812AE+8761)_HMC */
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#define RTW_MODULE_RTL8188EE_HMC_M2 BIT4 /* RTL8188EE(HMC + M.2) */
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#define RTW_MODULE_RTL8723BE_HMC_M2 BIT5 /* RTL8723BE(HMC + M.2) */
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#define RTW_MODULE_RTL8723BS_NGFF1216 BIT6 /* RTL8723BS(NGFF1216) */
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#define RTW_MODULE_RTL8192EEBT_HMC_M2 BIT7 /* RTL8192EEBT(8192EE+8761AU)_(HMC + M.2) */
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#define RTW_MODULE_RTL8723DE_NGFF1630 BIT8 /* RTL8723DE(NGFF1630) */
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#define RTW_MODULE_RTL8822BE BIT9 /* RTL8822BE */
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#define RTW_MODULE_RTL8821CE BIT10 /* RTL8821CE */
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struct country_chplan {
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char alpha2[2];
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u8 chplan;
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#ifdef CONFIG_80211AC_VHT
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u8 en_11ac;
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#endif
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#if RTW_DEF_MODULE_REGULATORY_CERT
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u16 def_module_flags; /* RTW_MODULE_RTLXXX */
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#endif
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};
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#ifdef CONFIG_80211AC_VHT
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#define COUNTRY_CHPLAN_EN_11AC(_ent) ((_ent)->en_11ac)
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#else
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#define COUNTRY_CHPLAN_EN_11AC(_ent) 0
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#endif
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#if RTW_DEF_MODULE_REGULATORY_CERT
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#define COUNTRY_CHPLAN_DEF_MODULE_FALGS(_ent) ((_ent)->def_module_flags)
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#else
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#define COUNTRY_CHPLAN_DEF_MODULE_FALGS(_ent) 0
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#endif
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const struct country_chplan *rtw_get_chplan_from_country(const char *country_code);
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void dump_country_chplan(void *sel, const struct country_chplan *ent);
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void dump_country_chplan_map(void *sel);
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void dump_chplan_id_list(void *sel);
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void dump_chplan_test(void *sel);
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void dump_chplan_ver(void *sel);
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#endif /* __RTW_CHPLAN_H__ */
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