mirror of
https://github.com/Mange/rtl8192eu-linux-driver
synced 2024-11-23 22:14:59 +00:00
88 lines
2.9 KiB
C
88 lines
2.9 KiB
C
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2017 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#ifndef __PHYDM_PRIMARYCCA_H__
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#define __PHYDM_PRIMARYCCA_H__
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#ifdef PHYDM_PRIMARY_CCA
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#define PRIMARYCCA_VERSION "2.0"
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/*@============================================================*/
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/*@Definition */
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/*@============================================================*/
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#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
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#define SECOND_CH_AT_LSB 2 /*@primary CH @ MSB, SD4: HAL_PRIME_CHNL_OFFSET_UPPER*/
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#define SECOND_CH_AT_USB 1 /*@primary CH @ LSB, SD4: HAL_PRIME_CHNL_OFFSET_LOWER*/
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#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
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#define SECOND_CH_AT_LSB 2 /*@primary CH @ MSB, SD7: HAL_PRIME_CHNL_OFFSET_UPPER*/
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#define SECOND_CH_AT_USB 1 /*@primary CH @ LSB, SD7: HAL_PRIME_CHNL_OFFSET_LOWER*/
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#else /*if (DM_ODM_SUPPORT_TYPE == ODM_AP)*/
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#define SECOND_CH_AT_LSB 1 /*@primary CH @ MSB, SD8: HT_2NDCH_OFFSET_BELOW*/
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#define SECOND_CH_AT_USB 2 /*@primary CH @ LSB, SD8: HT_2NDCH_OFFSET_ABOVE*/
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#endif
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#define OFDMCCA_TH 500
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#define bw_ind_bias 500
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#define PRI_CCA_MONITOR_TIME 30
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/*@============================================================*/
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/*structure and define*/
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/*@============================================================*/
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enum primary_cca_ch_position { /*N-series REG0xc6c[8:7]*/
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MF_USC_LSC = 0,
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MF_LSC = 1,
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MF_USC = 2
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};
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struct phydm_pricca_struct {
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#if (RTL8188E_SUPPORT == 1) || (RTL8192E_SUPPORT == 1)
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u8 pri_cca_flag;
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u8 intf_flag;
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u8 intf_type;
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u8 monitor_flag;
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u8 ch_offset;
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#endif
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u8 dup_rts_flag;
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u8 cca_th_40m_bkp; /*@c84[31:28]*/
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enum channel_width pre_bw;
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u8 pri_cca_is_become_linked;
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u8 mf_state;
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};
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/*@============================================================*/
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/*@function prototype*/
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/*@============================================================*/
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void phydm_write_dynamic_cca(void *dm_void, u8 curr_mf_state);
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boolean odm_dynamic_primary_cca_dup_rts(void *dm_void);
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void phydm_primary_cca_init(void *dm_void);
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void phydm_primary_cca(void *dm_void);
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#endif /*@#ifdef PHYDM_PRIMARY_CCA*/
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#endif /*@#ifndef __PHYDM_PRIMARYCCA_H__*/
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