mirror of
https://github.com/Mange/rtl8192eu-linux-driver
synced 2024-11-23 05:55:05 +00:00
87 lines
2.6 KiB
C
87 lines
2.6 KiB
C
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2017 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#ifndef __HALRF_DPK_H__
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#define __HALRF_DPK_H__
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/*@--------------------------Define Parameters-------------------------------*/
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#define GAIN_LOSS 1
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#define DO_DPK 2
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#define DPK_ON 3
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#define DPK_LOK 4
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#define DPK_TXK 5
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#define DAGC 4
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#define LOSS_CHK 0
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#define GAIN_CHK 1
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#define PAS_READ 2
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#define AVG_THERMAL_NUM 8
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#define AVG_THERMAL_NUM_DPK 8
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#define THERMAL_DPK_AVG_NUM 4
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/*@---------------------------End Define Parameters---------------------------*/
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struct dm_dpk_info {
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boolean is_dpk_enable;
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boolean is_dpk_pwr_on;
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boolean is_dpk_by_channel;
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u16 dpk_path_ok;
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/*@BIT(15)~BIT(12) : 5G reserved, BIT(11)~BIT(8) 5G_S3~5G_S0*/
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/*@BIT(7)~BIT(4) : 2G reserved, BIT(3)~BIT(0) 2G_S3~2G_S0*/
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u8 thermal_dpk;
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u8 thermal_dpk_avg[AVG_THERMAL_NUM_DPK];
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u8 thermal_dpk_avg_index;
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#if (RTL8822C_SUPPORT == 1)
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u8 result[2][1]; /*path/group*/
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u8 tx_agc[2][1]; /*path/group*/
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u32 coef[2][1][20]; /*path/group/MDPD coefficient*/
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#endif
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#if (RTL8198F_SUPPORT == 1 || RTL8192F_SUPPORT == 1 || RTL8197F_SUPPORT == 1)
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/*2G DPK data*/
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u8 dpk_result[4][3]; /*path/group*/
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u8 pwsf_2g[4][3]; /*path/group*/
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u32 lut_2g_even[4][3][64]; /*path/group/LUT data*/
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u32 lut_2g_odd[4][3][64]; /*path/group/LUT data*/
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#endif
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#if (RTL8195B_SUPPORT == 1)
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/*2G DPK data*/
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u8 dpk_2g_result[1][3]; /*path/group*/
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u8 pwsf_2g[1][3]; /*path/group*/
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u32 lut_2g_even[1][3][16]; /*path/group/LUT data*/
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u32 lut_2g_odd[1][3][16]; /*path/group/LUT data*/
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/*5G DPK data*/
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u8 dpk_5g_result[1][6]; /*path/group*/
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u8 pwsf_5g[1][6]; /*path/group*/
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u32 lut_5g_even[1][6][16]; /*path/group/LUT data*/
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u32 lut_5g_odd[1][6][16]; /*path/group/LUT data*/
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#endif
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};
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#endif /*__HALRF_DPK_H__*/
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