mirror of
https://github.com/Mange/rtl8192eu-linux-driver
synced 2024-11-22 21:45:22 +00:00
195 lines
11 KiB
C
195 lines
11 KiB
C
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2017 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#ifndef __RTL8192F_CMD_H__
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#define __RTL8192F_CMD_H__
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/* ---------------------------------------------------------------------------------------------------------
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* ---------------------------------- H2C CMD DEFINITION ------------------------------------------------
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* --------------------------------------------------------------------------------------------------------- */
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enum h2c_cmd_8192F {
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/* Common Class: 000 */
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H2C_8192F_RSVD_PAGE = 0x00,
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H2C_8192F_MEDIA_STATUS_RPT = 0x01,
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H2C_8192F_SCAN_ENABLE = 0x02,
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H2C_8192F_KEEP_ALIVE = 0x03,
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H2C_8192F_DISCON_DECISION = 0x04,
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H2C_8192F_PSD_OFFLOAD = 0x05,
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H2C_8192F_AP_OFFLOAD = 0x08,
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H2C_8192F_BCN_RSVDPAGE = 0x09,
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H2C_8192F_PROBERSP_RSVDPAGE = 0x0A,
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H2C_8192F_FCS_RSVDPAGE = 0x10,
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H2C_8192F_FCS_INFO = 0x11,
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H2C_8192F_AP_WOW_GPIO_CTRL = 0x13,
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/* PoweSave Class: 001 */
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H2C_8192F_SET_PWR_MODE = 0x20,
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H2C_8192F_PS_TUNING_PARA = 0x21,
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H2C_8192F_PS_TUNING_PARA2 = 0x22,
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H2C_8192F_P2P_LPS_PARAM = 0x23,
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H2C_8192F_P2P_PS_OFFLOAD = 0x24,
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H2C_8192F_PS_SCAN_ENABLE = 0x25,
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H2C_8192F_SAP_PS_ = 0x26,
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H2C_8192F_INACTIVE_PS_ = 0x27,/* Inactive_PS */
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H2C_8192F_FWLPS_IN_IPS_ = 0x28,
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/* Dynamic Mechanism Class: 010 */
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H2C_8192F_MACID_CFG = 0x40,
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H2C_8192F_TXBF = 0x41,
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H2C_8192F_RSSI_SETTING = 0x42,
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H2C_8192F_AP_REQ_TXRPT = 0x43,
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H2C_8192F_INIT_RATE_COLLECT = 0x44,
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H2C_8192F_RA_PARA_ADJUST = 0x46,
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/* BT Class: 011 */
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H2C_8192F_B_TYPE_TDMA = 0x60,
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H2C_8192F_BT_INFO = 0x61,
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H2C_8192F_FORCE_BT_TXPWR = 0x62,
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H2C_8192F_BT_IGNORE_WLANACT = 0x63,
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H2C_8192F_DAC_SWING_VALUE = 0x64,
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H2C_8192F_ANT_SEL_RSV = 0x65,
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H2C_8192F_WL_OPMODE = 0x66,
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H2C_8192F_BT_MP_OPER = 0x67,
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H2C_8192F_BT_CONTROL = 0x68,
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H2C_8192F_BT_WIFI_CTRL = 0x69,
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H2C_8192F_BT_FW_PATCH = 0x6A,
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H2C_8192F_BT_WLAN_CALIBRATION = 0x6D,
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/* WOWLAN Class: 100 */
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H2C_8192F_WOWLAN = 0x80,
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H2C_8192F_REMOTE_WAKE_CTRL = 0x81,
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H2C_8192F_AOAC_GLOBAL_INFO = 0x82,
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H2C_8192F_AOAC_RSVD_PAGE = 0x83,
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H2C_8192F_AOAC_RSVD_PAGE2 = 0x84,
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H2C_8192F_D0_SCAN_OFFLOAD_CTRL = 0x85,
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H2C_8192F_D0_SCAN_OFFLOAD_INFO = 0x86,
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H2C_8192F_CHNL_SWITCH_OFFLOAD = 0x87,
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H2C_8192F_P2P_OFFLOAD_RSVD_PAGE = 0x8A,
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H2C_8192F_P2P_OFFLOAD = 0x8B,
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H2C_8192F_RESET_TSF = 0xC0,
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H2C_8192F_MAXID,
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};
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/* ---------------------------------------------------------------------------------------------------------
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* ---------------------------------- H2C CMD CONTENT --------------------------------------------------
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* ---------------------------------------------------------------------------------------------------------
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* _RSVDPAGE_LOC_CMD_0x00 */
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#define SET_8192F_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
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#define SET_8192F_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
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#define SET_8192F_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
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#define SET_8192F_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
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#define SET_8192F_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
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/*_MEDIA_STATUS_RPT_PARM_CMD_0x01*/
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#define SET_8192F_H2CCMD_MSRRPT_PARM_OPMODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
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#define SET_8192F_H2CCMD_MSRRPT_PARM_MACID_IND(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
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#define SET_8192F_H2CCMD_MSRRPT_PARM_MACID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
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#define SET_8192F_H2CCMD_MSRRPT_PARM_MACID_END(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
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/* _PWR_MOD_CMD_0x20 */
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#define SET_8192F_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
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#define SET_8192F_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value)
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#define SET_8192F_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value)
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#define SET_8192F_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
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#define SET_8192F_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
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#define SET_8192F_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value)
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#define SET_8192F_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
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#define GET_8192F_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd) LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)
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/* _PS_TUNE_PARAM_CMD_0x21 */
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#define SET_8192F_H2CCMD_PSTUNE_PARM_BCN_TO_LIMIT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
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#define SET_8192F_H2CCMD_PSTUNE_PARM_DTIM_TIMEOUT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
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#define SET_8192F_H2CCMD_PSTUNE_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 1, __Value)
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#define SET_8192F_H2CCMD_PSTUNE_PARM_PS_TIMEOUT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 1, 7, __Value)
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#define SET_8192F_H2CCMD_PSTUNE_PARM_DTIM_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
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/* _MACID_CFG_CMD_0x40 */
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#define SET_8192F_H2CCMD_MACID_CFG_MACID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
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#define SET_8192F_H2CCMD_MACID_CFG_RAID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 5, __Value)
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#define SET_8192F_H2CCMD_MACID_CFG_SGI_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 7, 1, __Value)
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#define SET_8192F_H2CCMD_MACID_CFG_BW(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 2, __Value)
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#define SET_8192F_H2CCMD_MACID_CFG_NO_UPDATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 3, 1, __Value)
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#define SET_8192F_H2CCMD_MACID_CFG_VHT_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 4, 2, __Value)
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#define SET_8192F_H2CCMD_MACID_CFG_DISPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 6, 1, __Value)
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#define SET_8192F_H2CCMD_MACID_CFG_DISRA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 7, 1, __Value)
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#define SET_8192F_H2CCMD_MACID_CFG_RATE_MASK0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
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#define SET_8192F_H2CCMD_MACID_CFG_RATE_MASK1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
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#define SET_8192F_H2CCMD_MACID_CFG_RATE_MASK2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+5, 0, 8, __Value)
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#define SET_8192F_H2CCMD_MACID_CFG_RATE_MASK3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+6, 0, 8, __Value)
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/* _RSSI_SETTING_CMD_0x42 */
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#define SET_8192F_H2CCMD_RSSI_SETTING_MACID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
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#define SET_8192F_H2CCMD_RSSI_SETTING_RSSI(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 7, __Value)
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#define SET_8192F_H2CCMD_RSSI_SETTING_ULDL_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
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/* _AP_REQ_TXRPT_CMD_0x43 */
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#define SET_8192F_H2CCMD_APREQRPT_PARM_MACID1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
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#define SET_8192F_H2CCMD_APREQRPT_PARM_MACID2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
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/* _FORCE_BT_TXPWR_CMD_0x62 */
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#define SET_8192F_H2CCMD_BT_PWR_IDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
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/* _FORCE_BT_MP_OPER_CMD_0x67 */
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#define SET_8192F_H2CCMD_BT_MPOPER_VER(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)
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#define SET_8192F_H2CCMD_BT_MPOPER_REQNUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value)
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#define SET_8192F_H2CCMD_BT_MPOPER_IDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
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#define SET_8192F_H2CCMD_BT_MPOPER_PARAM1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
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#define SET_8192F_H2CCMD_BT_MPOPER_PARAM2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
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#define SET_8192F_H2CCMD_BT_MPOPER_PARAM3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
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/* _BT_FW_PATCH_0x6A */
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#define SET_8192F_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value) SET_BITS_TO_LE_2BYTE((pu1Byte)(__pH2CCmd), 0, 16, __Value)
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#define SET_8192F_H2CCMD_BT_FW_PATCH_ADDR0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
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#define SET_8192F_H2CCMD_BT_FW_PATCH_ADDR1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
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#define SET_8192F_H2CCMD_BT_FW_PATCH_ADDR2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
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#define SET_8192F_H2CCMD_BT_FW_PATCH_ADDR3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)
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/* ---------------------------------------------------------------------------------------------------------
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* ------------------------------------------- Structure --------------------------------------------------
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* --------------------------------------------------------------------------------------------------------- */
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/* ---------------------------------------------------------------------------------------------------------
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* ---------------------------------- Function Statement --------------------------------------------------
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* --------------------------------------------------------------------------------------------------------- */
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/* host message to firmware cmd */
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void rtl8192f_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode);
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void rtl8192f_set_FwJoinBssRpt_cmd(PADAPTER padapter, u8 mstatus);
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/* s32 rtl8192f__set_lowpwr_lps_cmd(PADAPTER padapter, u8 enable); */
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void rtl8192f_set_FwPsTuneParam_cmd(PADAPTER padapter);
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void rtl8192f_download_rsvd_page(PADAPTER padapter, u8 mstatus);
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#ifdef CONFIG_BT_COEXIST
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void rtl8192f__download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter);
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#endif /* CONFIG_BT_COEXIST */
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#ifdef CONFIG_P2P
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void rtl8192f_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);
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#endif /* CONFIG_P2P */
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#ifdef CONFIG_TDLS
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#ifdef CONFIG_TDLS_CH_SW
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void rtl8192f_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable);
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#endif
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#endif
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#ifdef CONFIG_P2P_WOWLAN
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void rtl8192f_set_p2p_wowlan_offload_cmd(PADAPTER padapter);
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#endif
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s32 FillH2CCmd8192F(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
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u8 GetTxBufferRsvdPageNum8192F(_adapter *padapter, bool wowlan);
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#endif
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