2019-11-09 10:12:08 +00:00
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2017 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#ifndef __RTL8814A_SPEC_H__
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#define __RTL8814A_SPEC_H__
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#include <drv_conf.h>
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/* ************************************************************
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*
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* ************************************************************ */
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/* -----------------------------------------------------
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*
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* 0x0000h ~ 0x00FFh System Configuration
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*
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* ----------------------------------------------------- */
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#define REG_SYS_ISO_CTRL_8814A 0x0000 /* 2 Byte */
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#define REG_SYS_FUNC_EN_8814A 0x0002 /* 2 Byte */
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#define REG_SYS_PW_CTRL_8814A 0x0004 /* 4 Byte */
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#define REG_SYS_CLKR_8814A 0x0008 /* 2 Byte */
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#define REG_SYS_EEPROM_CTRL_8814A 0x000A /* 2 Byte */
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#define REG_EE_VPD_8814A 0x000C /* 2 Byte */
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#define REG_SYS_SWR_CTRL1_8814A 0x0010 /* 1 Byte */
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#define REG_SPS0_CTRL_8814A 0x0011 /* 7 Byte */
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#define REG_SYS_SWR_CTRL3_8814A 0x0018 /* 4 Byte */
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#define REG_RSV_CTRL_8814A 0x001C /* 3 Byte */
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#define REG_RF_CTRL0_8814A 0x001F /* 1 Byte */
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#define REG_RF_CTRL1_8814A 0x0020 /* 1 Byte */
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#define REG_RF_CTRL2_8814A 0x0021 /* 1 Byte */
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#define REG_LPLDO_CTRL_8814A 0x0023 /* 1 Byte */
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#define REG_AFE_CTRL1_8814A 0x0024 /* 4 Byte */
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#define REG_AFE_CTRL2_8814A 0x0028 /* 4 Byte */
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#define REG_AFE_CTRL3_8814A 0x002c /* 4 Byte */
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#define REG_EFUSE_CTRL_8814A 0x0030
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#define REG_LDO_EFUSE_CTRL_8814A 0x0034
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#define REG_PWR_DATA_8814A 0x0038
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#define REG_CAL_TIMER_8814A 0x003C
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#define REG_ACLK_MON_8814A 0x003E
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#define REG_GPIO_MUXCFG_8814A 0x0040
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#define REG_GPIO_IO_SEL_8814A 0x0042
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#define REG_MAC_PINMUX_CFG_8814A 0x0043
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#define REG_GPIO_PIN_CTRL_8814A 0x0044
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#define REG_GPIO_INTM_8814A 0x0048
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#define REG_LEDCFG0_8814A 0x004C
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#define REG_LEDCFG1_8814A 0x004D
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#define REG_LEDCFG2_8814A 0x004E
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#define REG_LEDCFG3_8814A 0x004F
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#define REG_FSIMR_8814A 0x0050
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#define REG_FSISR_8814A 0x0054
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#define REG_HSIMR_8814A 0x0058
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#define REG_HSISR_8814A 0x005c
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#define REG_GPIO_EXT_CTRL_8814A 0x0060
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#define REG_GPIO_STATUS_8814A 0x006C
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#define REG_SDIO_CTRL_8814A 0x0070
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#define REG_HCI_OPT_CTRL_8814A 0x0074
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#define REG_RF_CTRL3_8814A 0x0076 /* 1 Byte */
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#define REG_AFE_CTRL4_8814A 0x0078
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#define REG_8051FW_CTRL_8814A 0x0080
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#define REG_HIMR0_8814A 0x00B0
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#define REG_HISR0_8814A 0x00B4
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#define REG_HIMR1_8814A 0x00B8
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#define REG_HISR1_8814A 0x00BC
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#define REG_SYS_CFG1_8814A 0x00F0
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#define REG_SYS_CFG2_8814A 0x00FC
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#define REG_SYS_CFG3_8814A 0x1000
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/* -----------------------------------------------------
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*
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* 0x0100h ~ 0x01FFh MACTOP General Configuration
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*
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* ----------------------------------------------------- */
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#define REG_CR_8814A 0x0100
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#define REG_PBP_8814A 0x0104
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#define REG_PKT_BUFF_ACCESS_CTRL_8814A 0x0106
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#define REG_TRXDMA_CTRL_8814A 0x010C
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#define REG_TRXFF_BNDY_8814A 0x0114
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#define REG_TRXFF_STATUS_8814A 0x0118
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#define REG_RXFF_PTR_8814A 0x011C
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#define REG_CPWM_8814A 0x012F
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#define REG_FWIMR_8814A 0x0130
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#define REG_FWISR_8814A 0x0134
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#define REG_FTIMR_8814A 0x0138
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#define REG_PKTBUF_DBG_CTRL_8814A 0x0140
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#define REG_RXPKTBUF_CTRL_8814A 0x0142
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#define REG_PKTBUF_DBG_DATA_L_8814A 0x0144
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#define REG_PKTBUF_DBG_DATA_H_8814A 0x0148
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#define REG_WOWLAN_WAKE_REASON REG_MCUTST_WOWLAN
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#define REG_TC0_CTRL_8814A 0x0150
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#define REG_TC1_CTRL_8814A 0x0154
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#define REG_TC2_CTRL_8814A 0x0158
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#define REG_TC3_CTRL_8814A 0x015C
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#define REG_TC4_CTRL_8814A 0x0160
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#define REG_TCUNIT_BASE_8814A 0x0164
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#define REG_RSVD3_8814A 0x0168
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#define REG_C2HEVT_MSG_NORMAL_8814A 0x01A0
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#define REG_C2HEVT_CLEAR_8814A 0x01AF
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#define REG_MCUTST_1_8814A 0x01C0
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#define REG_MCUTST_WOWLAN_8814A 0x01C7
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#define REG_FMETHR_8814A 0x01C8
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#define REG_HMETFR_8814A 0x01CC
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#define REG_HMEBOX_0_8814A 0x01D0
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#define REG_HMEBOX_1_8814A 0x01D4
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#define REG_HMEBOX_2_8814A 0x01D8
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#define REG_HMEBOX_3_8814A 0x01DC
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#define REG_LLT_INIT_8814A 0x01E0
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#define REG_LLT_ADDR_8814A 0x01E4 /* 20130415 KaiYuan add for 8814 */
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#define REG_HMEBOX_EXT0_8814A 0x01F0
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#define REG_HMEBOX_EXT1_8814A 0x01F4
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#define REG_HMEBOX_EXT2_8814A 0x01F8
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#define REG_HMEBOX_EXT3_8814A 0x01FC
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/* -----------------------------------------------------
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*
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* 0x0200h ~ 0x027Fh TXDMA Configuration
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*
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* ----------------------------------------------------- */
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#define REG_FIFOPAGE_CTRL_1_8814A 0x0200
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#define REG_FIFOPAGE_CTRL_2_8814A 0x0204
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#define REG_AUTO_LLT_8814A 0x0208
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#define REG_TXDMA_OFFSET_CHK_8814A 0x020C
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#define REG_TXDMA_STATUS_8814A 0x0210
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#define REG_RQPN_NPQ_8814A 0x0214
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#define REG_TQPNT1_8814A 0x0218
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#define REG_TQPNT2_8814A 0x021C
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#define REG_TQPNT3_8814A 0x0220
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#define REG_TQPNT4_8814A 0x0224
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#define REG_RQPN_CTRL_1_8814A 0x0228
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#define REG_RQPN_CTRL_2_8814A 0x022C
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#define REG_FIFOPAGE_INFO_1_8814A 0x0230
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#define REG_FIFOPAGE_INFO_2_8814A 0x0234
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#define REG_FIFOPAGE_INFO_3_8814A 0x0238
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#define REG_FIFOPAGE_INFO_4_8814A 0x023C
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#define REG_FIFOPAGE_INFO_5_8814A 0x0240
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/* -----------------------------------------------------
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*
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* 0x0280h ~ 0x02FFh RXDMA Configuration
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*
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* ----------------------------------------------------- */
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#define REG_RXDMA_AGG_PG_TH_8814A 0x0280
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#define REG_RXPKT_NUM_8814A 0x0284 /* The number of packets in RXPKTBUF. */
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#define REG_RXDMA_CONTROL_8814A 0x0286 /* ?????? Control the RX DMA. */
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#define REG_RXDMA_STATUS_8814A 0x0288
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#define REG_RXDMA_MODE_8814A 0x0290 /* ?????? */
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#define REG_EARLY_MODE_CONTROL_8814A 0x02BC /* ?????? */
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#define REG_RSVD5_8814A 0x02F0 /* ?????? */
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/* -----------------------------------------------------
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*
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* 0x0300h ~ 0x03FFh PCIe
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*
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* ----------------------------------------------------- */
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#define REG_PCIE_CTRL_REG_8814A 0x0300
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#define REG_INT_MIG_8814A 0x0304 /* Interrupt Migration */
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#define REG_BCNQ_TXBD_DESA_8814A 0x0308 /* TX Beacon Descriptor Address */
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#define REG_MGQ_TXBD_DESA_8814A 0x0310 /* TX Manage Queue Descriptor Address */
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#define REG_VOQ_TXBD_DESA_8814A 0x0318 /* TX VO Queue Descriptor Address */
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#define REG_VIQ_TXBD_DESA_8814A 0x0320 /* TX VI Queue Descriptor Address */
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#define REG_BEQ_TXBD_DESA_8814A 0x0328 /* TX BE Queue Descriptor Address */
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#define REG_BKQ_TXBD_DESA_8814A 0x0330 /* TX BK Queue Descriptor Address */
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#define REG_RXQ_RXBD_DESA_8814A 0x0338 /* RX Queue Descriptor Address */
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#define REG_HI0Q_TXBD_DESA_8814A 0x0340
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#define REG_HI1Q_TXBD_DESA_8814A 0x0348
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#define REG_HI2Q_TXBD_DESA_8814A 0x0350
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#define REG_HI3Q_TXBD_DESA_8814A 0x0358
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#define REG_HI4Q_TXBD_DESA_8814A 0x0360
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#define REG_HI5Q_TXBD_DESA_8814A 0x0368
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#define REG_HI6Q_TXBD_DESA_8814A 0x0370
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#define REG_HI7Q_TXBD_DESA_8814A 0x0378
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#define REG_MGQ_TXBD_NUM_8814A 0x0380
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#define REG_RX_RXBD_NUM_8814A 0x0382
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#define REG_VOQ_TXBD_NUM_8814A 0x0384
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#define REG_VIQ_TXBD_NUM_8814A 0x0386
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#define REG_BEQ_TXBD_NUM_8814A 0x0388
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#define REG_BKQ_TXBD_NUM_8814A 0x038A
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#define REG_HI0Q_TXBD_NUM_8814A 0x038C
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#define REG_HI1Q_TXBD_NUM_8814A 0x038E
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#define REG_HI2Q_TXBD_NUM_8814A 0x0390
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#define REG_HI3Q_TXBD_NUM_8814A 0x0392
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#define REG_HI4Q_TXBD_NUM_8814A 0x0394
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#define REG_HI5Q_TXBD_NUM_8814A 0x0396
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#define REG_HI6Q_TXBD_NUM_8814A 0x0398
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#define REG_HI7Q_TXBD_NUM_8814A 0x039A
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#define REG_TSFTIMER_HCI_8814A 0x039C
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/* Read Write Point */
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#define REG_VOQ_TXBD_IDX_8814A 0x03A0
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#define REG_VIQ_TXBD_IDX_8814A 0x03A4
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#define REG_BEQ_TXBD_IDX_8814A 0x03A8
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#define REG_BKQ_TXBD_IDX_8814A 0x03AC
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#define REG_MGQ_TXBD_IDX_8814A 0x03B0
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#define REG_RXQ_TXBD_IDX_8814A 0x03B4
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#define REG_HI0Q_TXBD_IDX_8814A 0x03B8
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#define REG_HI1Q_TXBD_IDX_8814A 0x03BC
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#define REG_HI2Q_TXBD_IDX_8814A 0x03C0
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#define REG_HI3Q_TXBD_IDX_8814A 0x03C4
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#define REG_HI4Q_TXBD_IDX_8814A 0x03C8
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#define REG_HI5Q_TXBD_IDX_8814A 0x03CC
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#define REG_HI6Q_TXBD_IDX_8814A 0x03D0
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#define REG_HI7Q_TXBD_IDX_8814A 0x03D4
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#define REG_DBG_SEL_V1_8814A 0x03D8
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#define REG_PCIE_HRPWM1_V1_8814A 0x03D9
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#define REG_PCIE_HCPWM1_V1_8814A 0x03DA
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#define REG_PCIE_CTRL2_8814A 0x03DB
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#define REG_PCIE_HRPWM2_V1_8814A 0x03DC
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#define REG_PCIE_HCPWM2_V1_8814A 0x03DE
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#define REG_PCIE_H2C_MSG_V1_8814A 0x03E0
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#define REG_PCIE_C2H_MSG_V1_8814A 0x03E4
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#define REG_DBI_WDATA_V1_8814A 0x03E8
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#define REG_DBI_RDATA_V1_8814A 0x03EC
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#define REG_DBI_FLAG_V1_8814A 0x03F0
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#define REG_MDIO_V1_8814A 0x03F4
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#define REG_PCIE_MIX_CFG_8814A 0x03F8
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#define REG_DBG_8814A 0x03FC
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/* -----------------------------------------------------
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*
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* 0x0400h ~ 0x047Fh Protocol Configuration
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*
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* ----------------------------------------------------- */
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#define REG_VOQ_INFORMATION_8814A 0x0400
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#define REG_VIQ_INFORMATION_8814A 0x0404
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#define REG_BEQ_INFORMATION_8814A 0x0408
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#define REG_BKQ_INFORMATION_8814A 0x040C
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#define REG_MGQ_INFORMATION_8814A 0x0410
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#define REG_HGQ_INFORMATION_8814A 0x0414
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#define REG_BCNQ_INFORMATION_8814A 0x0418
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#define REG_TXPKT_EMPTY_8814A 0x041A
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#define REG_CPU_MGQ_INFORMATION_8814A 0x041C
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#define REG_FWHW_TXQ_CTRL_8814A 0x0420
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#define REG_HWSEQ_CTRL_8814A 0x0423
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#define REG_TXPKTBUF_BCNQ_BDNY_8814A 0x0424
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/* #define REG_MGQ_BDNY_8814A 0x0425 */
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#define REG_LIFETIME_EN_8814A 0x0426
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/* #define REG_FW_FREE_TAIL_8814A 0x0427 */
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#define REG_SPEC_SIFS_8814A 0x0428
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#define REG_RETRY_LIMIT_8814A 0x042A
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#define REG_TXBF_CTRL_8814A 0x042C
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#define REG_DARFRC_8814A 0x0430
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#define REG_RARFRC_8814A 0x0438
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#define REG_RRSR_8814A 0x0440
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#define REG_ARFR0_8814A 0x0444
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#define REG_ARFR1_8814A 0x044C
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#define REG_CCK_CHECK_8814A 0x0454
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#define REG_AMPDU_MAX_TIME_8814A 0x0455
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#define REG_TXPKTBUF_BCNQ1_BDNY_8814A 0x0456
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#define REG_AMPDU_MAX_LENGTH_8814A 0x0458
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#define REG_ACQ_STOP_8814A 0x045C
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#define REG_NDPA_RATE_8814A 0x045D
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#define REG_TX_HANG_CTRL_8814A 0x045E
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#define REG_NDPA_OPT_CTRL_8814A 0x045F
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#define REG_FAST_EDCA_CTRL_8814A 0x0460
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#define REG_RD_RESP_PKT_TH_8814A 0x0463
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#define REG_CMDQ_INFO_8814A 0x0464
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#define REG_Q4_INFO_8814A 0x0468
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#define REG_Q5_INFO_8814A 0x046C
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#define REG_Q6_INFO_8814A 0x0470
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#define REG_Q7_INFO_8814A 0x0474
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#define REG_WMAC_LBK_BUF_HD_8814A 0x0478
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#define REG_MGQ_PGBNDY_8814A 0x047A
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#define REG_INIRTS_RATE_SEL_8814A 0x0480
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#define REG_BASIC_CFEND_RATE_8814A 0x0481
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#define REG_STBC_CFEND_RATE_8814A 0x0482
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#define REG_DATA_SC_8814A 0x0483
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#define REG_MACID_SLEEP3_8814A 0x0484
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#define REG_MACID_SLEEP1_8814A 0x0488
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#ifdef CONFIG_WOWLAN
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#define REG_TXPKTBUF_IV_LOW 0x0484
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#define REG_TXPKTBUF_IV_HIGH 0x0488
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#endif /* CONFIG_WOWLAN */
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#define REG_ARFR2_8814A 0x048C
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#define REG_ARFR3_8814A 0x0494
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#define REG_ARFR4_8814A 0x049C
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#define REG_ARFR5_8814A 0x04A4
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#define REG_TXRPT_START_OFFSET_8814A 0x04AC
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#define REG_TRYING_CNT_TH_8814A 0x04B0
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#define REG_POWER_STAGE1_8814A 0x04B4
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#define REG_POWER_STAGE2_8814A 0x04B8
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#define REG_SW_AMPDU_BURST_MODE_CTRL_8814A 0x04BC
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#define REG_PKT_LIFE_TIME_8814A 0x04C0
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#define REG_PKT_BE_BK_LIFE_TIME_8814A 0x04C2 /* ?????? */
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#define REG_STBC_SETTING_8814A 0x04C4
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#define REG_STBC_8814A 0x04C5
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#define REG_QUEUE_CTRL_8814A 0x04C6
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#define REG_SINGLE_AMPDU_CTRL_8814A 0x04C7
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#define REG_PROT_MODE_CTRL_8814A 0x04C8
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#define REG_MAX_AGGR_NUM_8814A 0x04CA
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#define REG_RTS_MAX_AGGR_NUM_8814A 0x04CB
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#define REG_BAR_MODE_CTRL_8814A 0x04CC
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#define REG_RA_TRY_RATE_AGG_LMT_8814A 0x04CF
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#define REG_MACID_SLEEP2_8814A 0x04D0
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#define REG_MACID_SLEEP0_8814A 0x04D4
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#define REG_HW_SEQ0_8814A 0x04D8
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#define REG_HW_SEQ1_8814A 0x04DA
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#define REG_HW_SEQ2_8814A 0x04DC
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#define REG_HW_SEQ3_8814A 0x04DE
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#define REG_NULL_PKT_STATUS_8814A 0x04E0
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#define REG_PTCL_ERR_STATUS_8814A 0x04E2
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#define REG_DROP_PKT_NUM_8814A 0x04EC
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#define REG_PTCL_TX_RPT_8814A 0x04F0
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#define REG_Dummy_8814A 0x04FC
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/* -----------------------------------------------------
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*
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* 0x0500h ~ 0x05FFh EDCA Configuration
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*
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* ----------------------------------------------------- */
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#define REG_EDCA_VO_PARAM_8814A 0x0500
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#define REG_EDCA_VI_PARAM_8814A 0x0504
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#define REG_EDCA_BE_PARAM_8814A 0x0508
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#define REG_EDCA_BK_PARAM_8814A 0x050C
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#define REG_BCNTCFG_8814A 0x0510
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#define REG_PIFS_8814A 0x0512
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#define REG_RDG_PIFS_8814A 0x0513
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#define REG_SIFS_CTX_8814A 0x0514
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#define REG_SIFS_TRX_8814A 0x0516
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#define REG_AGGR_BREAK_TIME_8814A 0x051A
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#define REG_SLOT_8814A 0x051B
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#define REG_TX_PTCL_CTRL_8814A 0x0520
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#define REG_TXPAUSE_8814A 0x0522
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#define REG_DIS_TXREQ_CLR_8814A 0x0523
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#define REG_RD_CTRL_8814A 0x0524
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/*
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* Format for offset 540h-542h:
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* [3:0]: TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT.
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* [7:4]: Reserved.
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* [19:8]: TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet.
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* [23:20]: Reserved
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* Description:
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* |
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* |<--Setup--|--Hold------------>|
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* --------------|----------------------
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* |
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* TBTT
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* Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold.
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* Described by Designer Tim and Bruce, 2011-01-14.
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* */
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#define REG_TBTT_PROHIBIT_8814A 0x0540
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#define REG_RD_NAV_NXT_8814A 0x0544
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#define REG_NAV_PROT_LEN_8814A 0x0546
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#define REG_BCN_CTRL_8814A 0x0550
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#define REG_BCN_CTRL_1_8814A 0x0551
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#define REG_MBID_NUM_8814A 0x0552
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#define REG_DUAL_TSF_RST_8814A 0x0553
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#define REG_MBSSID_BCN_SPACE_8814A 0x0554
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#define REG_DRVERLYINT_8814A 0x0558
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#define REG_BCNDMATIM_8814A 0x0559
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#define REG_ATIMWND_8814A 0x055A
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#define REG_USTIME_TSF_8814A 0x055C
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#define REG_BCN_MAX_ERR_8814A 0x055D
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#define REG_RXTSF_OFFSET_CCK_8814A 0x055E
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#define REG_RXTSF_OFFSET_OFDM_8814A 0x055F
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#define REG_TSFTR_8814A 0x0560
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#define REG_CTWND_8814A 0x0572
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#define REG_SECONDARY_CCA_CTRL_8814A 0x0577 /* ?????? */
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#define REG_PSTIMER_8814A 0x0580
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#define REG_TIMER0_8814A 0x0584
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#define REG_TIMER1_8814A 0x0588
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#define REG_BCN_PREDL_ITV_8814A 0x058F /* Pre download beacon interval */
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#define REG_ACMHWCTRL_8814A 0x05C0
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#define REG_P2P_RST_8814A 0x05F0
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/* -----------------------------------------------------
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*
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* 0x0600h ~ 0x07FFh WMAC Configuration
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*
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* ----------------------------------------------------- */
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#define REG_MAC_CR_8814A 0x0600
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#define REG_TCR_8814A 0x0604
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#define REG_RCR_8814A 0x0608
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#define REG_RX_PKT_LIMIT_8814A 0x060C
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#define REG_RX_DLK_TIME_8814A 0x060D
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#define REG_RX_DRVINFO_SZ_8814A 0x060F
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#define REG_MACID_8814A 0x0610
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#define REG_BSSID_8814A 0x0618
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#define REG_MAR_8814A 0x0620
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#define REG_MBIDCAMCFG_8814A 0x0628
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#define REG_USTIME_EDCA_8814A 0x0638
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#define REG_MAC_SPEC_SIFS_8814A 0x063A
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#define REG_RESP_SIFP_CCK_8814A 0x063C
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#define REG_RESP_SIFS_OFDM_8814A 0x063E
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#define REG_ACKTO_8814A 0x0640
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#define REG_CTS2TO_8814A 0x0641
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#define REG_EIFS_8814A 0x0642
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#define REG_NAV_UPPER_8814A 0x0652 /* unit of 128 */
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#define REG_TRXPTCL_CTL_8814A 0x0668
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/* Security */
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#define REG_CAMCMD_8814A 0x0670
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#define REG_CAMWRITE_8814A 0x0674
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#define REG_CAMREAD_8814A 0x0678
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#define REG_CAMDBG_8814A 0x067C
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#define REG_SECCFG_8814A 0x0680
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/* Power */
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#define REG_WOW_CTRL_8814A 0x0690
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#define REG_PS_RX_INFO_8814A 0x0692
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#define REG_UAPSD_TID_8814A 0x0693
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#define REG_WKFMCAM_NUM_8814A 0x0698
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#define REG_RXFLTMAP0_8814A 0x06A0
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#define REG_RXFLTMAP1_8814A 0x06A2
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#define REG_RXFLTMAP2_8814A 0x06A4
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#define REG_BCN_PSR_RPT_8814A 0x06A8
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#define REG_BT_COEX_TABLE_8814A 0x06C0
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#define REG_TX_DATA_RSP_RATE_8814A 0x06DE
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#define REG_ASSOCIATED_BFMER0_INFO_8814A 0x06E4
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#define REG_ASSOCIATED_BFMER1_INFO_8814A 0x06EC
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#define REG_CSI_RPT_PARAM_BW20_8814A 0x06F4
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#define REG_CSI_RPT_PARAM_BW40_8814A 0x06F8
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#define REG_CSI_RPT_PARAM_BW80_8814A 0x06FC
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/* Hardware Port 2 */
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#define REG_MACID1_8814A 0x0700
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#define REG_BSSID1_8814A 0x0708
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/* Hardware Port 3 */
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#define REG_MACID2_8814A 0x1620
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#define REG_BSSID2_8814A 0x1628
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/* Hardware Port 4 */
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#define REG_MACID3_8814A 0x1630
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#define REG_BSSID3_8814A 0x1638
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/* Hardware Port 5 */
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#define REG_MACID4_8814A 0x1640
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#define REG_BSSID4_8814A 0x1648
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#define REG_ASSOCIATED_BFMEE_SEL_8814A 0x0714
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#define REG_SND_PTCL_CTRL_8814A 0x0718
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#define REG_IQ_DUMP_8814A 0x07C0
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#define REG_CPU_DMEM_CON_8814A 0x1080
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/**** page 19 ****/
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/* TX BeamForming */
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#define REG_BB_TXBF_ANT_SET_BF1 0x19ac
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#define REG_BB_TXBF_ANT_SET_BF0 0x19b4
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/* 0x1200h ~ 0x12FFh DDMA CTRL
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*
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* ----------------------------------------------------- */
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#define REG_DDMA_CH0SA 0x1200
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#define REG_DDMA_CH0DA 0x1204
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#define REG_DDMA_CH0CTRL 0x1208
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#define REG_DDMA_CH1SA 0x1210
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#define REG_DDMA_CH1DA 0x1214
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#define REG_DDMA_CH1CTRL 0x1218
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#define REG_DDMA_CH2SA 0x1220
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#define REG_DDMA_CH2DA 0x1224
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#define REG_DDMA_CH2CTRL 0x1228
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#define REG_DDMA_CH3SA 0x1230
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#define REG_DDMA_CH3DA 0x1234
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#define REG_DDMA_CH3CTRL 0x1238
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#define REG_DDMA_CH4SA 0x1240
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#define REG_DDMA_CH4DA 0x1244
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#define REG_DDMA_CH4CTRL 0x1248
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#define REG_DDMA_CH5SA 0x1250
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#define REG_DDMA_CH5DA 0x1254
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#define REG_DDMA_CH5CTRL 0x1258
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#define REG_DDMA_INT_MSK 0x12E0
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#define REG_DDMA_CHSTATUS 0x12E8
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#define REG_DDMA_CHKSUM 0x12F0
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#define REG_DDMA_MONITER 0x12FC
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#define REG_Q0_Q1_INFO_8814A 0x1400
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#define REG_Q2_Q3_INFO_8814A 0x1404
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#define REG_Q4_Q5_INFO_8814A 0x1408
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#define REG_Q6_Q7_INFO_8814A 0x140C
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#define REG_MGQ_HIQ_INFO_8814A 0x1410
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#define REG_CMDQ_BCNQ_INFO_8814A 0x1414
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#define DDMA_LEN_MASK 0x0001FFFF
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#define FW_CHKSUM_DUMMY_SZ 8
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#define DDMA_CH_CHKSUM_CNT BIT(24)
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#define DDMA_RST_CHKSUM_STS BIT(25)
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#define DDMA_MODE_BLOCK_CPU BIT(26)
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#define DDMA_CHKSUM_FAIL BIT(27)
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#define DDMA_DA_W_DISABLE BIT(28)
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#define DDMA_CHKSUM_EN BIT(29)
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#define DDMA_CH_OWN BIT(31)
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/* 3081 FWDL */
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#define FWDL_EN BIT0
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#define IMEM_BOOT_DL_RDY BIT1
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#define IMEM_BOOT_CHKSUM_FAIL BIT2
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#define IMEM_DL_RDY BIT3
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#define IMEM_CHKSUM_OK BIT4
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#define DMEM_DL_RDY BIT5
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#define DMEM_CHKSUM_OK BIT6
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#define EMEM_DL_RDY BIT7
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#define EMEM_CHKSUM_FAIL BIT8
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#define EMEM_TXBUF_DL_RDY BIT9
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#define EMEM_TXBUF_CHKSUM_FAIL BIT10
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|
|
#define CPU_CLK_SWITCH_BUSY BIT11
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|
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#define CPU_CLK_SEL (BIT12 | BIT13)
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#define FWDL_OK BIT14
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|
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#define FW_INIT_RDY BIT15
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#define R_EN_BOOT_FLASH BIT20
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#define OCPBASE_IMEM_3081 0x00000000
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#define OCPBASE_DMEM_3081 0x00200000
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#define OCPBASE_RPTBUF_3081 0x18660000
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#define OCPBASE_RXBUF2_3081 0x18680000
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#define OCPBASE_RXBUF_3081 0x18700000
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#define OCPBASE_TXBUF_3081 0x18780000
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#define REG_FAST_EDCA_VOVI_SETTING_8814A 0x1448
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#define REG_FAST_EDCA_BEBK_SETTING_8814A 0x144C
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/* -----------------------------------------------------
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* */
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/* -----------------------------------------------------
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*
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* Redifine 8192C register definition for compatibility
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*
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* ----------------------------------------------------- */
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/* TODO: use these definition when using REG_xxx naming rule.
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* NOTE: DO NOT Remove these definition. Use later. */
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#define EFUSE_CTRL_8814A REG_EFUSE_CTRL_8814A /* E-Fuse Control. */
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#define EFUSE_TEST_8814A REG_LDO_EFUSE_CTRL_8814A /* E-Fuse Test. */
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#define MSR_8814A (REG_CR_8814A + 2) /* Media Status register */
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#define ISR_8814A REG_HISR0_8814A
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#define TSFR_8814A REG_TSFTR_8814A /* Timing Sync Function Timer Register. */
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#define PBP_8814A REG_PBP_8814A
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/* Redifine MACID register, to compatible prior ICs. */
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#define IDR0_8814A REG_MACID_8814A /* MAC ID Register, Offset 0x0050-0x0053 */
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#define IDR4_8814A (REG_MACID_8814A + 4) /* MAC ID Register, Offset 0x0054-0x0055 */
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/*
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* 9. Security Control Registers (Offset: )
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* */
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#define RWCAM_8814A REG_CAMCMD_8814A /* IN 8190 Data Sheet is called CAMcmd */
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#define WCAMI_8814A REG_CAMWRITE_8814A /* Software write CAM input content */
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#define RCAMO_8814A REG_CAMREAD_8814A /* Software read/write CAM config */
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#define CAMDBG_8814A REG_CAMDBG_8814A
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#define SECR_8814A REG_SECCFG_8814A /* Security Configuration Register */
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/* ----------------------------------------------------------------------------
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* 8195 IMR/ISR bits (offset 0xB0, 8bits)
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* ---------------------------------------------------------------------------- */
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#define IMR_DISABLED_8814A 0
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/* IMR DW0(0x00B0-00B3) Bit 0-31 */
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#define IMR_TIMER2_8814A BIT31 /* Timeout interrupt 2 */
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#define IMR_TIMER1_8814A BIT30 /* Timeout interrupt 1 */
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#define IMR_PSTIMEOUT_8814A BIT29 /* Power Save Time Out Interrupt */
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#define IMR_GTINT4_8814A BIT28 /* When GTIMER4 expires, this bit is set to 1 */
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#define IMR_GTINT3_8814A BIT27 /* When GTIMER3 expires, this bit is set to 1 */
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#define IMR_TXBCN0ERR_8814A BIT26 /* Transmit Beacon0 Error */
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#define IMR_TXBCN0OK_8814A BIT25 /* Transmit Beacon0 OK */
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#define IMR_TSF_BIT32_TOGGLE_8814A BIT24 /* TSF Timer BIT32 toggle indication interrupt */
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#define IMR_BCNDMAINT0_8814A BIT20 /* Beacon DMA Interrupt 0 */
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#define IMR_BCNDERR0_8814A BIT16 /* Beacon Queue DMA OK0 */
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#define IMR_HSISR_IND_ON_INT_8814A BIT15 /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */
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#define IMR_BCNDMAINT_E_8814A BIT14 /* Beacon DMA Interrupt Extension for Win7 */
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#define IMR_ATIMEND_8814A BIT12 /* CTWidnow End or ATIM Window End */
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#define IMR_C2HCMD_8814A BIT10 /* CPU to Host Command INT Status, Write 1 clear */
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#define IMR_CPWM2_8814A BIT9 /* CPU power Mode exchange INT Status, Write 1 clear */
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#define IMR_CPWM_8814A BIT8 /* CPU power Mode exchange INT Status, Write 1 clear */
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#define IMR_HIGHDOK_8814A BIT7 /* High Queue DMA OK */
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#define IMR_MGNTDOK_8814A BIT6 /* Management Queue DMA OK */
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#define IMR_BKDOK_8814A BIT5 /* AC_BK DMA OK */
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#define IMR_BEDOK_8814A BIT4 /* AC_BE DMA OK */
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#define IMR_VIDOK_8814A BIT3 /* AC_VI DMA OK */
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#define IMR_VODOK_8814A BIT2 /* AC_VO DMA OK */
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#define IMR_RDU_8814A BIT1 /* Rx Descriptor Unavailable */
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#define IMR_ROK_8814A BIT0 /* Receive DMA OK */
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/* IMR DW1(0x00B4-00B7) Bit 0-31 */
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#define IMR_MCUERR_8814A BIT28 /* Beacon DMA Interrupt 7 */
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#define IMR_BCNDMAINT7_8814A BIT27 /* Beacon DMA Interrupt 7 */
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#define IMR_BCNDMAINT6_8814A BIT26 /* Beacon DMA Interrupt 6 */
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#define IMR_BCNDMAINT5_8814A BIT25 /* Beacon DMA Interrupt 5 */
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#define IMR_BCNDMAINT4_8814A BIT24 /* Beacon DMA Interrupt 4 */
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#define IMR_BCNDMAINT3_8814A BIT23 /* Beacon DMA Interrupt 3 */
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#define IMR_BCNDMAINT2_8814A BIT22 /* Beacon DMA Interrupt 2 */
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#define IMR_BCNDMAINT1_8814A BIT21 /* Beacon DMA Interrupt 1 */
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#define IMR_BCNDOK7_8814A BIT20 /* Beacon Queue DMA OK Interrup 7 */
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#define IMR_BCNDOK6_8814A BIT19 /* Beacon Queue DMA OK Interrup 6 */
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#define IMR_BCNDOK5_8814A BIT18 /* Beacon Queue DMA OK Interrup 5 */
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#define IMR_BCNDOK4_8814A BIT17 /* Beacon Queue DMA OK Interrup 4 */
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#define IMR_BCNDOK3_8814A BIT16 /* Beacon Queue DMA OK Interrup 3 */
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#define IMR_BCNDOK2_8814A BIT15 /* Beacon Queue DMA OK Interrup 2 */
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#define IMR_BCNDOK1_8814A BIT14 /* Beacon Queue DMA OK Interrup 1 */
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#define IMR_ATIMEND_E_8814A BIT13 /* ATIM Window End Extension for Win7 */
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#define IMR_TXERR_8814A BIT11 /* Tx Error Flag Interrupt Status, write 1 clear. */
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#define IMR_RXERR_8814A BIT10 /* Rx Error Flag INT Status, Write 1 clear */
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#define IMR_TXFOVW_8814A BIT9 /* Transmit FIFO Overflow */
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#define IMR_RXFOVW_8814A BIT8 /* Receive FIFO Overflow */
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#ifdef CONFIG_PCI_HCI
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#define IMR_TX_MASK (IMR_VODOK_8814A | IMR_VIDOK_8814A | IMR_BEDOK_8814A | IMR_BKDOK_8814A | IMR_MGNTDOK_8814A | IMR_HIGHDOK_8814A)
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#define RT_BCN_INT_MASKS (IMR_BCNDMAINT0_8814A | IMR_TXBCN0OK_8814A | IMR_TXBCN0ERR_8814A | IMR_BCNDERR0_8814A)
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#define RT_AC_INT_MASKS (IMR_VIDOK_8814A | IMR_VODOK_8814A | IMR_BEDOK_8814A | IMR_BKDOK_8814A)
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#endif
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/*===================================================================
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=====================================================================
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Here the register defines are for 92C. When the define is as same with 92C,
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we will use the 92C's define for the consistency
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So the following defines for 92C is not entire!!!!!!
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=====================================================================
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=====================================================================*/
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/* -----------------------------------------------------
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*
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* 0xFE00h ~ 0xFE55h USB Configuration
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*
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* ----------------------------------------------------- */
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/* 2 Special Option */
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#define USB_AGG_EN_8814A BIT(7)
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#define REG_USB_HRPWM_U3 0xF052
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#define LAST_ENTRY_OF_TX_PKT_BUFFER_8814A (2048-1) /* 20130415 KaiYuan add for 8814 */
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#endif /* __RTL8814A_SPEC_H__ */
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