mirror of
https://github.com/Mange/rtl8192eu-linux-driver
synced 2024-11-24 06:25:02 +00:00
95 lines
2.9 KiB
C
95 lines
2.9 KiB
C
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2017 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#ifndef __PHYDM_MP_H__
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#define __PHYDM_MP_H__
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#define MP_VERSION "1.0"
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/* @1 ============================================================
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* 1 Definition
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* 1 ============================================================
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*/
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/* @1 ============================================================
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* 1 structure
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* 1 ============================================================
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*/
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struct phydm_mp {
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/* @Rx OK count, statistics used in Mass Production Test.*/
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u64 tx_phy_ok_cnt;
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u64 rx_phy_ok_cnt;
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/* @Rx CRC32 error count, statistics used in Mass Production Test.*/
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u64 rx_phy_crc_err_cnt;
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/* @The Value of IO operation is depend of MptActType.*/
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u32 io_value;
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u32 rf_reg0;
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/* @u32 rfe_sel_a_0;*/
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/* @u32 rfe_sel_b_0;*/
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/* @u32 rfe_sel_c_0;*/
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/* @u32 rfe_sel_d_0;*/
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/* @u32 rfe_sel_a_1;*/
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/* @u32 rfe_sel_b_1;*/
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/* @u32 rfe_sel_c_1;*/
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/* @u32 rfe_sel_d_1;*/
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};
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/* @1 ============================================================
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* 1 enumeration
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* 1 ============================================================
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*/
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enum TX_MODE_OFDM {
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OFDM_OFF = 0,
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OFDM_CONT_TX = 1,
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OFDM_SINGLE_CARRIER = 2,
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OFDM_SINGLE_TONE = 4,
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};
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/* @1 ============================================================
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* 1 function prototype
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* 1 ============================================================
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*/
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#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
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void phydm_mp_set_single_tone_jgr3(void *dm_void, boolean is_single_tone,
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u8 path);
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void phydm_mp_set_carrier_supp_jgr3(void *dm_void, boolean is_carrier_supp,
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u32 rate_index);
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#endif
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void phydm_mp_set_crystal_cap(void *dm_void, u8 crystal_cap);
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void phydm_mp_set_single_tone(void *dm_void, boolean is_single_tone, u8 path);
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void phydm_mp_set_carrier_supp(void *dm_void, boolean is_carrier_supp,
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u32 rate_index);
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void phydm_mp_set_single_carrier(void *dm_void, boolean is_single_carrier);
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void phydm_mp_reset_rx_counters_phy(void *dm_void);
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void phydm_mp_get_tx_ok(void *dm_void, u32 rate_index);
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void phydm_mp_get_rx_ok(void *dm_void);
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#endif
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