mirror of
https://github.com/Mange/rtl8192eu-linux-driver
synced 2024-11-24 14:34:58 +00:00
301 lines
9.6 KiB
C
301 lines
9.6 KiB
C
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2017 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#include "mp_precomp.h"
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#include "phydm_precomp.h"
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void odm_bub_sort(u32 *data, u32 n)
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{
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int i, j, temp, sp;
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for (i = n - 1; i >= 0; i--) {
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sp = 1;
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for (j = 0; j < i; j++) {
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if (data[j] < data[j + 1]) {
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temp = data[j];
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data[j] = data[j + 1];
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data[j + 1] = temp;
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sp = 0;
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}
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}
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if (sp == 1)
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break;
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}
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}
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#if (RTL8197F_SUPPORT == 1)
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u4Byte
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odm_tx_gain_gap_psd_8197f(
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void *dm_void,
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u1Byte rf_path,
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u4Byte rf56)
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{
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PDM_ODM_T dm = (PDM_ODM_T)dm_void;
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u1Byte i, j;
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u4Byte psd_vaule[5], psd_avg_time = 5, psd_vaule_temp;
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u4Byte iqk_ctl_addr[2][6] = {{0xe30, 0xe34, 0xe50, 0xe54, 0xe38, 0xe3c},
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{0xe50, 0xe54, 0xe30, 0xe34, 0xe58, 0xe5c}};
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u4Byte psd_finish_bit[2] = {0x04000000, 0x20000000};
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u4Byte psd_fail_bit[2] = {0x08000000, 0x40000000};
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u4Byte psd_cntl_value[2][2] = {{0x38008c1c, 0x10008c1c},
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{0x38008c2c, 0x10008c2c}};
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u4Byte psd_report_addr[2] = {0xea0, 0xec0};
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odm_set_rf_reg(dm, rf_path, RF_0xdf, bRFRegOffsetMask, 0x00e02);
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ODM_delay_us(100);
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odm_set_bb_reg(dm, R_0xe28, 0xffffffff, 0x0);
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odm_set_rf_reg(dm, rf_path, RF_0x56, 0xfff, rf56);
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while (rf56 != (odm_get_rf_reg(dm, rf_path, RF_0x56, 0xfff)))
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odm_set_rf_reg(dm, rf_path, RF_0x56, 0xfff, rf56);
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odm_set_bb_reg(dm, R_0xd94, 0xffffffff, 0x44FFBB44);
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odm_set_bb_reg(dm, R_0xe70, 0xffffffff, 0x00400040);
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odm_set_bb_reg(dm, R_0xc04, 0xffffffff, 0x6f005403);
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odm_set_bb_reg(dm, R_0xc08, 0xffffffff, 0x000804e4);
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odm_set_bb_reg(dm, R_0x874, 0xffffffff, 0x04203400);
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odm_set_bb_reg(dm, R_0xe28, 0xffffffff, 0x80800000);
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odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][0], 0xffffffff, psd_cntl_value[rf_path][0]);
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odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][1], 0xffffffff, psd_cntl_value[rf_path][1]);
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odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][2], 0xffffffff, psd_cntl_value[rf_path][0]);
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odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][3], 0xffffffff, psd_cntl_value[rf_path][0]);
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odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][4], 0xffffffff, 0x8215001F);
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odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][5], 0xffffffff, 0x2805001F);
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odm_set_bb_reg(dm, R_0xe40, 0xffffffff, 0x81007C00);
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odm_set_bb_reg(dm, R_0xe44, 0xffffffff, 0x81004800);
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odm_set_bb_reg(dm, R_0xe4c, 0xffffffff, 0x0046a8d0);
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for (i = 0; i < psd_avg_time; i++) {
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for (j = 0; j < 1000; j++) {
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odm_set_bb_reg(dm, R_0xe48, 0xffffffff, 0xfa005800);
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odm_set_bb_reg(dm, R_0xe48, 0xffffffff, 0xf8005800);
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while (!odm_get_bb_reg(dm, R_0xeac, psd_finish_bit[rf_path]))
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; /*wait finish bit*/
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if (!odm_get_bb_reg(dm, R_0xeac, psd_fail_bit[rf_path])) { /*check fail bit*/
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psd_vaule[i] = odm_get_bb_reg(dm, psd_report_addr[rf_path], 0xffffffff);
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if (psd_vaule[i] > 0xffff)
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break;
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}
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}
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RF_DBG(dm, DBG_RF_IQK,
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"[TGGC] rf0=0x%x rf56=0x%x rf56_reg=0x%x time=%d psd_vaule=0x%x\n",
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odm_get_rf_reg(dm, rf_path, RF_0x0, 0xff), rf56,
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odm_get_rf_reg(dm, rf_path, RF_0x56, 0xfff), j,
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psd_vaule[i]);
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}
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odm_bub_sort(psd_vaule, psd_avg_time);
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psd_vaule_temp = psd_vaule[(UINT)(psd_avg_time / 2)];
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odm_set_bb_reg(dm, R_0xd94, 0xffffffff, 0x44BBBB44);
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odm_set_bb_reg(dm, R_0xe70, 0xffffffff, 0x80408040);
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odm_set_bb_reg(dm, R_0xc04, 0xffffffff, 0x6f005433);
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odm_set_bb_reg(dm, R_0xc08, 0xffffffff, 0x000004e4);
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odm_set_bb_reg(dm, R_0x874, 0xffffffff, 0x04003400);
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odm_set_bb_reg(dm, R_0xe28, 0xffffffff, 0x00000000);
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RF_DBG(dm, DBG_RF_IQK,
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"[TGGC] rf0=0x%x rf56=0x%x rf56_reg=0x%x psd_vaule_temp=0x%x\n",
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odm_get_rf_reg(dm, rf_path, RF_0x0, 0xff), rf56,
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odm_get_rf_reg(dm, rf_path, RF_0x56, 0xfff), psd_vaule_temp);
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odm_set_rf_reg(dm, rf_path, RF_0xdf, bRFRegOffsetMask, 0x00602);
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return psd_vaule_temp;
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}
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void odm_tx_gain_gap_calibration_8197f(
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void *dm_void)
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{
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PDM_ODM_T dm = (PDM_ODM_T)dm_void;
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u1Byte rf_path, rf0_idx, rf0_idx_current, rf0_idx_next, i, delta_gain_retry = 3;
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s1Byte delta_gain_gap_pre, delta_gain_gap[2][11];
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u4Byte rf56_current, rf56_next, psd_value_current, psd_value_next;
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u4Byte psd_gap, rf56_current_temp[2][11];
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s4Byte rf33[2][11];
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memset(rf33, 0x0, sizeof(rf33));
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for (rf_path = RF_PATH_A; rf_path <= RF_PATH_B; rf_path++) {
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if (rf_path == RF_PATH_A)
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odm_set_bb_reg(dm, R_0x88c, (BIT(21) | BIT(20)), 0x3); /*disable 3-wire*/
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else if (rf_path == RF_PATH_B)
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odm_set_bb_reg(dm, R_0x88c, (BIT(23) | BIT(22)), 0x3); /*disable 3-wire*/
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ODM_delay_us(100);
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for (rf0_idx = 1; rf0_idx <= 10; rf0_idx++) {
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rf0_idx_current = 3 * (rf0_idx - 1) + 1;
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odm_set_rf_reg(dm, rf_path, RF_0x0, 0xff, rf0_idx_current);
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ODM_delay_us(100);
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rf56_current_temp[rf_path][rf0_idx] = odm_get_rf_reg(dm, rf_path, RF_0x56, 0xfff);
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rf56_current = rf56_current_temp[rf_path][rf0_idx];
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rf0_idx_next = 3 * rf0_idx + 1;
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odm_set_rf_reg(dm, rf_path, RF_0x0, 0xff, rf0_idx_next);
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ODM_delay_us(100);
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rf56_next = odm_get_rf_reg(dm, rf_path, RF_0x56, 0xfff);
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RF_DBG(dm, DBG_RF_IQK,
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"[TGGC] rf56_current[%d][%d]=0x%x rf56_next[%d][%d]=0x%x\n",
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rf_path, rf0_idx, rf56_current, rf_path, rf0_idx,
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rf56_next);
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if ((rf56_current >> 5) == (rf56_next >> 5)) {
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delta_gain_gap[rf_path][rf0_idx] = 0;
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RF_DBG(dm, DBG_RF_IQK,
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"[TGGC] rf56_current[11:5] == rf56_next[%d][%d][11:5]=0x%x delta_gain_gap[%d][%d]=%d\n",
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rf_path, rf0_idx, (rf56_next >> 5),
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rf_path, rf0_idx,
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delta_gain_gap[rf_path][rf0_idx]);
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continue;
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}
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RF_DBG(dm, DBG_RF_IQK,
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"[TGGC] rf56_current[%d][%d][11:5]=0x%x != rf56_next[%d][%d][11:5]=0x%x\n",
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rf_path, rf0_idx, (rf56_current >> 5), rf_path,
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rf0_idx, (rf56_next >> 5));
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for (i = 0; i < delta_gain_retry; i++) {
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psd_value_current = odm_tx_gain_gap_psd_8197f(dm, rf_path, rf56_current);
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psd_value_next = odm_tx_gain_gap_psd_8197f(dm, rf_path, rf56_next - 2);
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psd_gap = psd_value_next / (psd_value_current / 1000);
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#if 0
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if (psd_gap > 1413)
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delta_gain_gap[rf_path][rf0_idx] = 1;
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else if (psd_gap > 1122)
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delta_gain_gap[rf_path][rf0_idx] = 0;
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else
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delta_gain_gap[rf_path][rf0_idx] = -1;
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#endif
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if (psd_gap > 1445)
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delta_gain_gap[rf_path][rf0_idx] = 1;
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else if (psd_gap > 1096)
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delta_gain_gap[rf_path][rf0_idx] = 0;
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else
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delta_gain_gap[rf_path][rf0_idx] = -1;
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if (i == 0)
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delta_gain_gap_pre = delta_gain_gap[rf_path][rf0_idx];
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RF_DBG(dm, DBG_RF_IQK,
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"[TGGC] psd_value_current=0x%x psd_value_next=0x%x psd_value_next/psd_value_current=%d delta_gain_gap[%d][%d]=%d\n",
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psd_value_current, psd_value_next,
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psd_gap, rf_path, rf0_idx,
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delta_gain_gap[rf_path][rf0_idx]);
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if (i == 0 && delta_gain_gap[rf_path][rf0_idx] == 0)
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break;
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if (delta_gain_gap_pre != delta_gain_gap[rf_path][rf0_idx]) {
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delta_gain_gap[rf_path][rf0_idx] = 0;
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RF_DBG(dm, DBG_RF_IQK, "[TGGC] delta_gain_gap_pre(%d) != delta_gain_gap[%d][%d](%d) time=%d\n",
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delta_gain_gap_pre, rf_path, rf0_idx, delta_gain_gap[rf_path][rf0_idx], i);
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break;
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}
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RF_DBG(dm, DBG_RF_IQK,
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"[TGGC] delta_gain_gap_pre(%d) == delta_gain_gap[%d][%d](%d) time=%d\n",
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delta_gain_gap_pre, rf_path, rf0_idx,
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delta_gain_gap[rf_path][rf0_idx], i);
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}
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}
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if (rf_path == RF_PATH_A)
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odm_set_bb_reg(dm, R_0x88c, (BIT(21) | BIT(20)), 0x0); /*enable 3-wire*/
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else if (rf_path == RF_PATH_B)
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odm_set_bb_reg(dm, R_0x88c, (BIT(23) | BIT(22)), 0x0); /*enable 3-wire*/
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ODM_delay_us(100);
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}
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#if 0
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/*odm_set_bb_reg(dm, R_0x88c, (BIT(23) | BIT(22) | BIT(21) | BIT(20)), 0x0);*/ /*enable 3-wire*/
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#endif
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for (rf_path = RF_PATH_A; rf_path <= RF_PATH_B; rf_path++) {
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odm_set_rf_reg(dm, rf_path, RF_0xef, bRFRegOffsetMask, 0x00100);
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for (rf0_idx = 1; rf0_idx <= 10; rf0_idx++) {
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rf33[rf_path][rf0_idx] = rf33[rf_path][rf0_idx] + (rf56_current_temp[rf_path][rf0_idx] & 0x1f);
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for (i = rf0_idx; i <= 10; i++)
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rf33[rf_path][rf0_idx] = rf33[rf_path][rf0_idx] + delta_gain_gap[rf_path][i];
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if (rf33[rf_path][rf0_idx] >= 0x1d)
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rf33[rf_path][rf0_idx] = 0x1d;
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else if (rf33[rf_path][rf0_idx] <= 0x2)
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rf33[rf_path][rf0_idx] = 0x2;
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rf33[rf_path][rf0_idx] = rf33[rf_path][rf0_idx] + ((rf0_idx - 1) * 0x4000) + (rf56_current_temp[rf_path][rf0_idx] & 0xfffe0);
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RF_DBG(dm, DBG_RF_IQK,
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"[TGGC] rf56[%d][%d]=0x%05x rf33[%d][%d]=0x%05x\n",
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rf_path, rf0_idx,
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rf56_current_temp[rf_path][rf0_idx], rf_path,
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rf0_idx, rf33[rf_path][rf0_idx]);
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odm_set_rf_reg(dm, rf_path, RF_0x33, bRFRegOffsetMask, rf33[rf_path][rf0_idx]);
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}
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odm_set_rf_reg(dm, rf_path, RF_0xef, bRFRegOffsetMask, 0x00000);
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|
|
}
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
void odm_tx_gain_gap_calibration(void *dm_void)
|
||
|
|
{
|
||
|
|
PDM_ODM_T dm = (PDM_ODM_T)dm_void;
|
||
|
|
#if (RTL8197F_SUPPORT == 1)
|
||
|
|
if (dm->SupportICType & ODM_RTL8197F)
|
||
|
|
odm_tx_gain_gap_calibration_8197f(dm_void);
|
||
|
|
#endif
|
||
|
|
}
|