mirror of
https://github.com/Mange/rtl8192eu-linux-driver
synced 2024-11-23 14:05:00 +00:00
114 lines
2.8 KiB
C
114 lines
2.8 KiB
C
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2017 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#ifndef __PHYDM_AUTO_DBG_H__
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#define __PHYDM_AUTO_DBG_H__
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#define AUTO_DBG_VERSION "1.0" /* @2017.05.015 Dino, Add phydm_auto_dbg.h*/
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/* @1 ============================================================
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* 1 Definition
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* 1 ============================================================
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*/
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#define AUTO_CHK_HANG_STEP_MAX 3
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#define DBGPORT_CHK_NUM 6
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#ifdef PHYDM_AUTO_DEGBUG
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/* @1 ============================================================
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* 1 enumeration
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* 1 ============================================================
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*/
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enum auto_dbg_type_e {
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AUTO_DBG_STOP = 0,
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AUTO_DBG_CHECK_HANG = 1,
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AUTO_DBG_CHECK_RA = 2,
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AUTO_DBG_CHECK_DIG = 3
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};
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/* @1 ============================================================
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* 1 structure
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* 1 ============================================================
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*/
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struct n_dbgport_803 {
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/*@BYTE 3*/
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u8 bb_rst_b : 1;
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u8 glb_rst_b : 1;
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u8 zero_1bit_1 : 1;
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u8 ofdm_rst_b : 1;
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u8 cck_txpe : 1;
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u8 ofdm_txpe : 1;
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u8 phy_tx_on : 1;
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u8 tdrdy : 1;
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/*@BYTE 2*/
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u8 txd : 8;
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/*@BYTE 1*/
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u8 cck_cca_pp : 1;
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u8 ofdm_cca_pp : 1;
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u8 rx_rst : 1;
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u8 rdrdy : 1;
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u8 rxd_7_4 : 4;
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/*@BYTE 0*/
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u8 rxd_3_0 : 4;
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u8 ofdm_tx_en : 1;
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u8 cck_tx_en : 1;
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u8 zero_1bit_2 : 1;
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u8 clk_80m : 1;
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};
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struct phydm_auto_dbg_struct {
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enum auto_dbg_type_e auto_dbg_type;
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u8 dbg_step;
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u16 dbg_port_table[DBGPORT_CHK_NUM];
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u32 dbg_port_val[DBGPORT_CHK_NUM];
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u16 ofdm_t_cnt;
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u16 ofdm_r_cnt;
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u16 cck_t_cnt;
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u16 cck_r_cnt;
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u16 ofdm_crc_error_cnt;
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u16 cck_crc_error_cnt;
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};
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/* @1 ============================================================
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* 1 function prototype
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* 1 ============================================================
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*/
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void phydm_auto_dbg_console(
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void *dm_void,
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char input[][16],
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u32 *_used,
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char *output,
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u32 *_out_len);
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void phydm_auto_dbg_engine(void *dm_void);
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void phydm_auto_dbg_engine_init(void *dm_void);
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#endif
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#endif
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