mirror of
https://github.com/Mange/rtl8192eu-linux-driver
synced 2024-12-25 21:41:42 +00:00
185 lines
6.6 KiB
C
185 lines
6.6 KiB
C
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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*
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******************************************************************************/
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/*
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============================================================
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include files
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============================================================
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*/
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#include "mp_precomp.h"
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#include "phydm_precomp.h"
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#if defined(CONFIG_PHYDM_DFS_MASTER)
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VOID phydm_radar_detect_reset(PVOID pDM_VOID)
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{
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PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
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ODM_SetBBReg(pDM_Odm, 0x924 , BIT15, 0);
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ODM_SetBBReg(pDM_Odm, 0x924 , BIT15, 1);
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}
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VOID phydm_radar_detect_disable(PVOID pDM_VOID)
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{
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PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
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ODM_SetBBReg(pDM_Odm, 0x924 , BIT15, 0);
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}
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/* Init radar detection parameters, called after ch, bw is set */
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VOID phydm_radar_detect_enable(PVOID pDM_VOID)
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{
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PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
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u1Byte region_domain = pDM_Odm->DFS_RegionDomain;
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u1Byte c_channel = *(pDM_Odm->pChannel);
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if (region_domain == PHYDM_DFS_DOMAIN_UNKNOWN) {
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ODM_RT_TRACE(pDM_Odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("PHYDM_DFS_DOMAIN_UNKNOWN\n"));
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return;
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}
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if (pDM_Odm->SupportICType & (ODM_RTL8821 | ODM_RTL8812 | ODM_RTL8881A)) {
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ODM_SetBBReg(pDM_Odm, 0x814, 0x3fffffff, 0x04cc4d10);
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ODM_SetBBReg(pDM_Odm, 0x834, bMaskByte0, 0x06);
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if (region_domain == PHYDM_DFS_DOMAIN_ETSI) {
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ODM_SetBBReg(pDM_Odm, 0x918, bMaskDWord, 0x1c16ecdf);
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ODM_SetBBReg(pDM_Odm, 0x924, bMaskDWord, 0x0152a400);
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ODM_SetBBReg(pDM_Odm, 0x91c, bMaskDWord, 0x0fa21a20);
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ODM_SetBBReg(pDM_Odm, 0x920, bMaskDWord, 0xe0f57204);
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} else if (region_domain == PHYDM_DFS_DOMAIN_MKK) {
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ODM_SetBBReg(pDM_Odm, 0x924, bMaskDWord, 0x01528400);
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ODM_SetBBReg(pDM_Odm, 0x920, bMaskDWord, 0xe0d67234);
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if (c_channel >= 52 && c_channel <= 64) {
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ODM_SetBBReg(pDM_Odm, 0x918, bMaskDWord, 0x1c16ecdf);
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ODM_SetBBReg(pDM_Odm, 0x91c, bMaskDWord, 0x0f141a20);
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} else {
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ODM_SetBBReg(pDM_Odm, 0x918, bMaskDWord, 0x1c16acdf);
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if (pDM_Odm->pBandWidth == ODM_BW20M)
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ODM_SetBBReg(pDM_Odm, 0x91c, bMaskDWord, 0x64721a20);
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else
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ODM_SetBBReg(pDM_Odm, 0x91c, bMaskDWord, 0x68721a20);
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}
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} else if (region_domain == PHYDM_DFS_DOMAIN_FCC) {
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ODM_SetBBReg(pDM_Odm, 0x918, bMaskDWord, 0x1c16acdf);
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ODM_SetBBReg(pDM_Odm, 0x924, bMaskDWord, 0x0152a400);
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ODM_SetBBReg(pDM_Odm, 0x920, bMaskDWord, 0xe0d67231);
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if (pDM_Odm->pBandWidth == ODM_BW20M)
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ODM_SetBBReg(pDM_Odm, 0x91c, bMaskDWord, 0x64741a20);
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else
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ODM_SetBBReg(pDM_Odm, 0x91c, bMaskDWord, 0x68741a20);
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} else {
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/* not supported */
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ODM_RT_TRACE(pDM_Odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("Unsupported DFS_RegionDomain:%d\n", region_domain));
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}
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} else if (pDM_Odm->SupportICType & (ODM_RTL8814A | ODM_RTL8822B)) {
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ODM_SetBBReg(pDM_Odm, 0x814, 0x3fffffff, 0x04cc4d10);
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ODM_SetBBReg(pDM_Odm, 0x834, bMaskByte0, 0x06);
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/* 8822B only, when BW = 20M, DFIR output is 40Mhz, but DFS input is 80MMHz, so it need to upgrade to 80MHz */
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if (pDM_Odm->SupportICType & ODM_RTL8822B) {
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if (pDM_Odm->pBandWidth == ODM_BW20M)
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ODM_SetBBReg(pDM_Odm, 0x1984, BIT26, 1);
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else
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ODM_SetBBReg(pDM_Odm, 0x1984, BIT26, 0);
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}
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if (region_domain == PHYDM_DFS_DOMAIN_ETSI) {
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ODM_SetBBReg(pDM_Odm, 0x918, bMaskDWord, 0x1c16acdf);
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ODM_SetBBReg(pDM_Odm, 0x924, bMaskDWord, 0x095aa400);
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ODM_SetBBReg(pDM_Odm, 0x91c, bMaskDWord, 0x0fa21a20);
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ODM_SetBBReg(pDM_Odm, 0x920, bMaskDWord, 0xe0f57204);
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} else if (region_domain == PHYDM_DFS_DOMAIN_MKK) {
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ODM_SetBBReg(pDM_Odm, 0x924, bMaskDWord, 0x095aa400);
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ODM_SetBBReg(pDM_Odm, 0x920, bMaskDWord, 0xe0d67234);
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if (c_channel >= 52 && c_channel <= 64) {
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ODM_SetBBReg(pDM_Odm, 0x918, bMaskDWord, 0x1c16ecdf);
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ODM_SetBBReg(pDM_Odm, 0x91c, bMaskDWord, 0x0f141a20);
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} else {
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ODM_SetBBReg(pDM_Odm, 0x918, bMaskDWord, 0x1c166cdf);
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if (pDM_Odm->pBandWidth == ODM_BW20M)
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ODM_SetBBReg(pDM_Odm, 0x91c, bMaskDWord, 0x64721a20);
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else
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ODM_SetBBReg(pDM_Odm, 0x91c, bMaskDWord, 0x68721a20);
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}
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} else if (region_domain == PHYDM_DFS_DOMAIN_FCC) {
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ODM_SetBBReg(pDM_Odm, 0x918, bMaskDWord, 0x1c166cdf);
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ODM_SetBBReg(pDM_Odm, 0x924, bMaskDWord, 0x095aa400);
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ODM_SetBBReg(pDM_Odm, 0x920, bMaskDWord, 0xe0d67231);
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if (pDM_Odm->pBandWidth == ODM_BW20M)
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ODM_SetBBReg(pDM_Odm, 0x91c, bMaskDWord, 0x64741a20);
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else
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ODM_SetBBReg(pDM_Odm, 0x91c, bMaskDWord, 0x68741a20);
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} else {
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/* not supported */
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ODM_RT_TRACE(pDM_Odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("Unsupported DFS_RegionDomain:%d\n", region_domain));
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}
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} else {
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/* not supported IC type*/
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ODM_RT_TRACE(pDM_Odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("Unsupported IC Type:%d\n", pDM_Odm->SupportICType));
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}
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phydm_radar_detect_reset(pDM_Odm);
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}
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BOOLEAN phydm_radar_detect(PVOID pDM_VOID)
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{
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PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
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BOOLEAN enable_DFS = FALSE;
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BOOLEAN bypass = FALSE;
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BOOLEAN radar_detected = FALSE;
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u1Byte region_domain = pDM_Odm->DFS_RegionDomain;
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u4Byte tp_th = ((*pDM_Odm->pBandWidth == ODM_BW40M) ? 45 : 20); /* refer AP team's testing number */
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if (region_domain == PHYDM_DFS_DOMAIN_UNKNOWN) {
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ODM_RT_TRACE(pDM_Odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("PHYDM_DFS_DOMAIN_UNKNOWN\n"));
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return FALSE;
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}
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if ((pDM_Odm->total_tp) > tp_th)
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bypass = TRUE;
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if (ODM_GetBBReg(pDM_Odm , 0x924, BIT15))
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enable_DFS = TRUE;
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if ((ODM_GetBBReg(pDM_Odm , 0xf98, BIT17))
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radar_detected = TRUE;
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ODM_RT_TRACE(pDM_Odm, ODM_COMP_DFS, ODM_DBG_LOUD
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, ("Radar detect: enable_DFS:%d, radar_detected:%d, bypass:%d(throughput:%u, tp_th:%d)\n"
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, enable_DFS, radar_detected, bypass, pDM_Odm->total_tp, tp_th));
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if (enable_DFS && radar_detected)
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phydm_radar_detect_reset(pDM_Odm);
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exit:
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return (enable_DFS && radar_detected && !bypass);
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}
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#endif /* defined(CONFIG_PHYDM_DFS_MASTER) */
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