2019-11-09 10:12:08 +00:00
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2017 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#ifndef __ODM_REGDEFINE11N_H__
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#define __ODM_REGDEFINE11N_H__
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/* @2 RF REG LIST */
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#define ODM_REG_RF_MODE_11N 0x00
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#define ODM_REG_RF_0B_11N 0x0B
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#define ODM_REG_CHNBW_11N 0x18
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#define ODM_REG_T_METER_11N 0x24
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#define ODM_REG_RF_25_11N 0x25
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#define ODM_REG_RF_26_11N 0x26
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#define ODM_REG_RF_27_11N 0x27
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#define ODM_REG_RF_2B_11N 0x2B
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#define ODM_REG_RF_2C_11N 0x2C
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#define ODM_REG_RXRF_A3_11N 0x3C
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#define ODM_REG_T_METER_92D_11N 0x42
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#define ODM_REG_T_METER_88E_11N 0x42
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/* @2 BB REG LIST
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* PAGE 8
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*/
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#define ODM_REG_BB_CTRL_11N 0x800
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#define ODM_REG_RF_PIN_11N 0x804
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#define ODM_REG_PSD_CTRL_11N 0x808
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#define ODM_REG_TX_ANT_CTRL_11N 0x80C
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#define ODM_REG_BB_PWR_SAV5_11N 0x818
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#define ODM_REG_CCK_RPT_FORMAT_11N 0x824
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#define ODM_REG_CCK_RPT_FORMAT_11N_B 0x82C
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#define ODM_REG_RX_DEFAULT_A_11N 0x858
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#define ODM_REG_RX_DEFAULT_B_11N 0x85A
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#define ODM_REG_BB_PWR_SAV3_11N 0x85C
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#define ODM_REG_ANTSEL_CTRL_11N 0x860
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#define ODM_REG_RX_ANT_CTRL_11N 0x864
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#define ODM_REG_PIN_CTRL_11N 0x870
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#define ODM_REG_BB_PWR_SAV1_11N 0x874
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#define ODM_REG_ANTSEL_PATH_11N 0x878
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#define ODM_REG_BB_3WIRE_11N 0x88C
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#define ODM_REG_SC_CNT_11N 0x8C4
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#define ODM_REG_PSD_DATA_11N 0x8B4
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#define ODM_REG_CCX_PERIOD_11N 0x894
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#define ODM_REG_NHM_TH9_TH10_11N 0x890
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#define ODM_REG_CLM_11N 0x890
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#define ODM_REG_NHM_TH3_TO_TH0_11N 0x898
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#define ODM_REG_NHM_TH7_TO_TH4_11N 0x89c
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#define ODM_REG_NHM_TH8_11N 0xe28
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#define ODM_REG_CLM_READY_11N 0x8b4
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#define ODM_REG_CLM_RESULT_11N 0x8d0
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#define ODM_REG_NHM_CNT_11N 0x8d8
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/* @For struct acs_info, Jeffery, 2014-12-26 */
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#define ODM_REG_NHM_CNT7_TO_CNT4_11N 0x8dc
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#define ODM_REG_NHM_CNT9_TO_CNT8_11N 0x8d0
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#define ODM_REG_NHM_CNT10_TO_CNT11_11N 0x8d4
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/* PAGE 9 */
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#define ODM_REG_BB_CTRL_PAGE9_11N 0x900
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#define ODM_REG_DBG_RPT_11N 0x908
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#define ODM_REG_BB_TX_PATH_11N 0x90c
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#define ODM_REG_ANT_MAPPING1_11N 0x914
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#define ODM_REG_ANT_MAPPING2_11N 0x918
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#define ODM_REG_EDCCA_DOWN_OPT_11N 0x948
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#define ODM_REG_RX_DFIR_MOD_97F 0x948
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#define ODM_REG_SOML_97F 0x998
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/* PAGE A */
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#define ODM_REG_CCK_ANTDIV_PARA1_11N 0xA00
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#define ODM_REG_CCK_ANT_SEL_11N 0xA04
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#define ODM_REG_CCK_CCA_11N 0xA0A
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#define ODM_REG_CCK_ANTDIV_PARA2_11N 0xA0C
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#define ODM_REG_CCK_ANTDIV_PARA3_11N 0xA10
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#define ODM_REG_CCK_ANTDIV_PARA4_11N 0xA14
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#define ODM_REG_CCK_FILTER_PARA1_11N 0xA22
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#define ODM_REG_CCK_FILTER_PARA2_11N 0xA23
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#define ODM_REG_CCK_FILTER_PARA3_11N 0xA24
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#define ODM_REG_CCK_FILTER_PARA4_11N 0xA25
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#define ODM_REG_CCK_FILTER_PARA5_11N 0xA26
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#define ODM_REG_CCK_FILTER_PARA6_11N 0xA27
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#define ODM_REG_CCK_FILTER_PARA7_11N 0xA28
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#define ODM_REG_CCK_FILTER_PARA8_11N 0xA29
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#define ODM_REG_CCK_FA_RST_11N 0xA2C
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#define ODM_REG_CCK_FA_MSB_11N 0xA58
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#define ODM_REG_CCK_FA_LSB_11N 0xA5C
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#define ODM_REG_CCK_CCA_CNT_11N 0xA60
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#define ODM_REG_BB_PWR_SAV4_11N 0xA74
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/* PAGE B */
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#define ODM_REG_LNA_SWITCH_11N 0xB2C
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#define ODM_REG_PATH_SWITCH_11N 0xB30
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#define ODM_REG_RSSI_CTRL_11N 0xB38
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#define ODM_REG_CONFIG_ANTA_11N 0xB68
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#define ODM_REG_RSSI_BT_11N 0xB9C
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#define ODM_REG_RXCK_RFMOD 0xBB0
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#define ODM_REG_EDCCA_DCNF_97F 0xBC0
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/* PAGE C */
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#define ODM_REG_OFDM_FA_HOLDC_11N 0xC00
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#define ODM_REG_BB_RX_PATH_11N 0xC04
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#define ODM_REG_TRMUX_11N 0xC08
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#define ODM_REG_OFDM_FA_RSTC_11N 0xC0C
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#define ODM_REG_DOWNSAM_FACTOR_11N 0xC10
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#define ODM_REG_RXIQI_MATRIX_11N 0xC14
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#define ODM_REG_TXIQK_MATRIX_LSB1_11N 0xC4C
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#define ODM_REG_IGI_A_11N 0xC50
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#define ODM_REG_ANTDIV_PARA2_11N 0xC54
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#define ODM_REG_IGI_B_11N 0xC58
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#define ODM_REG_ANTDIV_PARA3_11N 0xC5C
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#define ODM_REG_L1SBD_PD_CH_11N 0XC6C
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#define ODM_REG_BB_PWR_SAV2_11N 0xC70
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#define ODM_REG_BB_AGC_SET_2_11N 0xc74
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#define ODM_REG_RX_OFF_11N 0xC7C
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#define ODM_REG_TXIQK_MATRIXA_11N 0xC80
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#define ODM_REG_TXIQK_MATRIXB_11N 0xC88
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#define ODM_REG_TXIQK_MATRIXA_LSB2_11N 0xC94
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#define ODM_REG_TXIQK_MATRIXB_LSB2_11N 0xC9C
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#define ODM_REG_RXIQK_MATRIX_LSB_11N 0xCA0
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#define ODM_REG_ANTDIV_PARA1_11N 0xCA4
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#define ODM_REG_SMALL_BANDWIDTH_11N 0xCE4
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#define ODM_REG_OFDM_FA_TYPE1_11N 0xCF0
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/* PAGE D */
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#define ODM_REG_OFDM_FA_RSTD_11N 0xD00
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#define ODM_REG_BB_RX_ANT_11N 0xD04
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#define ODM_REG_BB_ATC_11N 0xD2C
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#define ODM_REG_OFDM_FA_TYPE2_11N 0xDA0
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#define ODM_REG_OFDM_FA_TYPE3_11N 0xDA4
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#define ODM_REG_OFDM_FA_TYPE4_11N 0xDA8
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#define ODM_REG_RPT_11N 0xDF4
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/* PAGE E */
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#define ODM_REG_TXAGC_A_6_18_11N 0xE00
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#define ODM_REG_TXAGC_A_24_54_11N 0xE04
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#define ODM_REG_TXAGC_A_1_MCS32_11N 0xE08
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#define ODM_REG_TXAGC_A_MCS0_3_11N 0xE10
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#define ODM_REG_TXAGC_A_MCS4_7_11N 0xE14
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#define ODM_REG_TXAGC_A_MCS8_11_11N 0xE18
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#define ODM_REG_TXAGC_A_MCS12_15_11N 0xE1C
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#define ODM_REG_EDCCA_DCNF_11N 0xE24
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#define ODM_REG_TAP_UPD_97F 0xE24
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#define ODM_REG_FPGA0_IQK_11N 0xE28
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#define ODM_REG_PAGE_B1_97F 0xE28
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#define ODM_REG_TXIQK_TONE_A_11N 0xE30
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#define ODM_REG_RXIQK_TONE_A_11N 0xE34
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#define ODM_REG_TXIQK_PI_A_11N 0xE38
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#define ODM_REG_RXIQK_PI_A_11N 0xE3C
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#define ODM_REG_TXIQK_11N 0xE40
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#define ODM_REG_RXIQK_11N 0xE44
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#define ODM_REG_IQK_AGC_PTS_11N 0xE48
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#define ODM_REG_IQK_AGC_RSP_11N 0xE4C
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#define ODM_REG_BLUETOOTH_11N 0xE6C
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#define ODM_REG_RX_WAIT_CCA_11N 0xE70
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#define ODM_REG_TX_CCK_RFON_11N 0xE74
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#define ODM_REG_TX_CCK_BBON_11N 0xE78
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#define ODM_REG_OFDM_RFON_11N 0xE7C
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#define ODM_REG_OFDM_BBON_11N 0xE80
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#define ODM_REG_TX2RX_11N 0xE84
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#define ODM_REG_TX2TX_11N 0xE88
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#define ODM_REG_RX_CCK_11N 0xE8C
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#define ODM_REG_RX_OFDM_11N 0xED0
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#define ODM_REG_RX_WAIT_RIFS_11N 0xED4
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#define ODM_REG_RX2RX_11N 0xED8
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#define ODM_REG_STANDBY_11N 0xEDC
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#define ODM_REG_SLEEP_11N 0xEE0
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#define ODM_REG_PMPD_ANAEN_11N 0xEEC
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/* PAGE F */
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#define ODM_REG_PAGE_F_RST_11N 0xF14
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#define ODM_REG_IGI_C_11N 0xF84
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#define ODM_REG_IGI_D_11N 0xF88
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#define ODM_REG_CCK_CRC32_ERROR_CNT_11N 0xF84
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#define ODM_REG_CCK_CRC32_OK_CNT_11N 0xF88
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#define ODM_REG_HT_CRC32_CNT_11N 0xF90
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#define ODM_REG_OFDM_CRC32_CNT_11N 0xF94
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#define ODM_REG_HT_CRC32_CNT_11N_AGG 0xFB8
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/* @2 MAC REG LIST */
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#define ODM_REG_BB_RST_11N 0x02
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#define ODM_REG_ANTSEL_PIN_11N 0x4C
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#define ODM_REG_EARLY_MODE_11N 0x4D0
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#define ODM_REG_RSSI_MONITOR_11N 0x4FE
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#define ODM_REG_EDCA_VO_11N 0x500
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#define ODM_REG_EDCA_VI_11N 0x504
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#define ODM_REG_EDCA_BE_11N 0x508
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#define ODM_REG_EDCA_BK_11N 0x50C
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#define ODM_REG_TXPAUSE_11N 0x522
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#define ODM_REG_RESP_TX_11N 0x6D8
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#define ODM_REG_ANT_TRAIN_PARA1_11N 0x7b0
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#define ODM_REG_ANT_TRAIN_PARA2_11N 0x7b4
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/* @DIG Related */
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#define ODM_BIT_IGI_11N 0x0000007F
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#define ODM_BIT_CCK_RPT_FORMAT_11N BIT(9)
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#define ODM_BIT_BB_RX_PATH_11N 0xF
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#define ODM_BIT_BB_TX_PATH_11N 0xF
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#define ODM_BIT_BB_ATC_11N BIT(11)
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#endif
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